1*4299f85aSLars Povlsen /* SPDX-License-Identifier: GPL-2.0-only */ 2*4299f85aSLars Povlsen /* 3*4299f85aSLars Povlsen * Copyright (c) 2019 Microchip Inc. 4*4299f85aSLars Povlsen * 5*4299f85aSLars Povlsen * Author: Lars Povlsen <lars.povlsen@microchip.com> 6*4299f85aSLars Povlsen */ 7*4299f85aSLars Povlsen 8*4299f85aSLars Povlsen #ifndef _DT_BINDINGS_CLK_SPARX5_H 9*4299f85aSLars Povlsen #define _DT_BINDINGS_CLK_SPARX5_H 10*4299f85aSLars Povlsen 11*4299f85aSLars Povlsen #define CLK_ID_CORE 0 12*4299f85aSLars Povlsen #define CLK_ID_DDR 1 13*4299f85aSLars Povlsen #define CLK_ID_CPU2 2 14*4299f85aSLars Povlsen #define CLK_ID_ARM2 3 15*4299f85aSLars Povlsen #define CLK_ID_AUX1 4 16*4299f85aSLars Povlsen #define CLK_ID_AUX2 5 17*4299f85aSLars Povlsen #define CLK_ID_AUX3 6 18*4299f85aSLars Povlsen #define CLK_ID_AUX4 7 19*4299f85aSLars Povlsen #define CLK_ID_SYNCE 8 20*4299f85aSLars Povlsen 21*4299f85aSLars Povlsen #define N_CLOCKS 9 22*4299f85aSLars Povlsen 23*4299f85aSLars Povlsen #endif 24