17a29a869SCarlo Caione /* 27a29a869SCarlo Caione * Meson8b clock tree IDs 37a29a869SCarlo Caione */ 47a29a869SCarlo Caione 57a29a869SCarlo Caione #ifndef __MESON8B_CLKC_H 67a29a869SCarlo Caione #define __MESON8B_CLKC_H 77a29a869SCarlo Caione 87a29a869SCarlo Caione #define CLKID_UNUSED 0 97a29a869SCarlo Caione #define CLKID_XTAL 1 107a29a869SCarlo Caione #define CLKID_PLL_FIXED 2 117a29a869SCarlo Caione #define CLKID_PLL_VID 3 127a29a869SCarlo Caione #define CLKID_PLL_SYS 4 137a29a869SCarlo Caione #define CLKID_FCLK_DIV2 5 147a29a869SCarlo Caione #define CLKID_FCLK_DIV3 6 157a29a869SCarlo Caione #define CLKID_FCLK_DIV4 7 167a29a869SCarlo Caione #define CLKID_FCLK_DIV5 8 177a29a869SCarlo Caione #define CLKID_FCLK_DIV7 9 187a29a869SCarlo Caione #define CLKID_CLK81 10 197a29a869SCarlo Caione #define CLKID_MALI 11 207a29a869SCarlo Caione #define CLKID_CPUCLK 12 217a29a869SCarlo Caione #define CLKID_ZERO 13 22c0daa3e6SMichael Turquette #define CLKID_MPEG_SEL 14 23c0daa3e6SMichael Turquette #define CLKID_MPEG_DIV 15 2470ad0d03SMartin Blumenstingl #define CLKID_SAR_ADC 23 2506eff6a7SMartin Blumenstingl #define CLKID_RNG0 25 26e2e5f321SMartin Blumenstingl #define CLKID_SDIO 30 27c22f06d3SMartin Blumenstingl #define CLKID_ETH 36 28677f6af5SMartin Blumenstingl #define CLKID_USB0 50 29677f6af5SMartin Blumenstingl #define CLKID_USB1 51 30677f6af5SMartin Blumenstingl #define CLKID_USB 55 31677f6af5SMartin Blumenstingl #define CLKID_USB1_DDR_BRIDGE 64 32677f6af5SMartin Blumenstingl #define CLKID_USB0_DDR_BRIDGE 65 3370ad0d03SMartin Blumenstingl #define CLKID_SANA 69 347a29a869SCarlo Caione 357a29a869SCarlo Caione #endif /* __MESON8B_CLKC_H */ 36