17a29a869SCarlo Caione /*
27a29a869SCarlo Caione  * Meson8b clock tree IDs
37a29a869SCarlo Caione  */
47a29a869SCarlo Caione 
57a29a869SCarlo Caione #ifndef __MESON8B_CLKC_H
67a29a869SCarlo Caione #define __MESON8B_CLKC_H
77a29a869SCarlo Caione 
87a29a869SCarlo Caione #define CLKID_UNUSED		0
97a29a869SCarlo Caione #define CLKID_XTAL		1
107a29a869SCarlo Caione #define CLKID_PLL_FIXED		2
117a29a869SCarlo Caione #define CLKID_PLL_VID		3
127a29a869SCarlo Caione #define CLKID_PLL_SYS		4
137a29a869SCarlo Caione #define CLKID_FCLK_DIV2		5
147a29a869SCarlo Caione #define CLKID_FCLK_DIV3		6
157a29a869SCarlo Caione #define CLKID_FCLK_DIV4		7
167a29a869SCarlo Caione #define CLKID_FCLK_DIV5		8
177a29a869SCarlo Caione #define CLKID_FCLK_DIV7		9
187a29a869SCarlo Caione #define CLKID_CLK81		10
197a29a869SCarlo Caione #define CLKID_MALI		11
207a29a869SCarlo Caione #define CLKID_CPUCLK		12
217a29a869SCarlo Caione #define CLKID_ZERO		13
22c0daa3e6SMichael Turquette #define CLKID_MPEG_SEL		14
23c0daa3e6SMichael Turquette #define CLKID_MPEG_DIV		15
247a29a869SCarlo Caione 
25c0daa3e6SMichael Turquette #define CLK_NR_CLKS		(CLKID_MPEG_DIV + 1)
267a29a869SCarlo Caione 
277a29a869SCarlo Caione #endif /* __MESON8B_CLKC_H */
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