17a29a869SCarlo Caione /* 27a29a869SCarlo Caione * Meson8b clock tree IDs 37a29a869SCarlo Caione */ 47a29a869SCarlo Caione 57a29a869SCarlo Caione #ifndef __MESON8B_CLKC_H 67a29a869SCarlo Caione #define __MESON8B_CLKC_H 77a29a869SCarlo Caione 87a29a869SCarlo Caione #define CLKID_UNUSED 0 97a29a869SCarlo Caione #define CLKID_XTAL 1 107a29a869SCarlo Caione #define CLKID_PLL_FIXED 2 117a29a869SCarlo Caione #define CLKID_PLL_VID 3 127a29a869SCarlo Caione #define CLKID_PLL_SYS 4 137a29a869SCarlo Caione #define CLKID_FCLK_DIV2 5 147a29a869SCarlo Caione #define CLKID_FCLK_DIV3 6 157a29a869SCarlo Caione #define CLKID_FCLK_DIV4 7 167a29a869SCarlo Caione #define CLKID_FCLK_DIV5 8 177a29a869SCarlo Caione #define CLKID_FCLK_DIV7 9 187a29a869SCarlo Caione #define CLKID_CLK81 10 197a29a869SCarlo Caione #define CLKID_MALI 11 207a29a869SCarlo Caione #define CLKID_CPUCLK 12 217a29a869SCarlo Caione #define CLKID_ZERO 13 22c0daa3e6SMichael Turquette #define CLKID_MPEG_SEL 14 23c0daa3e6SMichael Turquette #define CLKID_MPEG_DIV 15 2431128822SJerome Brunet #define CLKID_DDR 16 2531128822SJerome Brunet #define CLKID_DOS 17 2631128822SJerome Brunet #define CLKID_ISA 18 2731128822SJerome Brunet #define CLKID_PL301 19 2831128822SJerome Brunet #define CLKID_PERIPHS 20 2931128822SJerome Brunet #define CLKID_SPICC 21 3031128822SJerome Brunet #define CLKID_I2C 22 3170ad0d03SMartin Blumenstingl #define CLKID_SAR_ADC 23 3231128822SJerome Brunet #define CLKID_SMART_CARD 24 3306eff6a7SMartin Blumenstingl #define CLKID_RNG0 25 3431128822SJerome Brunet #define CLKID_UART0 26 3531128822SJerome Brunet #define CLKID_SDHC 27 3631128822SJerome Brunet #define CLKID_STREAM 28 3731128822SJerome Brunet #define CLKID_ASYNC_FIFO 29 38e2e5f321SMartin Blumenstingl #define CLKID_SDIO 30 3931128822SJerome Brunet #define CLKID_ABUF 31 4031128822SJerome Brunet #define CLKID_HIU_IFACE 32 4131128822SJerome Brunet #define CLKID_ASSIST_MISC 33 4231128822SJerome Brunet #define CLKID_SPI 34 4331128822SJerome Brunet #define CLKID_I2S_SPDIF 35 44c22f06d3SMartin Blumenstingl #define CLKID_ETH 36 4531128822SJerome Brunet #define CLKID_DEMUX 37 4631128822SJerome Brunet #define CLKID_AIU_GLUE 38 4731128822SJerome Brunet #define CLKID_IEC958 39 4831128822SJerome Brunet #define CLKID_I2S_OUT 40 4931128822SJerome Brunet #define CLKID_AMCLK 41 5031128822SJerome Brunet #define CLKID_AIFIFO2 42 5131128822SJerome Brunet #define CLKID_MIXER 43 5231128822SJerome Brunet #define CLKID_MIXER_IFACE 44 5331128822SJerome Brunet #define CLKID_ADC 45 5431128822SJerome Brunet #define CLKID_BLKMV 46 5531128822SJerome Brunet #define CLKID_AIU 47 5631128822SJerome Brunet #define CLKID_UART1 48 5731128822SJerome Brunet #define CLKID_G2D 49 58677f6af5SMartin Blumenstingl #define CLKID_USB0 50 59677f6af5SMartin Blumenstingl #define CLKID_USB1 51 6031128822SJerome Brunet #define CLKID_RESET 52 6131128822SJerome Brunet #define CLKID_NAND 53 6231128822SJerome Brunet #define CLKID_DOS_PARSER 54 63677f6af5SMartin Blumenstingl #define CLKID_USB 55 6431128822SJerome Brunet #define CLKID_VDIN1 56 6531128822SJerome Brunet #define CLKID_AHB_ARB0 57 6631128822SJerome Brunet #define CLKID_EFUSE 58 6731128822SJerome Brunet #define CLKID_BOOT_ROM 59 6831128822SJerome Brunet #define CLKID_AHB_DATA_BUS 60 6931128822SJerome Brunet #define CLKID_AHB_CTRL_BUS 61 7031128822SJerome Brunet #define CLKID_HDMI_INTR_SYNC 62 7131128822SJerome Brunet #define CLKID_HDMI_PCLK 63 72677f6af5SMartin Blumenstingl #define CLKID_USB1_DDR_BRIDGE 64 73677f6af5SMartin Blumenstingl #define CLKID_USB0_DDR_BRIDGE 65 7431128822SJerome Brunet #define CLKID_MMC_PCLK 66 7531128822SJerome Brunet #define CLKID_DVIN 67 7631128822SJerome Brunet #define CLKID_UART2 68 7770ad0d03SMartin Blumenstingl #define CLKID_SANA 69 7831128822SJerome Brunet #define CLKID_VPU_INTR 70 7931128822SJerome Brunet #define CLKID_SEC_AHB_AHB3_BRIDGE 71 8031128822SJerome Brunet #define CLKID_CLK81_A9 72 8131128822SJerome Brunet #define CLKID_VCLK2_VENCI0 73 8231128822SJerome Brunet #define CLKID_VCLK2_VENCI1 74 8331128822SJerome Brunet #define CLKID_VCLK2_VENCP0 75 8431128822SJerome Brunet #define CLKID_VCLK2_VENCP1 76 8531128822SJerome Brunet #define CLKID_GCLK_VENCI_INT 77 8631128822SJerome Brunet #define CLKID_GCLK_VENCP_INT 78 8731128822SJerome Brunet #define CLKID_DAC_CLK 79 8831128822SJerome Brunet #define CLKID_AOCLK_GATE 80 8931128822SJerome Brunet #define CLKID_IEC958_GATE 81 9031128822SJerome Brunet #define CLKID_ENC480P 82 9131128822SJerome Brunet #define CLKID_RNG1 83 9231128822SJerome Brunet #define CLKID_GCLK_VENCL_INT 84 9331128822SJerome Brunet #define CLKID_VCLK2_VENCLMCC 85 9431128822SJerome Brunet #define CLKID_VCLK2_VENCL 86 9531128822SJerome Brunet #define CLKID_VCLK2_OTHER 87 9631128822SJerome Brunet #define CLKID_EDP 88 9731128822SJerome Brunet #define CLKID_AO_MEDIA_CPU 89 9831128822SJerome Brunet #define CLKID_AO_AHB_SRAM 90 9931128822SJerome Brunet #define CLKID_AO_AHB_BUS 91 10031128822SJerome Brunet #define CLKID_AO_IFACE 92 10131128822SJerome Brunet #define CLKID_MPLL0 93 10231128822SJerome Brunet #define CLKID_MPLL1 94 10331128822SJerome Brunet #define CLKID_MPLL2 95 1047a29a869SCarlo Caione 1057a29a869SCarlo Caione #endif /* __MESON8B_CLKC_H */ 106