1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 27a29a869SCarlo Caione /* 37a29a869SCarlo Caione * Meson8b clock tree IDs 47a29a869SCarlo Caione */ 57a29a869SCarlo Caione 67a29a869SCarlo Caione #ifndef __MESON8B_CLKC_H 77a29a869SCarlo Caione #define __MESON8B_CLKC_H 87a29a869SCarlo Caione 97a29a869SCarlo Caione #define CLKID_UNUSED 0 107a29a869SCarlo Caione #define CLKID_XTAL 1 117a29a869SCarlo Caione #define CLKID_PLL_FIXED 2 127a29a869SCarlo Caione #define CLKID_PLL_VID 3 137a29a869SCarlo Caione #define CLKID_PLL_SYS 4 147a29a869SCarlo Caione #define CLKID_FCLK_DIV2 5 157a29a869SCarlo Caione #define CLKID_FCLK_DIV3 6 167a29a869SCarlo Caione #define CLKID_FCLK_DIV4 7 177a29a869SCarlo Caione #define CLKID_FCLK_DIV5 8 187a29a869SCarlo Caione #define CLKID_FCLK_DIV7 9 197a29a869SCarlo Caione #define CLKID_CLK81 10 207a29a869SCarlo Caione #define CLKID_MALI 11 217a29a869SCarlo Caione #define CLKID_CPUCLK 12 227a29a869SCarlo Caione #define CLKID_ZERO 13 23c0daa3e6SMichael Turquette #define CLKID_MPEG_SEL 14 24c0daa3e6SMichael Turquette #define CLKID_MPEG_DIV 15 2531128822SJerome Brunet #define CLKID_DDR 16 2631128822SJerome Brunet #define CLKID_DOS 17 2731128822SJerome Brunet #define CLKID_ISA 18 2831128822SJerome Brunet #define CLKID_PL301 19 2931128822SJerome Brunet #define CLKID_PERIPHS 20 3031128822SJerome Brunet #define CLKID_SPICC 21 3131128822SJerome Brunet #define CLKID_I2C 22 3270ad0d03SMartin Blumenstingl #define CLKID_SAR_ADC 23 3331128822SJerome Brunet #define CLKID_SMART_CARD 24 3406eff6a7SMartin Blumenstingl #define CLKID_RNG0 25 3531128822SJerome Brunet #define CLKID_UART0 26 3631128822SJerome Brunet #define CLKID_SDHC 27 3731128822SJerome Brunet #define CLKID_STREAM 28 3831128822SJerome Brunet #define CLKID_ASYNC_FIFO 29 39e2e5f321SMartin Blumenstingl #define CLKID_SDIO 30 4031128822SJerome Brunet #define CLKID_ABUF 31 4131128822SJerome Brunet #define CLKID_HIU_IFACE 32 4231128822SJerome Brunet #define CLKID_ASSIST_MISC 33 4331128822SJerome Brunet #define CLKID_SPI 34 4431128822SJerome Brunet #define CLKID_I2S_SPDIF 35 45c22f06d3SMartin Blumenstingl #define CLKID_ETH 36 4631128822SJerome Brunet #define CLKID_DEMUX 37 4731128822SJerome Brunet #define CLKID_AIU_GLUE 38 4831128822SJerome Brunet #define CLKID_IEC958 39 4931128822SJerome Brunet #define CLKID_I2S_OUT 40 5031128822SJerome Brunet #define CLKID_AMCLK 41 5131128822SJerome Brunet #define CLKID_AIFIFO2 42 5231128822SJerome Brunet #define CLKID_MIXER 43 5331128822SJerome Brunet #define CLKID_MIXER_IFACE 44 5431128822SJerome Brunet #define CLKID_ADC 45 5531128822SJerome Brunet #define CLKID_BLKMV 46 5631128822SJerome Brunet #define CLKID_AIU 47 5731128822SJerome Brunet #define CLKID_UART1 48 5831128822SJerome Brunet #define CLKID_G2D 49 59677f6af5SMartin Blumenstingl #define CLKID_USB0 50 60677f6af5SMartin Blumenstingl #define CLKID_USB1 51 6131128822SJerome Brunet #define CLKID_RESET 52 6231128822SJerome Brunet #define CLKID_NAND 53 6331128822SJerome Brunet #define CLKID_DOS_PARSER 54 64677f6af5SMartin Blumenstingl #define CLKID_USB 55 6531128822SJerome Brunet #define CLKID_VDIN1 56 6631128822SJerome Brunet #define CLKID_AHB_ARB0 57 6731128822SJerome Brunet #define CLKID_EFUSE 58 6831128822SJerome Brunet #define CLKID_BOOT_ROM 59 6931128822SJerome Brunet #define CLKID_AHB_DATA_BUS 60 7031128822SJerome Brunet #define CLKID_AHB_CTRL_BUS 61 7131128822SJerome Brunet #define CLKID_HDMI_INTR_SYNC 62 7231128822SJerome Brunet #define CLKID_HDMI_PCLK 63 73677f6af5SMartin Blumenstingl #define CLKID_USB1_DDR_BRIDGE 64 74677f6af5SMartin Blumenstingl #define CLKID_USB0_DDR_BRIDGE 65 7531128822SJerome Brunet #define CLKID_MMC_PCLK 66 7631128822SJerome Brunet #define CLKID_DVIN 67 7731128822SJerome Brunet #define CLKID_UART2 68 7870ad0d03SMartin Blumenstingl #define CLKID_SANA 69 7931128822SJerome Brunet #define CLKID_VPU_INTR 70 8031128822SJerome Brunet #define CLKID_SEC_AHB_AHB3_BRIDGE 71 8131128822SJerome Brunet #define CLKID_CLK81_A9 72 8231128822SJerome Brunet #define CLKID_VCLK2_VENCI0 73 8331128822SJerome Brunet #define CLKID_VCLK2_VENCI1 74 8431128822SJerome Brunet #define CLKID_VCLK2_VENCP0 75 8531128822SJerome Brunet #define CLKID_VCLK2_VENCP1 76 8631128822SJerome Brunet #define CLKID_GCLK_VENCI_INT 77 8731128822SJerome Brunet #define CLKID_GCLK_VENCP_INT 78 8831128822SJerome Brunet #define CLKID_DAC_CLK 79 8931128822SJerome Brunet #define CLKID_AOCLK_GATE 80 9031128822SJerome Brunet #define CLKID_IEC958_GATE 81 9131128822SJerome Brunet #define CLKID_ENC480P 82 9231128822SJerome Brunet #define CLKID_RNG1 83 9331128822SJerome Brunet #define CLKID_GCLK_VENCL_INT 84 9431128822SJerome Brunet #define CLKID_VCLK2_VENCLMCC 85 9531128822SJerome Brunet #define CLKID_VCLK2_VENCL 86 9631128822SJerome Brunet #define CLKID_VCLK2_OTHER 87 9731128822SJerome Brunet #define CLKID_EDP 88 9831128822SJerome Brunet #define CLKID_AO_MEDIA_CPU 89 9931128822SJerome Brunet #define CLKID_AO_AHB_SRAM 90 10031128822SJerome Brunet #define CLKID_AO_AHB_BUS 91 10131128822SJerome Brunet #define CLKID_AO_IFACE 92 10231128822SJerome Brunet #define CLKID_MPLL0 93 10331128822SJerome Brunet #define CLKID_MPLL1 94 10431128822SJerome Brunet #define CLKID_MPLL2 95 10509e19d73SMartin Blumenstingl #define CLKID_NAND_CLK 112 1067a29a869SCarlo Caione 1077a29a869SCarlo Caione #endif /* __MESON8B_CLKC_H */ 108