1 #ifndef __DTS_MARVELL_PXA168_CLOCK_H
2 #define __DTS_MARVELL_PXA168_CLOCK_H
3 
4 /* fixed clocks and plls */
5 #define PXA168_CLK_CLK32		1
6 #define PXA168_CLK_VCTCXO		2
7 #define PXA168_CLK_PLL1			3
8 #define PXA168_CLK_PLL1_2		8
9 #define PXA168_CLK_PLL1_4		9
10 #define PXA168_CLK_PLL1_8		10
11 #define PXA168_CLK_PLL1_16		11
12 #define PXA168_CLK_PLL1_6		12
13 #define PXA168_CLK_PLL1_12		13
14 #define PXA168_CLK_PLL1_24		14
15 #define PXA168_CLK_PLL1_48		15
16 #define PXA168_CLK_PLL1_96		16
17 #define PXA168_CLK_PLL1_13		17
18 #define PXA168_CLK_PLL1_13_1_5		18
19 #define PXA168_CLK_PLL1_2_1_5		19
20 #define PXA168_CLK_PLL1_3_16		20
21 #define PXA168_CLK_UART_PLL		27
22 
23 /* apb periphrals */
24 #define PXA168_CLK_TWSI0		60
25 #define PXA168_CLK_TWSI1		61
26 #define PXA168_CLK_TWSI2		62
27 #define PXA168_CLK_TWSI3		63
28 #define PXA168_CLK_GPIO			64
29 #define PXA168_CLK_KPC			65
30 #define PXA168_CLK_RTC			66
31 #define PXA168_CLK_PWM0			67
32 #define PXA168_CLK_PWM1			68
33 #define PXA168_CLK_PWM2			69
34 #define PXA168_CLK_PWM3			70
35 #define PXA168_CLK_UART0		71
36 #define PXA168_CLK_UART1		72
37 #define PXA168_CLK_UART2		73
38 #define PXA168_CLK_SSP0			74
39 #define PXA168_CLK_SSP1			75
40 #define PXA168_CLK_SSP2			76
41 #define PXA168_CLK_SSP3			77
42 #define PXA168_CLK_SSP4			78
43 
44 /* axi periphrals */
45 #define PXA168_CLK_DFC			100
46 #define PXA168_CLK_SDH0			101
47 #define PXA168_CLK_SDH1			102
48 #define PXA168_CLK_SDH2			103
49 #define PXA168_CLK_USB			104
50 #define PXA168_CLK_SPH			105
51 #define PXA168_CLK_DISP0		106
52 #define PXA168_CLK_CCIC0		107
53 #define PXA168_CLK_CCIC0_PHY		108
54 #define PXA168_CLK_CCIC0_SPHY		109
55 
56 #define PXA168_NR_CLKS			200
57 #endif
58