12bc61da9SChao Xie #ifndef __DTS_MARVELL_PXA910_CLOCK_H 22bc61da9SChao Xie #define __DTS_MARVELL_PXA910_CLOCK_H 32bc61da9SChao Xie 42bc61da9SChao Xie /* fixed clocks and plls */ 52bc61da9SChao Xie #define PXA910_CLK_CLK32 1 62bc61da9SChao Xie #define PXA910_CLK_VCTCXO 2 72bc61da9SChao Xie #define PXA910_CLK_PLL1 3 82bc61da9SChao Xie #define PXA910_CLK_PLL1_2 8 92bc61da9SChao Xie #define PXA910_CLK_PLL1_4 9 102bc61da9SChao Xie #define PXA910_CLK_PLL1_8 10 112bc61da9SChao Xie #define PXA910_CLK_PLL1_16 11 122bc61da9SChao Xie #define PXA910_CLK_PLL1_6 12 132bc61da9SChao Xie #define PXA910_CLK_PLL1_12 13 142bc61da9SChao Xie #define PXA910_CLK_PLL1_24 14 152bc61da9SChao Xie #define PXA910_CLK_PLL1_48 15 162bc61da9SChao Xie #define PXA910_CLK_PLL1_96 16 172bc61da9SChao Xie #define PXA910_CLK_PLL1_13 17 182bc61da9SChao Xie #define PXA910_CLK_PLL1_13_1_5 18 192bc61da9SChao Xie #define PXA910_CLK_PLL1_2_1_5 19 202bc61da9SChao Xie #define PXA910_CLK_PLL1_3_16 20 2124c65a02SChao Xie #define PXA910_CLK_PLL1_192 21 222bc61da9SChao Xie #define PXA910_CLK_UART_PLL 27 23a35247c6SChao Xie #define PXA910_CLK_USB_PLL 28 242bc61da9SChao Xie 252bc61da9SChao Xie /* apb periphrals */ 262bc61da9SChao Xie #define PXA910_CLK_TWSI0 60 272bc61da9SChao Xie #define PXA910_CLK_TWSI1 61 282bc61da9SChao Xie #define PXA910_CLK_TWSI2 62 292bc61da9SChao Xie #define PXA910_CLK_TWSI3 63 302bc61da9SChao Xie #define PXA910_CLK_GPIO 64 312bc61da9SChao Xie #define PXA910_CLK_KPC 65 322bc61da9SChao Xie #define PXA910_CLK_RTC 66 332bc61da9SChao Xie #define PXA910_CLK_PWM0 67 342bc61da9SChao Xie #define PXA910_CLK_PWM1 68 352bc61da9SChao Xie #define PXA910_CLK_PWM2 69 362bc61da9SChao Xie #define PXA910_CLK_PWM3 70 372bc61da9SChao Xie #define PXA910_CLK_UART0 71 382bc61da9SChao Xie #define PXA910_CLK_UART1 72 392bc61da9SChao Xie #define PXA910_CLK_UART2 73 402bc61da9SChao Xie #define PXA910_CLK_SSP0 74 412bc61da9SChao Xie #define PXA910_CLK_SSP1 75 4224c65a02SChao Xie #define PXA910_CLK_TIMER0 76 4324c65a02SChao Xie #define PXA910_CLK_TIMER1 77 442bc61da9SChao Xie 452bc61da9SChao Xie /* axi periphrals */ 462bc61da9SChao Xie #define PXA910_CLK_DFC 100 472bc61da9SChao Xie #define PXA910_CLK_SDH0 101 482bc61da9SChao Xie #define PXA910_CLK_SDH1 102 492bc61da9SChao Xie #define PXA910_CLK_SDH2 103 502bc61da9SChao Xie #define PXA910_CLK_USB 104 512bc61da9SChao Xie #define PXA910_CLK_SPH 105 522bc61da9SChao Xie #define PXA910_CLK_DISP0 106 532bc61da9SChao Xie #define PXA910_CLK_CCIC0 107 542bc61da9SChao Xie #define PXA910_CLK_CCIC0_PHY 108 552bc61da9SChao Xie #define PXA910_CLK_CCIC0_SPHY 109 562bc61da9SChao Xie 572bc61da9SChao Xie #define PXA910_NR_CLKS 200 582bc61da9SChao Xie #endif 59