1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2ab08aefcSChao Xie #ifndef __DTS_MARVELL_PXA168_CLOCK_H 3ab08aefcSChao Xie #define __DTS_MARVELL_PXA168_CLOCK_H 4ab08aefcSChao Xie 5ab08aefcSChao Xie /* fixed clocks and plls */ 6ab08aefcSChao Xie #define PXA168_CLK_CLK32 1 7ab08aefcSChao Xie #define PXA168_CLK_VCTCXO 2 8ab08aefcSChao Xie #define PXA168_CLK_PLL1 3 9ab08aefcSChao Xie #define PXA168_CLK_PLL1_2 8 10ab08aefcSChao Xie #define PXA168_CLK_PLL1_4 9 11ab08aefcSChao Xie #define PXA168_CLK_PLL1_8 10 12ab08aefcSChao Xie #define PXA168_CLK_PLL1_16 11 13ab08aefcSChao Xie #define PXA168_CLK_PLL1_6 12 14ab08aefcSChao Xie #define PXA168_CLK_PLL1_12 13 15ab08aefcSChao Xie #define PXA168_CLK_PLL1_24 14 16ab08aefcSChao Xie #define PXA168_CLK_PLL1_48 15 17ab08aefcSChao Xie #define PXA168_CLK_PLL1_96 16 18ab08aefcSChao Xie #define PXA168_CLK_PLL1_13 17 19ab08aefcSChao Xie #define PXA168_CLK_PLL1_13_1_5 18 20ab08aefcSChao Xie #define PXA168_CLK_PLL1_2_1_5 19 21ab08aefcSChao Xie #define PXA168_CLK_PLL1_3_16 20 2224c65a02SChao Xie #define PXA168_CLK_PLL1_192 21 23260d2f34SDoug Brown #define PXA168_CLK_PLL1_2_1_10 22 24260d2f34SDoug Brown #define PXA168_CLK_PLL1_2_3_16 23 25ab08aefcSChao Xie #define PXA168_CLK_UART_PLL 27 26a35247c6SChao Xie #define PXA168_CLK_USB_PLL 28 27260d2f34SDoug Brown #define PXA168_CLK_CLK32_2 50 28ab08aefcSChao Xie 296853feceSTom Rix /* apb peripherals */ 30ab08aefcSChao Xie #define PXA168_CLK_TWSI0 60 31ab08aefcSChao Xie #define PXA168_CLK_TWSI1 61 32ab08aefcSChao Xie #define PXA168_CLK_TWSI2 62 33ab08aefcSChao Xie #define PXA168_CLK_TWSI3 63 34ab08aefcSChao Xie #define PXA168_CLK_GPIO 64 35ab08aefcSChao Xie #define PXA168_CLK_KPC 65 36ab08aefcSChao Xie #define PXA168_CLK_RTC 66 37ab08aefcSChao Xie #define PXA168_CLK_PWM0 67 38ab08aefcSChao Xie #define PXA168_CLK_PWM1 68 39ab08aefcSChao Xie #define PXA168_CLK_PWM2 69 40ab08aefcSChao Xie #define PXA168_CLK_PWM3 70 41ab08aefcSChao Xie #define PXA168_CLK_UART0 71 42ab08aefcSChao Xie #define PXA168_CLK_UART1 72 43ab08aefcSChao Xie #define PXA168_CLK_UART2 73 44ab08aefcSChao Xie #define PXA168_CLK_SSP0 74 45ab08aefcSChao Xie #define PXA168_CLK_SSP1 75 46ab08aefcSChao Xie #define PXA168_CLK_SSP2 76 47ab08aefcSChao Xie #define PXA168_CLK_SSP3 77 48ab08aefcSChao Xie #define PXA168_CLK_SSP4 78 4924c65a02SChao Xie #define PXA168_CLK_TIMER 79 50ab08aefcSChao Xie 516853feceSTom Rix /* axi peripherals */ 52ab08aefcSChao Xie #define PXA168_CLK_DFC 100 53ab08aefcSChao Xie #define PXA168_CLK_SDH0 101 54ab08aefcSChao Xie #define PXA168_CLK_SDH1 102 55ab08aefcSChao Xie #define PXA168_CLK_SDH2 103 56ab08aefcSChao Xie #define PXA168_CLK_USB 104 57ab08aefcSChao Xie #define PXA168_CLK_SPH 105 58ab08aefcSChao Xie #define PXA168_CLK_DISP0 106 59ab08aefcSChao Xie #define PXA168_CLK_CCIC0 107 60ab08aefcSChao Xie #define PXA168_CLK_CCIC0_PHY 108 61ab08aefcSChao Xie #define PXA168_CLK_CCIC0_SPHY 109 62ca41820bSDoug Brown #define PXA168_CLK_SDH3 110 63*238e73edSDoug Brown #define PXA168_CLK_SDH01_AXI 111 64*238e73edSDoug Brown #define PXA168_CLK_SDH23_AXI 112 65ab08aefcSChao Xie 66ab08aefcSChao Xie #define PXA168_NR_CLKS 200 67ab08aefcSChao Xie #endif 68