1*12de2f50SKeguang Zhang /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2*12de2f50SKeguang Zhang /*
3*12de2f50SKeguang Zhang  * Loongson-1 clock tree IDs
4*12de2f50SKeguang Zhang  *
5*12de2f50SKeguang Zhang  * Copyright (C) 2023 Keguang Zhang <keguang.zhang@gmail.com>
6*12de2f50SKeguang Zhang  */
7*12de2f50SKeguang Zhang 
8*12de2f50SKeguang Zhang #ifndef __DT_BINDINGS_CLOCK_LS1X_CLK_H__
9*12de2f50SKeguang Zhang #define __DT_BINDINGS_CLOCK_LS1X_CLK_H__
10*12de2f50SKeguang Zhang 
11*12de2f50SKeguang Zhang #define LS1X_CLKID_PLL	0
12*12de2f50SKeguang Zhang #define LS1X_CLKID_CPU	1
13*12de2f50SKeguang Zhang #define LS1X_CLKID_DC	2
14*12de2f50SKeguang Zhang #define LS1X_CLKID_AHB	3
15*12de2f50SKeguang Zhang #define LS1X_CLKID_APB	4
16*12de2f50SKeguang Zhang 
17*12de2f50SKeguang Zhang #define CLK_NR_CLKS	(LS1X_CLKID_APB + 1)
18*12de2f50SKeguang Zhang 
19*12de2f50SKeguang Zhang #endif /* __DT_BINDINGS_CLOCK_LS1X_CLK_H__ */
20