1*0384759bSLukas Bulwahn /* SPDX-License-Identifier: GPL-2.0 */ 2*0384759bSLukas Bulwahn /* 3*0384759bSLukas Bulwahn * Device Tree defines for Lochnagar clocking 4*0384759bSLukas Bulwahn * 5*0384759bSLukas Bulwahn * Copyright (c) 2017-2018 Cirrus Logic, Inc. and 6*0384759bSLukas Bulwahn * Cirrus Logic International Semiconductor Ltd. 7*0384759bSLukas Bulwahn * 8*0384759bSLukas Bulwahn * Author: Charles Keepax <ckeepax@opensource.cirrus.com> 9*0384759bSLukas Bulwahn */ 10*0384759bSLukas Bulwahn 11*0384759bSLukas Bulwahn #ifndef DT_BINDINGS_CLK_LOCHNAGAR_H 12*0384759bSLukas Bulwahn #define DT_BINDINGS_CLK_LOCHNAGAR_H 13*0384759bSLukas Bulwahn 14*0384759bSLukas Bulwahn #define LOCHNAGAR_CDC_MCLK1 0 15*0384759bSLukas Bulwahn #define LOCHNAGAR_CDC_MCLK2 1 16*0384759bSLukas Bulwahn #define LOCHNAGAR_DSP_CLKIN 2 17*0384759bSLukas Bulwahn #define LOCHNAGAR_GF_CLKOUT1 3 18*0384759bSLukas Bulwahn #define LOCHNAGAR_GF_CLKOUT2 4 19*0384759bSLukas Bulwahn #define LOCHNAGAR_PSIA1_MCLK 5 20*0384759bSLukas Bulwahn #define LOCHNAGAR_PSIA2_MCLK 6 21*0384759bSLukas Bulwahn #define LOCHNAGAR_SPDIF_MCLK 7 22*0384759bSLukas Bulwahn #define LOCHNAGAR_ADAT_MCLK 8 23*0384759bSLukas Bulwahn #define LOCHNAGAR_SOUNDCARD_MCLK 9 24*0384759bSLukas Bulwahn #define LOCHNAGAR_SPDIF_CLKOUT 10 25*0384759bSLukas Bulwahn 26*0384759bSLukas Bulwahn #endif 27