1e2266f4cSRahul Tanwar /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2e2266f4cSRahul Tanwar /* 3e2266f4cSRahul Tanwar * Copyright (C) 2020 Intel Corporation. 4e2266f4cSRahul Tanwar * Lei Chuanhua <Chuanhua.lei@intel.com> 5e2266f4cSRahul Tanwar * Zhu Yixin <Yixin.zhu@intel.com> 6e2266f4cSRahul Tanwar */ 7e2266f4cSRahul Tanwar #ifndef __INTEL_LGM_CLK_H 8e2266f4cSRahul Tanwar #define __INTEL_LGM_CLK_H 9e2266f4cSRahul Tanwar 10e2266f4cSRahul Tanwar /* PLL clocks */ 11e2266f4cSRahul Tanwar #define LGM_CLK_OSC 1 12e2266f4cSRahul Tanwar #define LGM_CLK_PLLPP 2 13e2266f4cSRahul Tanwar #define LGM_CLK_PLL2 3 14e2266f4cSRahul Tanwar #define LGM_CLK_PLL0CZ 4 15e2266f4cSRahul Tanwar #define LGM_CLK_PLL0B 5 16e2266f4cSRahul Tanwar #define LGM_CLK_PLL1 6 17e2266f4cSRahul Tanwar #define LGM_CLK_LJPLL3 7 18e2266f4cSRahul Tanwar #define LGM_CLK_LJPLL4 8 19e2266f4cSRahul Tanwar #define LGM_CLK_PLL0CM0 9 20e2266f4cSRahul Tanwar #define LGM_CLK_PLL0CM1 10 21e2266f4cSRahul Tanwar 22e2266f4cSRahul Tanwar /* clocks from PLLs */ 23e2266f4cSRahul Tanwar 24e2266f4cSRahul Tanwar /* ROPLL clocks */ 25e2266f4cSRahul Tanwar #define LGM_CLK_PP_HW 15 26e2266f4cSRahul Tanwar #define LGM_CLK_PP_UC 16 27e2266f4cSRahul Tanwar #define LGM_CLK_PP_FXD 17 28e2266f4cSRahul Tanwar #define LGM_CLK_PP_TBM 18 29e2266f4cSRahul Tanwar 30e2266f4cSRahul Tanwar /* PLL2 clocks */ 31e2266f4cSRahul Tanwar #define LGM_CLK_DDR 20 32e2266f4cSRahul Tanwar 33e2266f4cSRahul Tanwar /* PLL0CZ */ 34e2266f4cSRahul Tanwar #define LGM_CLK_CM 25 35e2266f4cSRahul Tanwar #define LGM_CLK_IC 26 36e2266f4cSRahul Tanwar #define LGM_CLK_SDXC3 27 37e2266f4cSRahul Tanwar 38e2266f4cSRahul Tanwar /* PLL0B */ 39e2266f4cSRahul Tanwar #define LGM_CLK_NGI 30 40e2266f4cSRahul Tanwar #define LGM_CLK_NOC4 31 41e2266f4cSRahul Tanwar #define LGM_CLK_SW 32 42e2266f4cSRahul Tanwar #define LGM_CLK_QSPI 33 43e2266f4cSRahul Tanwar #define LGM_CLK_CQEM LGM_CLK_SW 44e2266f4cSRahul Tanwar #define LGM_CLK_EMMC5 LGM_CLK_NOC4 45e2266f4cSRahul Tanwar 46e2266f4cSRahul Tanwar /* PLL1 */ 47e2266f4cSRahul Tanwar #define LGM_CLK_CT 35 48e2266f4cSRahul Tanwar #define LGM_CLK_DSP 36 49e2266f4cSRahul Tanwar #define LGM_CLK_VIF 37 50e2266f4cSRahul Tanwar 51e2266f4cSRahul Tanwar /* LJPLL3 */ 52e2266f4cSRahul Tanwar #define LGM_CLK_CML 40 53e2266f4cSRahul Tanwar #define LGM_CLK_SERDES 41 54e2266f4cSRahul Tanwar #define LGM_CLK_POOL 42 55e2266f4cSRahul Tanwar #define LGM_CLK_PTP 43 56e2266f4cSRahul Tanwar 57e2266f4cSRahul Tanwar /* LJPLL4 */ 58e2266f4cSRahul Tanwar #define LGM_CLK_PCIE 45 59e2266f4cSRahul Tanwar #define LGM_CLK_SATA LGM_CLK_PCIE 60e2266f4cSRahul Tanwar 61e2266f4cSRahul Tanwar /* PLL0CM0 */ 62e2266f4cSRahul Tanwar #define LGM_CLK_CPU0 50 63e2266f4cSRahul Tanwar 64e2266f4cSRahul Tanwar /* PLL0CM1 */ 65e2266f4cSRahul Tanwar #define LGM_CLK_CPU1 55 66e2266f4cSRahul Tanwar 67e2266f4cSRahul Tanwar /* Miscellaneous clocks */ 68e2266f4cSRahul Tanwar #define LGM_CLK_EMMC4 60 69e2266f4cSRahul Tanwar #define LGM_CLK_SDXC2 61 70e2266f4cSRahul Tanwar #define LGM_CLK_EMMC 62 71e2266f4cSRahul Tanwar #define LGM_CLK_SDXC 63 72e2266f4cSRahul Tanwar #define LGM_CLK_SLIC 64 73e2266f4cSRahul Tanwar #define LGM_CLK_DCL 65 74e2266f4cSRahul Tanwar #define LGM_CLK_DOCSIS 66 75e2266f4cSRahul Tanwar #define LGM_CLK_PCM 67 76e2266f4cSRahul Tanwar #define LGM_CLK_DDR_PHY 68 77e2266f4cSRahul Tanwar #define LGM_CLK_PONDEF 69 78e2266f4cSRahul Tanwar #define LGM_CLK_PL25M 70 79e2266f4cSRahul Tanwar #define LGM_CLK_PL10M 71 80e2266f4cSRahul Tanwar #define LGM_CLK_PL1544K 72 81e2266f4cSRahul Tanwar #define LGM_CLK_PL2048K 73 82e2266f4cSRahul Tanwar #define LGM_CLK_PL8K 74 83e2266f4cSRahul Tanwar #define LGM_CLK_PON_NTR 75 84e2266f4cSRahul Tanwar #define LGM_CLK_SYNC0 76 85e2266f4cSRahul Tanwar #define LGM_CLK_SYNC1 77 86e2266f4cSRahul Tanwar #define LGM_CLK_PROGDIV 78 87e2266f4cSRahul Tanwar #define LGM_CLK_OD0 79 88e2266f4cSRahul Tanwar #define LGM_CLK_OD1 80 89e2266f4cSRahul Tanwar #define LGM_CLK_CBPHY0 81 90e2266f4cSRahul Tanwar #define LGM_CLK_CBPHY1 82 91e2266f4cSRahul Tanwar #define LGM_CLK_CBPHY2 83 92e2266f4cSRahul Tanwar #define LGM_CLK_CBPHY3 84 93e2266f4cSRahul Tanwar 94e2266f4cSRahul Tanwar /* Gate clocks */ 95e2266f4cSRahul Tanwar /* Gate CLK0 */ 96e2266f4cSRahul Tanwar #define LGM_GCLK_C55 100 97e2266f4cSRahul Tanwar #define LGM_GCLK_QSPI 101 98e2266f4cSRahul Tanwar #define LGM_GCLK_EIP197 102 99e2266f4cSRahul Tanwar #define LGM_GCLK_VAULT 103 100e2266f4cSRahul Tanwar #define LGM_GCLK_TOE 104 101e2266f4cSRahul Tanwar #define LGM_GCLK_SDXC 105 102e2266f4cSRahul Tanwar #define LGM_GCLK_EMMC 106 103e2266f4cSRahul Tanwar #define LGM_GCLK_SPI_DBG 107 104e2266f4cSRahul Tanwar #define LGM_GCLK_DMA3 108 105e2266f4cSRahul Tanwar 106e2266f4cSRahul Tanwar /* Gate CLK1 */ 107e2266f4cSRahul Tanwar #define LGM_GCLK_DMA0 120 108e2266f4cSRahul Tanwar #define LGM_GCLK_LEDC0 121 109e2266f4cSRahul Tanwar #define LGM_GCLK_LEDC1 122 110e2266f4cSRahul Tanwar #define LGM_GCLK_I2S0 123 111e2266f4cSRahul Tanwar #define LGM_GCLK_I2S1 124 112e2266f4cSRahul Tanwar #define LGM_GCLK_EBU 125 113e2266f4cSRahul Tanwar #define LGM_GCLK_PWM 126 114e2266f4cSRahul Tanwar #define LGM_GCLK_I2C0 127 115e2266f4cSRahul Tanwar #define LGM_GCLK_I2C1 128 116e2266f4cSRahul Tanwar #define LGM_GCLK_I2C2 129 117e2266f4cSRahul Tanwar #define LGM_GCLK_I2C3 130 118e2266f4cSRahul Tanwar #define LGM_GCLK_SSC0 131 119e2266f4cSRahul Tanwar #define LGM_GCLK_SSC1 132 120e2266f4cSRahul Tanwar #define LGM_GCLK_SSC2 133 121e2266f4cSRahul Tanwar #define LGM_GCLK_SSC3 134 122e2266f4cSRahul Tanwar #define LGM_GCLK_GPTC0 135 123e2266f4cSRahul Tanwar #define LGM_GCLK_GPTC1 136 124e2266f4cSRahul Tanwar #define LGM_GCLK_GPTC2 137 125e2266f4cSRahul Tanwar #define LGM_GCLK_GPTC3 138 126e2266f4cSRahul Tanwar #define LGM_GCLK_ASC0 139 127e2266f4cSRahul Tanwar #define LGM_GCLK_ASC1 140 128e2266f4cSRahul Tanwar #define LGM_GCLK_ASC2 141 129e2266f4cSRahul Tanwar #define LGM_GCLK_ASC3 142 130e2266f4cSRahul Tanwar #define LGM_GCLK_PCM0 143 131e2266f4cSRahul Tanwar #define LGM_GCLK_PCM1 144 132e2266f4cSRahul Tanwar #define LGM_GCLK_PCM2 145 133e2266f4cSRahul Tanwar 134e2266f4cSRahul Tanwar /* Gate CLK2 */ 135e2266f4cSRahul Tanwar #define LGM_GCLK_PCIE10 150 136e2266f4cSRahul Tanwar #define LGM_GCLK_PCIE11 151 137e2266f4cSRahul Tanwar #define LGM_GCLK_PCIE30 152 138e2266f4cSRahul Tanwar #define LGM_GCLK_PCIE31 153 139e2266f4cSRahul Tanwar #define LGM_GCLK_PCIE20 154 140e2266f4cSRahul Tanwar #define LGM_GCLK_PCIE21 155 141e2266f4cSRahul Tanwar #define LGM_GCLK_PCIE40 156 142e2266f4cSRahul Tanwar #define LGM_GCLK_PCIE41 157 143e2266f4cSRahul Tanwar #define LGM_GCLK_XPCS0 158 144e2266f4cSRahul Tanwar #define LGM_GCLK_XPCS1 159 145e2266f4cSRahul Tanwar #define LGM_GCLK_XPCS2 160 146e2266f4cSRahul Tanwar #define LGM_GCLK_XPCS3 161 147e2266f4cSRahul Tanwar #define LGM_GCLK_SATA0 162 148e2266f4cSRahul Tanwar #define LGM_GCLK_SATA1 163 149e2266f4cSRahul Tanwar #define LGM_GCLK_SATA2 164 150e2266f4cSRahul Tanwar #define LGM_GCLK_SATA3 165 151e2266f4cSRahul Tanwar 152e2266f4cSRahul Tanwar /* Gate CLK3 */ 153e2266f4cSRahul Tanwar #define LGM_GCLK_ARCEM4 170 154e2266f4cSRahul Tanwar #define LGM_GCLK_IDMAR1 171 155e2266f4cSRahul Tanwar #define LGM_GCLK_IDMAT0 172 156e2266f4cSRahul Tanwar #define LGM_GCLK_IDMAT1 173 157e2266f4cSRahul Tanwar #define LGM_GCLK_IDMAT2 174 158e2266f4cSRahul Tanwar #define LGM_GCLK_PPV4 175 159e2266f4cSRahul Tanwar #define LGM_GCLK_GSWIPO 176 160e2266f4cSRahul Tanwar #define LGM_GCLK_CQEM 177 161e2266f4cSRahul Tanwar #define LGM_GCLK_XPCS5 178 162e2266f4cSRahul Tanwar #define LGM_GCLK_USB1 179 163e2266f4cSRahul Tanwar #define LGM_GCLK_USB2 180 164e2266f4cSRahul Tanwar 165e2266f4cSRahul Tanwar #endif /* __INTEL_LGM_CLK_H */ 166