135bcaf00SAlexander Shiyan /* 235bcaf00SAlexander Shiyan * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 335bcaf00SAlexander Shiyan * 435bcaf00SAlexander Shiyan * This program is free software; you can redistribute it and/or modify 535bcaf00SAlexander Shiyan * it under the terms of the GNU General Public License version 2 as 635bcaf00SAlexander Shiyan * published by the Free Software Foundation. 735bcaf00SAlexander Shiyan * 835bcaf00SAlexander Shiyan */ 935bcaf00SAlexander Shiyan 1035bcaf00SAlexander Shiyan #ifndef __DT_BINDINGS_CLOCK_IMX21_H 1135bcaf00SAlexander Shiyan #define __DT_BINDINGS_CLOCK_IMX21_H 1235bcaf00SAlexander Shiyan 1335bcaf00SAlexander Shiyan #define IMX21_CLK_DUMMY 0 1435bcaf00SAlexander Shiyan #define IMX21_CLK_CKIL 1 1535bcaf00SAlexander Shiyan #define IMX21_CLK_CKIH 2 1635bcaf00SAlexander Shiyan #define IMX21_CLK_FPM 3 1735bcaf00SAlexander Shiyan #define IMX21_CLK_CKIH_DIV1P5 4 1835bcaf00SAlexander Shiyan #define IMX21_CLK_MPLL_GATE 5 1935bcaf00SAlexander Shiyan #define IMX21_CLK_SPLL_GATE 6 2035bcaf00SAlexander Shiyan #define IMX21_CLK_FPM_GATE 7 2135bcaf00SAlexander Shiyan #define IMX21_CLK_CKIH_GATE 8 2235bcaf00SAlexander Shiyan #define IMX21_CLK_MPLL_OSC_SEL 9 2335bcaf00SAlexander Shiyan #define IMX21_CLK_IPG 10 2435bcaf00SAlexander Shiyan #define IMX21_CLK_HCLK 11 2535bcaf00SAlexander Shiyan #define IMX21_CLK_MPLL_SEL 12 2635bcaf00SAlexander Shiyan #define IMX21_CLK_SPLL_SEL 13 2735bcaf00SAlexander Shiyan #define IMX21_CLK_SSI1_SEL 14 2835bcaf00SAlexander Shiyan #define IMX21_CLK_SSI2_SEL 15 2935bcaf00SAlexander Shiyan #define IMX21_CLK_USB_DIV 16 3035bcaf00SAlexander Shiyan #define IMX21_CLK_FCLK 17 3135bcaf00SAlexander Shiyan #define IMX21_CLK_MPLL 18 3235bcaf00SAlexander Shiyan #define IMX21_CLK_SPLL 19 3335bcaf00SAlexander Shiyan #define IMX21_CLK_NFC_DIV 20 3435bcaf00SAlexander Shiyan #define IMX21_CLK_SSI1_DIV 21 3535bcaf00SAlexander Shiyan #define IMX21_CLK_SSI2_DIV 22 3635bcaf00SAlexander Shiyan #define IMX21_CLK_PER1 23 3735bcaf00SAlexander Shiyan #define IMX21_CLK_PER2 24 3835bcaf00SAlexander Shiyan #define IMX21_CLK_PER3 25 3935bcaf00SAlexander Shiyan #define IMX21_CLK_PER4 26 4035bcaf00SAlexander Shiyan #define IMX21_CLK_UART1_IPG_GATE 27 4135bcaf00SAlexander Shiyan #define IMX21_CLK_UART2_IPG_GATE 28 4235bcaf00SAlexander Shiyan #define IMX21_CLK_UART3_IPG_GATE 29 4335bcaf00SAlexander Shiyan #define IMX21_CLK_UART4_IPG_GATE 30 4435bcaf00SAlexander Shiyan #define IMX21_CLK_CSPI1_IPG_GATE 31 4535bcaf00SAlexander Shiyan #define IMX21_CLK_CSPI2_IPG_GATE 32 4635bcaf00SAlexander Shiyan #define IMX21_CLK_SSI1_GATE 33 4735bcaf00SAlexander Shiyan #define IMX21_CLK_SSI2_GATE 34 4835bcaf00SAlexander Shiyan #define IMX21_CLK_SDHC1_IPG_GATE 35 4935bcaf00SAlexander Shiyan #define IMX21_CLK_SDHC2_IPG_GATE 36 5035bcaf00SAlexander Shiyan #define IMX21_CLK_GPIO_GATE 37 5135bcaf00SAlexander Shiyan #define IMX21_CLK_I2C_GATE 38 5235bcaf00SAlexander Shiyan #define IMX21_CLK_DMA_GATE 39 5335bcaf00SAlexander Shiyan #define IMX21_CLK_USB_GATE 40 5435bcaf00SAlexander Shiyan #define IMX21_CLK_EMMA_GATE 41 5535bcaf00SAlexander Shiyan #define IMX21_CLK_SSI2_BAUD_GATE 42 5635bcaf00SAlexander Shiyan #define IMX21_CLK_SSI1_BAUD_GATE 43 5735bcaf00SAlexander Shiyan #define IMX21_CLK_LCDC_IPG_GATE 44 5835bcaf00SAlexander Shiyan #define IMX21_CLK_NFC_GATE 45 5935bcaf00SAlexander Shiyan #define IMX21_CLK_LCDC_HCLK_GATE 46 6035bcaf00SAlexander Shiyan #define IMX21_CLK_PER4_GATE 47 6135bcaf00SAlexander Shiyan #define IMX21_CLK_BMI_GATE 48 6235bcaf00SAlexander Shiyan #define IMX21_CLK_USB_HCLK_GATE 49 6335bcaf00SAlexander Shiyan #define IMX21_CLK_SLCDC_GATE 50 6435bcaf00SAlexander Shiyan #define IMX21_CLK_SLCDC_HCLK_GATE 51 6535bcaf00SAlexander Shiyan #define IMX21_CLK_EMMA_HCLK_GATE 52 6635bcaf00SAlexander Shiyan #define IMX21_CLK_BROM_GATE 53 6735bcaf00SAlexander Shiyan #define IMX21_CLK_DMA_HCLK_GATE 54 6835bcaf00SAlexander Shiyan #define IMX21_CLK_CSI_HCLK_GATE 55 6935bcaf00SAlexander Shiyan #define IMX21_CLK_CSPI3_IPG_GATE 56 7035bcaf00SAlexander Shiyan #define IMX21_CLK_WDOG_GATE 57 7135bcaf00SAlexander Shiyan #define IMX21_CLK_GPT1_IPG_GATE 58 7235bcaf00SAlexander Shiyan #define IMX21_CLK_GPT2_IPG_GATE 59 7335bcaf00SAlexander Shiyan #define IMX21_CLK_GPT3_IPG_GATE 60 7435bcaf00SAlexander Shiyan #define IMX21_CLK_PWM_IPG_GATE 61 7535bcaf00SAlexander Shiyan #define IMX21_CLK_RTC_GATE 62 7635bcaf00SAlexander Shiyan #define IMX21_CLK_KPP_GATE 63 7735bcaf00SAlexander Shiyan #define IMX21_CLK_OWIRE_GATE 64 7835bcaf00SAlexander Shiyan #define IMX21_CLK_MAX 65 7935bcaf00SAlexander Shiyan 8035bcaf00SAlexander Shiyan #endif 81