10aa0c95fSHaojian Zhuang /* 20aa0c95fSHaojian Zhuang * Copyright (c) 2012-2013 Hisilicon Limited. 30aa0c95fSHaojian Zhuang * Copyright (c) 2012-2013 Linaro Limited. 40aa0c95fSHaojian Zhuang * 50aa0c95fSHaojian Zhuang * Author: Haojian Zhuang <haojian.zhuang@linaro.org> 60aa0c95fSHaojian Zhuang * Xin Li <li.xin@linaro.org> 70aa0c95fSHaojian Zhuang * 80aa0c95fSHaojian Zhuang * This program is free software; you can redistribute it and/or modify 90aa0c95fSHaojian Zhuang * it under the terms of the GNU General Public License as published by 100aa0c95fSHaojian Zhuang * the Free Software Foundation; either version 2 of the License, or 110aa0c95fSHaojian Zhuang * (at your option) any later version. 120aa0c95fSHaojian Zhuang * 130aa0c95fSHaojian Zhuang * This program is distributed in the hope that it will be useful, 140aa0c95fSHaojian Zhuang * but WITHOUT ANY WARRANTY; without even the implied warranty of 150aa0c95fSHaojian Zhuang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 160aa0c95fSHaojian Zhuang * GNU General Public License for more details. 170aa0c95fSHaojian Zhuang * 180aa0c95fSHaojian Zhuang * You should have received a copy of the GNU General Public License along 190aa0c95fSHaojian Zhuang * with this program; if not, write to the Free Software Foundation, Inc., 200aa0c95fSHaojian Zhuang * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 210aa0c95fSHaojian Zhuang * 220aa0c95fSHaojian Zhuang */ 230aa0c95fSHaojian Zhuang 240aa0c95fSHaojian Zhuang #ifndef __DTS_HI3620_CLOCK_H 250aa0c95fSHaojian Zhuang #define __DTS_HI3620_CLOCK_H 260aa0c95fSHaojian Zhuang 270aa0c95fSHaojian Zhuang #define HI3620_NONE_CLOCK 0 280aa0c95fSHaojian Zhuang 290aa0c95fSHaojian Zhuang /* fixed rate & fixed factor clocks */ 300aa0c95fSHaojian Zhuang #define HI3620_OSC32K 1 310aa0c95fSHaojian Zhuang #define HI3620_OSC26M 2 320aa0c95fSHaojian Zhuang #define HI3620_PCLK 3 330aa0c95fSHaojian Zhuang #define HI3620_PLL_ARM0 4 340aa0c95fSHaojian Zhuang #define HI3620_PLL_ARM1 5 350aa0c95fSHaojian Zhuang #define HI3620_PLL_PERI 6 360aa0c95fSHaojian Zhuang #define HI3620_PLL_USB 7 370aa0c95fSHaojian Zhuang #define HI3620_PLL_HDMI 8 380aa0c95fSHaojian Zhuang #define HI3620_PLL_GPU 9 390aa0c95fSHaojian Zhuang #define HI3620_RCLK_TCXO 10 400aa0c95fSHaojian Zhuang #define HI3620_RCLK_CFGAXI 11 410aa0c95fSHaojian Zhuang #define HI3620_RCLK_PICO 12 420aa0c95fSHaojian Zhuang 430aa0c95fSHaojian Zhuang /* mux clocks */ 440aa0c95fSHaojian Zhuang #define HI3620_TIMER0_MUX 32 450aa0c95fSHaojian Zhuang #define HI3620_TIMER1_MUX 33 460aa0c95fSHaojian Zhuang #define HI3620_TIMER2_MUX 34 470aa0c95fSHaojian Zhuang #define HI3620_TIMER3_MUX 35 480aa0c95fSHaojian Zhuang #define HI3620_TIMER4_MUX 36 490aa0c95fSHaojian Zhuang #define HI3620_TIMER5_MUX 37 500aa0c95fSHaojian Zhuang #define HI3620_TIMER6_MUX 38 510aa0c95fSHaojian Zhuang #define HI3620_TIMER7_MUX 39 520aa0c95fSHaojian Zhuang #define HI3620_TIMER8_MUX 40 530aa0c95fSHaojian Zhuang #define HI3620_TIMER9_MUX 41 540aa0c95fSHaojian Zhuang #define HI3620_UART0_MUX 42 550aa0c95fSHaojian Zhuang #define HI3620_UART1_MUX 43 560aa0c95fSHaojian Zhuang #define HI3620_UART2_MUX 44 570aa0c95fSHaojian Zhuang #define HI3620_UART3_MUX 45 580aa0c95fSHaojian Zhuang #define HI3620_UART4_MUX 46 590aa0c95fSHaojian Zhuang #define HI3620_SPI0_MUX 47 600aa0c95fSHaojian Zhuang #define HI3620_SPI1_MUX 48 610aa0c95fSHaojian Zhuang #define HI3620_SPI2_MUX 49 620aa0c95fSHaojian Zhuang #define HI3620_SAXI_MUX 50 630aa0c95fSHaojian Zhuang #define HI3620_PWM0_MUX 51 640aa0c95fSHaojian Zhuang #define HI3620_PWM1_MUX 52 650aa0c95fSHaojian Zhuang #define HI3620_SD_MUX 53 660aa0c95fSHaojian Zhuang #define HI3620_MMC1_MUX 54 670aa0c95fSHaojian Zhuang #define HI3620_MMC1_MUX2 55 680aa0c95fSHaojian Zhuang #define HI3620_G2D_MUX 56 690aa0c95fSHaojian Zhuang #define HI3620_VENC_MUX 57 700aa0c95fSHaojian Zhuang #define HI3620_VDEC_MUX 58 710aa0c95fSHaojian Zhuang #define HI3620_VPP_MUX 59 720aa0c95fSHaojian Zhuang #define HI3620_EDC0_MUX 60 730aa0c95fSHaojian Zhuang #define HI3620_LDI0_MUX 61 740aa0c95fSHaojian Zhuang #define HI3620_EDC1_MUX 62 750aa0c95fSHaojian Zhuang #define HI3620_LDI1_MUX 63 760aa0c95fSHaojian Zhuang #define HI3620_RCLK_HSIC 64 770aa0c95fSHaojian Zhuang #define HI3620_MMC2_MUX 65 780aa0c95fSHaojian Zhuang #define HI3620_MMC3_MUX 66 790aa0c95fSHaojian Zhuang 800aa0c95fSHaojian Zhuang /* divider clocks */ 810aa0c95fSHaojian Zhuang #define HI3620_SHAREAXI_DIV 128 820aa0c95fSHaojian Zhuang #define HI3620_CFGAXI_DIV 129 830aa0c95fSHaojian Zhuang #define HI3620_SD_DIV 130 840aa0c95fSHaojian Zhuang #define HI3620_MMC1_DIV 131 850aa0c95fSHaojian Zhuang #define HI3620_HSIC_DIV 132 860aa0c95fSHaojian Zhuang #define HI3620_MMC2_DIV 133 870aa0c95fSHaojian Zhuang #define HI3620_MMC3_DIV 134 880aa0c95fSHaojian Zhuang 890aa0c95fSHaojian Zhuang /* gate clocks */ 900aa0c95fSHaojian Zhuang #define HI3620_TIMERCLK01 160 910aa0c95fSHaojian Zhuang #define HI3620_TIMER_RCLK01 161 920aa0c95fSHaojian Zhuang #define HI3620_TIMERCLK23 162 930aa0c95fSHaojian Zhuang #define HI3620_TIMER_RCLK23 163 940aa0c95fSHaojian Zhuang #define HI3620_TIMERCLK45 164 950aa0c95fSHaojian Zhuang #define HI3620_TIMERCLK67 165 960aa0c95fSHaojian Zhuang #define HI3620_TIMERCLK89 166 970aa0c95fSHaojian Zhuang #define HI3620_RTCCLK 167 980aa0c95fSHaojian Zhuang #define HI3620_KPC_CLK 168 990aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK0 169 1000aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK1 170 1010aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK2 171 1020aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK3 172 1030aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK4 173 1040aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK5 174 1050aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK6 175 1060aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK7 176 1070aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK8 177 1080aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK9 178 1090aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK10 179 1100aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK11 180 1110aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK12 181 1120aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK13 182 1130aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK14 183 1140aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK15 184 1150aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK16 185 1160aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK17 186 1170aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK18 187 1180aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK19 188 1190aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK20 189 1200aa0c95fSHaojian Zhuang #define HI3620_GPIOCLK21 190 1210aa0c95fSHaojian Zhuang #define HI3620_DPHY0_CLK 191 1220aa0c95fSHaojian Zhuang #define HI3620_DPHY1_CLK 192 1230aa0c95fSHaojian Zhuang #define HI3620_DPHY2_CLK 193 1240aa0c95fSHaojian Zhuang #define HI3620_USBPHY_CLK 194 1250aa0c95fSHaojian Zhuang #define HI3620_ACP_CLK 195 1260aa0c95fSHaojian Zhuang #define HI3620_PWMCLK0 196 1270aa0c95fSHaojian Zhuang #define HI3620_PWMCLK1 197 1280aa0c95fSHaojian Zhuang #define HI3620_UARTCLK0 198 1290aa0c95fSHaojian Zhuang #define HI3620_UARTCLK1 199 1300aa0c95fSHaojian Zhuang #define HI3620_UARTCLK2 200 1310aa0c95fSHaojian Zhuang #define HI3620_UARTCLK3 201 1320aa0c95fSHaojian Zhuang #define HI3620_UARTCLK4 202 1330aa0c95fSHaojian Zhuang #define HI3620_SPICLK0 203 1340aa0c95fSHaojian Zhuang #define HI3620_SPICLK1 204 1350aa0c95fSHaojian Zhuang #define HI3620_SPICLK2 205 1360aa0c95fSHaojian Zhuang #define HI3620_I2CCLK0 206 1370aa0c95fSHaojian Zhuang #define HI3620_I2CCLK1 207 1380aa0c95fSHaojian Zhuang #define HI3620_I2CCLK2 208 1390aa0c95fSHaojian Zhuang #define HI3620_I2CCLK3 209 1400aa0c95fSHaojian Zhuang #define HI3620_SCI_CLK 210 1410aa0c95fSHaojian Zhuang #define HI3620_DDRC_PER_CLK 211 1420aa0c95fSHaojian Zhuang #define HI3620_DMAC_CLK 212 1430aa0c95fSHaojian Zhuang #define HI3620_USB2DVC_CLK 213 1440aa0c95fSHaojian Zhuang #define HI3620_SD_CLK 214 1450aa0c95fSHaojian Zhuang #define HI3620_MMC_CLK1 215 1460aa0c95fSHaojian Zhuang #define HI3620_MMC_CLK2 216 1470aa0c95fSHaojian Zhuang #define HI3620_MMC_CLK3 217 1480aa0c95fSHaojian Zhuang #define HI3620_MCU_CLK 218 1490aa0c95fSHaojian Zhuang 15062ac983bSZhangfei Gao #define HI3620_SD_CIUCLK 0 15162ac983bSZhangfei Gao #define HI3620_MMC_CIUCLK1 1 15262ac983bSZhangfei Gao #define HI3620_MMC_CIUCLK2 2 15362ac983bSZhangfei Gao #define HI3620_MMC_CIUCLK3 3 15462ac983bSZhangfei Gao 1550aa0c95fSHaojian Zhuang #define HI3620_NR_CLKS 219 1560aa0c95fSHaojian Zhuang 1570aa0c95fSHaojian Zhuang #endif /* __DTS_HI3620_CLOCK_H */ 158