1 /*
2  * GXBB clock tree IDs
3  */
4 
5 #ifndef __GXBB_CLKC_H
6 #define __GXBB_CLKC_H
7 
8 #define CLKID_CPUCLK		1
9 #define CLKID_HDMI_PLL		2
10 #define CLKID_FCLK_DIV2		4
11 #define CLKID_FCLK_DIV3		5
12 #define CLKID_FCLK_DIV4		6
13 #define CLKID_CLK81		12
14 #define CLKID_MPLL2		15
15 #define CLKID_SPI		34
16 #define CLKID_I2C		22
17 #define CLKID_ETH		36
18 #define CLKID_USB0		50
19 #define CLKID_USB1		51
20 #define CLKID_USB		55
21 #define CLKID_USB1_DDR_BRIDGE	64
22 #define CLKID_USB0_DDR_BRIDGE	65
23 #define CLKID_AO_I2C		93
24 #define CLKID_SD_EMMC_A		94
25 #define CLKID_SD_EMMC_B		95
26 #define CLKID_SD_EMMC_C		96
27 
28 #endif /* __GXBB_CLKC_H */
29