12ae5c2c3SSam Protsenko /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 22ae5c2c3SSam Protsenko /* 32ae5c2c3SSam Protsenko * Copyright (C) 2021 Linaro Ltd. 42ae5c2c3SSam Protsenko * Author: Sam Protsenko <semen.protsenko@linaro.org> 52ae5c2c3SSam Protsenko * 62ae5c2c3SSam Protsenko * Device Tree binding constants for Exynos850 clock controller. 72ae5c2c3SSam Protsenko */ 82ae5c2c3SSam Protsenko 92ae5c2c3SSam Protsenko #ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H 102ae5c2c3SSam Protsenko #define _DT_BINDINGS_CLOCK_EXYNOS_850_H 112ae5c2c3SSam Protsenko 122ae5c2c3SSam Protsenko /* CMU_TOP */ 132ae5c2c3SSam Protsenko #define CLK_FOUT_SHARED0_PLL 1 142ae5c2c3SSam Protsenko #define CLK_FOUT_SHARED1_PLL 2 152ae5c2c3SSam Protsenko #define CLK_FOUT_MMC_PLL 3 162ae5c2c3SSam Protsenko #define CLK_MOUT_SHARED0_PLL 4 172ae5c2c3SSam Protsenko #define CLK_MOUT_SHARED1_PLL 5 182ae5c2c3SSam Protsenko #define CLK_MOUT_MMC_PLL 6 192ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_BUS 7 202ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_CCI 8 212ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_MMC_EMBD 9 222ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_SSS 10 232ae5c2c3SSam Protsenko #define CLK_MOUT_DPU 11 242ae5c2c3SSam Protsenko #define CLK_MOUT_HSI_BUS 12 252ae5c2c3SSam Protsenko #define CLK_MOUT_HSI_MMC_CARD 13 262ae5c2c3SSam Protsenko #define CLK_MOUT_HSI_USB20DRD 14 272ae5c2c3SSam Protsenko #define CLK_MOUT_PERI_BUS 15 282ae5c2c3SSam Protsenko #define CLK_MOUT_PERI_UART 16 292ae5c2c3SSam Protsenko #define CLK_MOUT_PERI_IP 17 302ae5c2c3SSam Protsenko #define CLK_DOUT_SHARED0_DIV3 18 312ae5c2c3SSam Protsenko #define CLK_DOUT_SHARED0_DIV2 19 322ae5c2c3SSam Protsenko #define CLK_DOUT_SHARED1_DIV3 20 332ae5c2c3SSam Protsenko #define CLK_DOUT_SHARED1_DIV2 21 342ae5c2c3SSam Protsenko #define CLK_DOUT_SHARED0_DIV4 22 352ae5c2c3SSam Protsenko #define CLK_DOUT_SHARED1_DIV4 23 362ae5c2c3SSam Protsenko #define CLK_DOUT_CORE_BUS 24 372ae5c2c3SSam Protsenko #define CLK_DOUT_CORE_CCI 25 382ae5c2c3SSam Protsenko #define CLK_DOUT_CORE_MMC_EMBD 26 392ae5c2c3SSam Protsenko #define CLK_DOUT_CORE_SSS 27 402ae5c2c3SSam Protsenko #define CLK_DOUT_DPU 28 412ae5c2c3SSam Protsenko #define CLK_DOUT_HSI_BUS 29 422ae5c2c3SSam Protsenko #define CLK_DOUT_HSI_MMC_CARD 30 432ae5c2c3SSam Protsenko #define CLK_DOUT_HSI_USB20DRD 31 442ae5c2c3SSam Protsenko #define CLK_DOUT_PERI_BUS 32 452ae5c2c3SSam Protsenko #define CLK_DOUT_PERI_UART 33 462ae5c2c3SSam Protsenko #define CLK_DOUT_PERI_IP 34 472ae5c2c3SSam Protsenko #define CLK_GOUT_CORE_BUS 35 482ae5c2c3SSam Protsenko #define CLK_GOUT_CORE_CCI 36 492ae5c2c3SSam Protsenko #define CLK_GOUT_CORE_MMC_EMBD 37 502ae5c2c3SSam Protsenko #define CLK_GOUT_CORE_SSS 38 512ae5c2c3SSam Protsenko #define CLK_GOUT_DPU 39 522ae5c2c3SSam Protsenko #define CLK_GOUT_HSI_BUS 40 532ae5c2c3SSam Protsenko #define CLK_GOUT_HSI_MMC_CARD 41 542ae5c2c3SSam Protsenko #define CLK_GOUT_HSI_USB20DRD 42 552ae5c2c3SSam Protsenko #define CLK_GOUT_PERI_BUS 43 562ae5c2c3SSam Protsenko #define CLK_GOUT_PERI_UART 44 572ae5c2c3SSam Protsenko #define CLK_GOUT_PERI_IP 45 5816e0c247SSam Protsenko #define CLK_MOUT_CLKCMU_APM_BUS 46 5916e0c247SSam Protsenko #define CLK_DOUT_CLKCMU_APM_BUS 47 6016e0c247SSam Protsenko #define CLK_GOUT_CLKCMU_APM_BUS 48 6116e0c247SSam Protsenko #define TOP_NR_CLK 49 6216e0c247SSam Protsenko 6316e0c247SSam Protsenko /* CMU_APM */ 6416e0c247SSam Protsenko #define CLK_RCO_I3C_PMIC 1 6516e0c247SSam Protsenko #define OSCCLK_RCO_APM 2 6616e0c247SSam Protsenko #define CLK_RCO_APM__ALV 3 6716e0c247SSam Protsenko #define CLK_DLL_DCO 4 6816e0c247SSam Protsenko #define CLK_MOUT_APM_BUS_USER 5 6916e0c247SSam Protsenko #define CLK_MOUT_RCO_APM_I3C_USER 6 7016e0c247SSam Protsenko #define CLK_MOUT_RCO_APM_USER 7 7116e0c247SSam Protsenko #define CLK_MOUT_DLL_USER 8 7216e0c247SSam Protsenko #define CLK_MOUT_CLKCMU_CHUB_BUS 9 7316e0c247SSam Protsenko #define CLK_MOUT_APM_BUS 10 7416e0c247SSam Protsenko #define CLK_MOUT_APM_I3C 11 7516e0c247SSam Protsenko #define CLK_DOUT_CLKCMU_CHUB_BUS 12 7616e0c247SSam Protsenko #define CLK_DOUT_APM_BUS 13 7716e0c247SSam Protsenko #define CLK_DOUT_APM_I3C 14 7816e0c247SSam Protsenko #define CLK_GOUT_CLKCMU_CMGP_BUS 15 7916e0c247SSam Protsenko #define CLK_GOUT_CLKCMU_CHUB_BUS 16 8016e0c247SSam Protsenko #define CLK_GOUT_RTC_PCLK 17 8116e0c247SSam Protsenko #define CLK_GOUT_TOP_RTC_PCLK 18 8216e0c247SSam Protsenko #define CLK_GOUT_I3C_PCLK 19 8316e0c247SSam Protsenko #define CLK_GOUT_I3C_SCLK 20 8416e0c247SSam Protsenko #define CLK_GOUT_SPEEDY_PCLK 21 8516e0c247SSam Protsenko #define APM_NR_CLK 22 862ae5c2c3SSam Protsenko 87*c2afeb79SSam Protsenko /* CMU_CMGP */ 88*c2afeb79SSam Protsenko #define CLK_RCO_CMGP 1 89*c2afeb79SSam Protsenko #define CLK_MOUT_CMGP_ADC 2 90*c2afeb79SSam Protsenko #define CLK_MOUT_CMGP_USI0 3 91*c2afeb79SSam Protsenko #define CLK_MOUT_CMGP_USI1 4 92*c2afeb79SSam Protsenko #define CLK_DOUT_CMGP_ADC 5 93*c2afeb79SSam Protsenko #define CLK_DOUT_CMGP_USI0 6 94*c2afeb79SSam Protsenko #define CLK_DOUT_CMGP_USI1 7 95*c2afeb79SSam Protsenko #define CLK_GOUT_CMGP_ADC_S0_PCLK 8 96*c2afeb79SSam Protsenko #define CLK_GOUT_CMGP_ADC_S1_PCLK 9 97*c2afeb79SSam Protsenko #define CLK_GOUT_CMGP_GPIO_PCLK 10 98*c2afeb79SSam Protsenko #define CLK_GOUT_CMGP_USI0_IPCLK 11 99*c2afeb79SSam Protsenko #define CLK_GOUT_CMGP_USI0_PCLK 12 100*c2afeb79SSam Protsenko #define CLK_GOUT_CMGP_USI1_IPCLK 13 101*c2afeb79SSam Protsenko #define CLK_GOUT_CMGP_USI1_PCLK 14 102*c2afeb79SSam Protsenko #define CMGP_NR_CLK 15 103*c2afeb79SSam Protsenko 1042ae5c2c3SSam Protsenko /* CMU_HSI */ 1052ae5c2c3SSam Protsenko #define CLK_MOUT_HSI_BUS_USER 1 1062ae5c2c3SSam Protsenko #define CLK_MOUT_HSI_MMC_CARD_USER 2 1072ae5c2c3SSam Protsenko #define CLK_MOUT_HSI_USB20DRD_USER 3 1082ae5c2c3SSam Protsenko #define CLK_MOUT_HSI_RTC 4 1092ae5c2c3SSam Protsenko #define CLK_GOUT_USB_RTC_CLK 5 1102ae5c2c3SSam Protsenko #define CLK_GOUT_USB_REF_CLK 6 1112ae5c2c3SSam Protsenko #define CLK_GOUT_USB_PHY_REF_CLK 7 1122ae5c2c3SSam Protsenko #define CLK_GOUT_USB_PHY_ACLK 8 1132ae5c2c3SSam Protsenko #define CLK_GOUT_USB_BUS_EARLY_CLK 9 1142ae5c2c3SSam Protsenko #define CLK_GOUT_GPIO_HSI_PCLK 10 1152ae5c2c3SSam Protsenko #define CLK_GOUT_MMC_CARD_ACLK 11 1162ae5c2c3SSam Protsenko #define CLK_GOUT_MMC_CARD_SDCLKIN 12 1172ae5c2c3SSam Protsenko #define CLK_GOUT_SYSREG_HSI_PCLK 13 1182ae5c2c3SSam Protsenko #define HSI_NR_CLK 14 1192ae5c2c3SSam Protsenko 1202ae5c2c3SSam Protsenko /* CMU_PERI */ 1212ae5c2c3SSam Protsenko #define CLK_MOUT_PERI_BUS_USER 1 1222ae5c2c3SSam Protsenko #define CLK_MOUT_PERI_UART_USER 2 1232ae5c2c3SSam Protsenko #define CLK_MOUT_PERI_HSI2C_USER 3 1242ae5c2c3SSam Protsenko #define CLK_MOUT_PERI_SPI_USER 4 1252ae5c2c3SSam Protsenko #define CLK_DOUT_PERI_HSI2C0 5 1262ae5c2c3SSam Protsenko #define CLK_DOUT_PERI_HSI2C1 6 1272ae5c2c3SSam Protsenko #define CLK_DOUT_PERI_HSI2C2 7 1282ae5c2c3SSam Protsenko #define CLK_DOUT_PERI_SPI0 8 1292ae5c2c3SSam Protsenko #define CLK_GOUT_PERI_HSI2C0 9 1302ae5c2c3SSam Protsenko #define CLK_GOUT_PERI_HSI2C1 10 1312ae5c2c3SSam Protsenko #define CLK_GOUT_PERI_HSI2C2 11 1322ae5c2c3SSam Protsenko #define CLK_GOUT_GPIO_PERI_PCLK 12 1332ae5c2c3SSam Protsenko #define CLK_GOUT_HSI2C0_IPCLK 13 1342ae5c2c3SSam Protsenko #define CLK_GOUT_HSI2C0_PCLK 14 1352ae5c2c3SSam Protsenko #define CLK_GOUT_HSI2C1_IPCLK 15 1362ae5c2c3SSam Protsenko #define CLK_GOUT_HSI2C1_PCLK 16 1372ae5c2c3SSam Protsenko #define CLK_GOUT_HSI2C2_IPCLK 17 1382ae5c2c3SSam Protsenko #define CLK_GOUT_HSI2C2_PCLK 18 1392ae5c2c3SSam Protsenko #define CLK_GOUT_I2C0_PCLK 19 1402ae5c2c3SSam Protsenko #define CLK_GOUT_I2C1_PCLK 20 1412ae5c2c3SSam Protsenko #define CLK_GOUT_I2C2_PCLK 21 1422ae5c2c3SSam Protsenko #define CLK_GOUT_I2C3_PCLK 22 1432ae5c2c3SSam Protsenko #define CLK_GOUT_I2C4_PCLK 23 1442ae5c2c3SSam Protsenko #define CLK_GOUT_I2C5_PCLK 24 1452ae5c2c3SSam Protsenko #define CLK_GOUT_I2C6_PCLK 25 1462ae5c2c3SSam Protsenko #define CLK_GOUT_MCT_PCLK 26 1472ae5c2c3SSam Protsenko #define CLK_GOUT_PWM_MOTOR_PCLK 27 1482ae5c2c3SSam Protsenko #define CLK_GOUT_SPI0_IPCLK 28 1492ae5c2c3SSam Protsenko #define CLK_GOUT_SPI0_PCLK 29 1502ae5c2c3SSam Protsenko #define CLK_GOUT_SYSREG_PERI_PCLK 30 1512ae5c2c3SSam Protsenko #define CLK_GOUT_UART_IPCLK 31 1522ae5c2c3SSam Protsenko #define CLK_GOUT_UART_PCLK 32 1532ae5c2c3SSam Protsenko #define CLK_GOUT_WDT0_PCLK 33 1542ae5c2c3SSam Protsenko #define CLK_GOUT_WDT1_PCLK 34 1552ae5c2c3SSam Protsenko #define PERI_NR_CLK 35 1562ae5c2c3SSam Protsenko 1572ae5c2c3SSam Protsenko /* CMU_CORE */ 1582ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_BUS_USER 1 1592ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_CCI_USER 2 1602ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_MMC_EMBD_USER 3 1612ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_SSS_USER 4 1622ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_GIC 5 1632ae5c2c3SSam Protsenko #define CLK_DOUT_CORE_BUSP 6 1642ae5c2c3SSam Protsenko #define CLK_GOUT_CCI_ACLK 7 1652ae5c2c3SSam Protsenko #define CLK_GOUT_GIC_CLK 8 1662ae5c2c3SSam Protsenko #define CLK_GOUT_MMC_EMBD_ACLK 9 1672ae5c2c3SSam Protsenko #define CLK_GOUT_MMC_EMBD_SDCLKIN 10 1682ae5c2c3SSam Protsenko #define CLK_GOUT_SSS_ACLK 11 1692ae5c2c3SSam Protsenko #define CLK_GOUT_SSS_PCLK 12 1702ae5c2c3SSam Protsenko #define CORE_NR_CLK 13 1712ae5c2c3SSam Protsenko 1722ae5c2c3SSam Protsenko /* CMU_DPU */ 1732ae5c2c3SSam Protsenko #define CLK_MOUT_DPU_USER 1 1742ae5c2c3SSam Protsenko #define CLK_DOUT_DPU_BUSP 2 1752ae5c2c3SSam Protsenko #define CLK_GOUT_DPU_CMU_DPU_PCLK 3 1762ae5c2c3SSam Protsenko #define CLK_GOUT_DPU_DECON0_ACLK 4 1772ae5c2c3SSam Protsenko #define CLK_GOUT_DPU_DMA_ACLK 5 1782ae5c2c3SSam Protsenko #define CLK_GOUT_DPU_DPP_ACLK 6 1792ae5c2c3SSam Protsenko #define CLK_GOUT_DPU_PPMU_ACLK 7 1802ae5c2c3SSam Protsenko #define CLK_GOUT_DPU_PPMU_PCLK 8 1812ae5c2c3SSam Protsenko #define CLK_GOUT_DPU_SMMU_CLK 9 1822ae5c2c3SSam Protsenko #define CLK_GOUT_DPU_SYSREG_PCLK 10 1832ae5c2c3SSam Protsenko #define DPU_NR_CLK 11 1842ae5c2c3SSam Protsenko 1852ae5c2c3SSam Protsenko #endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */ 186