1*2ae5c2c3SSam Protsenko /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*2ae5c2c3SSam Protsenko /* 3*2ae5c2c3SSam Protsenko * Copyright (C) 2021 Linaro Ltd. 4*2ae5c2c3SSam Protsenko * Author: Sam Protsenko <semen.protsenko@linaro.org> 5*2ae5c2c3SSam Protsenko * 6*2ae5c2c3SSam Protsenko * Device Tree binding constants for Exynos850 clock controller. 7*2ae5c2c3SSam Protsenko */ 8*2ae5c2c3SSam Protsenko 9*2ae5c2c3SSam Protsenko #ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H 10*2ae5c2c3SSam Protsenko #define _DT_BINDINGS_CLOCK_EXYNOS_850_H 11*2ae5c2c3SSam Protsenko 12*2ae5c2c3SSam Protsenko /* CMU_TOP */ 13*2ae5c2c3SSam Protsenko #define CLK_FOUT_SHARED0_PLL 1 14*2ae5c2c3SSam Protsenko #define CLK_FOUT_SHARED1_PLL 2 15*2ae5c2c3SSam Protsenko #define CLK_FOUT_MMC_PLL 3 16*2ae5c2c3SSam Protsenko #define CLK_MOUT_SHARED0_PLL 4 17*2ae5c2c3SSam Protsenko #define CLK_MOUT_SHARED1_PLL 5 18*2ae5c2c3SSam Protsenko #define CLK_MOUT_MMC_PLL 6 19*2ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_BUS 7 20*2ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_CCI 8 21*2ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_MMC_EMBD 9 22*2ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_SSS 10 23*2ae5c2c3SSam Protsenko #define CLK_MOUT_DPU 11 24*2ae5c2c3SSam Protsenko #define CLK_MOUT_HSI_BUS 12 25*2ae5c2c3SSam Protsenko #define CLK_MOUT_HSI_MMC_CARD 13 26*2ae5c2c3SSam Protsenko #define CLK_MOUT_HSI_USB20DRD 14 27*2ae5c2c3SSam Protsenko #define CLK_MOUT_PERI_BUS 15 28*2ae5c2c3SSam Protsenko #define CLK_MOUT_PERI_UART 16 29*2ae5c2c3SSam Protsenko #define CLK_MOUT_PERI_IP 17 30*2ae5c2c3SSam Protsenko #define CLK_DOUT_SHARED0_DIV3 18 31*2ae5c2c3SSam Protsenko #define CLK_DOUT_SHARED0_DIV2 19 32*2ae5c2c3SSam Protsenko #define CLK_DOUT_SHARED1_DIV3 20 33*2ae5c2c3SSam Protsenko #define CLK_DOUT_SHARED1_DIV2 21 34*2ae5c2c3SSam Protsenko #define CLK_DOUT_SHARED0_DIV4 22 35*2ae5c2c3SSam Protsenko #define CLK_DOUT_SHARED1_DIV4 23 36*2ae5c2c3SSam Protsenko #define CLK_DOUT_CORE_BUS 24 37*2ae5c2c3SSam Protsenko #define CLK_DOUT_CORE_CCI 25 38*2ae5c2c3SSam Protsenko #define CLK_DOUT_CORE_MMC_EMBD 26 39*2ae5c2c3SSam Protsenko #define CLK_DOUT_CORE_SSS 27 40*2ae5c2c3SSam Protsenko #define CLK_DOUT_DPU 28 41*2ae5c2c3SSam Protsenko #define CLK_DOUT_HSI_BUS 29 42*2ae5c2c3SSam Protsenko #define CLK_DOUT_HSI_MMC_CARD 30 43*2ae5c2c3SSam Protsenko #define CLK_DOUT_HSI_USB20DRD 31 44*2ae5c2c3SSam Protsenko #define CLK_DOUT_PERI_BUS 32 45*2ae5c2c3SSam Protsenko #define CLK_DOUT_PERI_UART 33 46*2ae5c2c3SSam Protsenko #define CLK_DOUT_PERI_IP 34 47*2ae5c2c3SSam Protsenko #define CLK_GOUT_CORE_BUS 35 48*2ae5c2c3SSam Protsenko #define CLK_GOUT_CORE_CCI 36 49*2ae5c2c3SSam Protsenko #define CLK_GOUT_CORE_MMC_EMBD 37 50*2ae5c2c3SSam Protsenko #define CLK_GOUT_CORE_SSS 38 51*2ae5c2c3SSam Protsenko #define CLK_GOUT_DPU 39 52*2ae5c2c3SSam Protsenko #define CLK_GOUT_HSI_BUS 40 53*2ae5c2c3SSam Protsenko #define CLK_GOUT_HSI_MMC_CARD 41 54*2ae5c2c3SSam Protsenko #define CLK_GOUT_HSI_USB20DRD 42 55*2ae5c2c3SSam Protsenko #define CLK_GOUT_PERI_BUS 43 56*2ae5c2c3SSam Protsenko #define CLK_GOUT_PERI_UART 44 57*2ae5c2c3SSam Protsenko #define CLK_GOUT_PERI_IP 45 58*2ae5c2c3SSam Protsenko #define TOP_NR_CLK 46 59*2ae5c2c3SSam Protsenko 60*2ae5c2c3SSam Protsenko /* CMU_HSI */ 61*2ae5c2c3SSam Protsenko #define CLK_MOUT_HSI_BUS_USER 1 62*2ae5c2c3SSam Protsenko #define CLK_MOUT_HSI_MMC_CARD_USER 2 63*2ae5c2c3SSam Protsenko #define CLK_MOUT_HSI_USB20DRD_USER 3 64*2ae5c2c3SSam Protsenko #define CLK_MOUT_HSI_RTC 4 65*2ae5c2c3SSam Protsenko #define CLK_GOUT_USB_RTC_CLK 5 66*2ae5c2c3SSam Protsenko #define CLK_GOUT_USB_REF_CLK 6 67*2ae5c2c3SSam Protsenko #define CLK_GOUT_USB_PHY_REF_CLK 7 68*2ae5c2c3SSam Protsenko #define CLK_GOUT_USB_PHY_ACLK 8 69*2ae5c2c3SSam Protsenko #define CLK_GOUT_USB_BUS_EARLY_CLK 9 70*2ae5c2c3SSam Protsenko #define CLK_GOUT_GPIO_HSI_PCLK 10 71*2ae5c2c3SSam Protsenko #define CLK_GOUT_MMC_CARD_ACLK 11 72*2ae5c2c3SSam Protsenko #define CLK_GOUT_MMC_CARD_SDCLKIN 12 73*2ae5c2c3SSam Protsenko #define CLK_GOUT_SYSREG_HSI_PCLK 13 74*2ae5c2c3SSam Protsenko #define HSI_NR_CLK 14 75*2ae5c2c3SSam Protsenko 76*2ae5c2c3SSam Protsenko /* CMU_PERI */ 77*2ae5c2c3SSam Protsenko #define CLK_MOUT_PERI_BUS_USER 1 78*2ae5c2c3SSam Protsenko #define CLK_MOUT_PERI_UART_USER 2 79*2ae5c2c3SSam Protsenko #define CLK_MOUT_PERI_HSI2C_USER 3 80*2ae5c2c3SSam Protsenko #define CLK_MOUT_PERI_SPI_USER 4 81*2ae5c2c3SSam Protsenko #define CLK_DOUT_PERI_HSI2C0 5 82*2ae5c2c3SSam Protsenko #define CLK_DOUT_PERI_HSI2C1 6 83*2ae5c2c3SSam Protsenko #define CLK_DOUT_PERI_HSI2C2 7 84*2ae5c2c3SSam Protsenko #define CLK_DOUT_PERI_SPI0 8 85*2ae5c2c3SSam Protsenko #define CLK_GOUT_PERI_HSI2C0 9 86*2ae5c2c3SSam Protsenko #define CLK_GOUT_PERI_HSI2C1 10 87*2ae5c2c3SSam Protsenko #define CLK_GOUT_PERI_HSI2C2 11 88*2ae5c2c3SSam Protsenko #define CLK_GOUT_GPIO_PERI_PCLK 12 89*2ae5c2c3SSam Protsenko #define CLK_GOUT_HSI2C0_IPCLK 13 90*2ae5c2c3SSam Protsenko #define CLK_GOUT_HSI2C0_PCLK 14 91*2ae5c2c3SSam Protsenko #define CLK_GOUT_HSI2C1_IPCLK 15 92*2ae5c2c3SSam Protsenko #define CLK_GOUT_HSI2C1_PCLK 16 93*2ae5c2c3SSam Protsenko #define CLK_GOUT_HSI2C2_IPCLK 17 94*2ae5c2c3SSam Protsenko #define CLK_GOUT_HSI2C2_PCLK 18 95*2ae5c2c3SSam Protsenko #define CLK_GOUT_I2C0_PCLK 19 96*2ae5c2c3SSam Protsenko #define CLK_GOUT_I2C1_PCLK 20 97*2ae5c2c3SSam Protsenko #define CLK_GOUT_I2C2_PCLK 21 98*2ae5c2c3SSam Protsenko #define CLK_GOUT_I2C3_PCLK 22 99*2ae5c2c3SSam Protsenko #define CLK_GOUT_I2C4_PCLK 23 100*2ae5c2c3SSam Protsenko #define CLK_GOUT_I2C5_PCLK 24 101*2ae5c2c3SSam Protsenko #define CLK_GOUT_I2C6_PCLK 25 102*2ae5c2c3SSam Protsenko #define CLK_GOUT_MCT_PCLK 26 103*2ae5c2c3SSam Protsenko #define CLK_GOUT_PWM_MOTOR_PCLK 27 104*2ae5c2c3SSam Protsenko #define CLK_GOUT_SPI0_IPCLK 28 105*2ae5c2c3SSam Protsenko #define CLK_GOUT_SPI0_PCLK 29 106*2ae5c2c3SSam Protsenko #define CLK_GOUT_SYSREG_PERI_PCLK 30 107*2ae5c2c3SSam Protsenko #define CLK_GOUT_UART_IPCLK 31 108*2ae5c2c3SSam Protsenko #define CLK_GOUT_UART_PCLK 32 109*2ae5c2c3SSam Protsenko #define CLK_GOUT_WDT0_PCLK 33 110*2ae5c2c3SSam Protsenko #define CLK_GOUT_WDT1_PCLK 34 111*2ae5c2c3SSam Protsenko #define PERI_NR_CLK 35 112*2ae5c2c3SSam Protsenko 113*2ae5c2c3SSam Protsenko /* CMU_CORE */ 114*2ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_BUS_USER 1 115*2ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_CCI_USER 2 116*2ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_MMC_EMBD_USER 3 117*2ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_SSS_USER 4 118*2ae5c2c3SSam Protsenko #define CLK_MOUT_CORE_GIC 5 119*2ae5c2c3SSam Protsenko #define CLK_DOUT_CORE_BUSP 6 120*2ae5c2c3SSam Protsenko #define CLK_GOUT_CCI_ACLK 7 121*2ae5c2c3SSam Protsenko #define CLK_GOUT_GIC_CLK 8 122*2ae5c2c3SSam Protsenko #define CLK_GOUT_MMC_EMBD_ACLK 9 123*2ae5c2c3SSam Protsenko #define CLK_GOUT_MMC_EMBD_SDCLKIN 10 124*2ae5c2c3SSam Protsenko #define CLK_GOUT_SSS_ACLK 11 125*2ae5c2c3SSam Protsenko #define CLK_GOUT_SSS_PCLK 12 126*2ae5c2c3SSam Protsenko #define CORE_NR_CLK 13 127*2ae5c2c3SSam Protsenko 128*2ae5c2c3SSam Protsenko /* CMU_DPU */ 129*2ae5c2c3SSam Protsenko #define CLK_MOUT_DPU_USER 1 130*2ae5c2c3SSam Protsenko #define CLK_DOUT_DPU_BUSP 2 131*2ae5c2c3SSam Protsenko #define CLK_GOUT_DPU_CMU_DPU_PCLK 3 132*2ae5c2c3SSam Protsenko #define CLK_GOUT_DPU_DECON0_ACLK 4 133*2ae5c2c3SSam Protsenko #define CLK_GOUT_DPU_DMA_ACLK 5 134*2ae5c2c3SSam Protsenko #define CLK_GOUT_DPU_DPP_ACLK 6 135*2ae5c2c3SSam Protsenko #define CLK_GOUT_DPU_PPMU_ACLK 7 136*2ae5c2c3SSam Protsenko #define CLK_GOUT_DPU_PPMU_PCLK 8 137*2ae5c2c3SSam Protsenko #define CLK_GOUT_DPU_SMMU_CLK 9 138*2ae5c2c3SSam Protsenko #define CLK_GOUT_DPU_SYSREG_PCLK 10 139*2ae5c2c3SSam Protsenko #define DPU_NR_CLK 11 140*2ae5c2c3SSam Protsenko 141*2ae5c2c3SSam Protsenko #endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */ 142