1591020a5SDavid Virag /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2591020a5SDavid Virag /* 3591020a5SDavid Virag * Copyright (c) 2021 Dávid Virág 4591020a5SDavid Virag * 5591020a5SDavid Virag * Device Tree binding constants for Exynos7885 clock controller. 6591020a5SDavid Virag */ 7591020a5SDavid Virag 8591020a5SDavid Virag #ifndef _DT_BINDINGS_CLOCK_EXYNOS_7885_H 9591020a5SDavid Virag #define _DT_BINDINGS_CLOCK_EXYNOS_7885_H 10591020a5SDavid Virag 11591020a5SDavid Virag /* CMU_TOP */ 12591020a5SDavid Virag #define CLK_FOUT_SHARED0_PLL 1 13591020a5SDavid Virag #define CLK_FOUT_SHARED1_PLL 2 14591020a5SDavid Virag #define CLK_DOUT_SHARED0_DIV2 3 15591020a5SDavid Virag #define CLK_DOUT_SHARED0_DIV3 4 16591020a5SDavid Virag #define CLK_DOUT_SHARED0_DIV4 5 17591020a5SDavid Virag #define CLK_DOUT_SHARED0_DIV5 6 18591020a5SDavid Virag #define CLK_DOUT_SHARED1_DIV2 7 19591020a5SDavid Virag #define CLK_DOUT_SHARED1_DIV3 8 20591020a5SDavid Virag #define CLK_DOUT_SHARED1_DIV4 9 21591020a5SDavid Virag #define CLK_MOUT_CORE_BUS 10 22591020a5SDavid Virag #define CLK_MOUT_CORE_CCI 11 23591020a5SDavid Virag #define CLK_MOUT_CORE_G3D 12 24591020a5SDavid Virag #define CLK_DOUT_CORE_BUS 13 25591020a5SDavid Virag #define CLK_DOUT_CORE_CCI 14 26591020a5SDavid Virag #define CLK_DOUT_CORE_G3D 15 27591020a5SDavid Virag #define CLK_GOUT_CORE_BUS 16 28591020a5SDavid Virag #define CLK_GOUT_CORE_CCI 17 29591020a5SDavid Virag #define CLK_GOUT_CORE_G3D 18 30591020a5SDavid Virag #define CLK_MOUT_PERI_BUS 19 31591020a5SDavid Virag #define CLK_MOUT_PERI_SPI0 20 32591020a5SDavid Virag #define CLK_MOUT_PERI_SPI1 21 33591020a5SDavid Virag #define CLK_MOUT_PERI_UART0 22 34591020a5SDavid Virag #define CLK_MOUT_PERI_UART1 23 35591020a5SDavid Virag #define CLK_MOUT_PERI_UART2 24 36591020a5SDavid Virag #define CLK_MOUT_PERI_USI0 25 37591020a5SDavid Virag #define CLK_MOUT_PERI_USI1 26 38591020a5SDavid Virag #define CLK_MOUT_PERI_USI2 27 39591020a5SDavid Virag #define CLK_DOUT_PERI_BUS 28 40591020a5SDavid Virag #define CLK_DOUT_PERI_SPI0 29 41591020a5SDavid Virag #define CLK_DOUT_PERI_SPI1 30 42591020a5SDavid Virag #define CLK_DOUT_PERI_UART0 31 43591020a5SDavid Virag #define CLK_DOUT_PERI_UART1 32 44591020a5SDavid Virag #define CLK_DOUT_PERI_UART2 33 45591020a5SDavid Virag #define CLK_DOUT_PERI_USI0 34 46591020a5SDavid Virag #define CLK_DOUT_PERI_USI1 35 47591020a5SDavid Virag #define CLK_DOUT_PERI_USI2 36 48591020a5SDavid Virag #define CLK_GOUT_PERI_BUS 37 49591020a5SDavid Virag #define CLK_GOUT_PERI_SPI0 38 50591020a5SDavid Virag #define CLK_GOUT_PERI_SPI1 39 51591020a5SDavid Virag #define CLK_GOUT_PERI_UART0 40 52591020a5SDavid Virag #define CLK_GOUT_PERI_UART1 41 53591020a5SDavid Virag #define CLK_GOUT_PERI_UART2 42 54591020a5SDavid Virag #define CLK_GOUT_PERI_USI0 43 55591020a5SDavid Virag #define CLK_GOUT_PERI_USI1 44 56591020a5SDavid Virag #define CLK_GOUT_PERI_USI2 45 57*cd268e30SDavid Virag #define CLK_MOUT_FSYS_BUS 46 58*cd268e30SDavid Virag #define CLK_MOUT_FSYS_MMC_CARD 47 59*cd268e30SDavid Virag #define CLK_MOUT_FSYS_MMC_EMBD 48 60*cd268e30SDavid Virag #define CLK_MOUT_FSYS_MMC_SDIO 49 61*cd268e30SDavid Virag #define CLK_MOUT_FSYS_USB30DRD 50 62*cd268e30SDavid Virag #define CLK_DOUT_FSYS_BUS 51 63*cd268e30SDavid Virag #define CLK_DOUT_FSYS_MMC_CARD 52 64*cd268e30SDavid Virag #define CLK_DOUT_FSYS_MMC_EMBD 53 65*cd268e30SDavid Virag #define CLK_DOUT_FSYS_MMC_SDIO 54 66*cd268e30SDavid Virag #define CLK_DOUT_FSYS_USB30DRD 55 67*cd268e30SDavid Virag #define CLK_GOUT_FSYS_BUS 56 68*cd268e30SDavid Virag #define CLK_GOUT_FSYS_MMC_CARD 57 69*cd268e30SDavid Virag #define CLK_GOUT_FSYS_MMC_EMBD 58 70*cd268e30SDavid Virag #define CLK_GOUT_FSYS_MMC_SDIO 59 71*cd268e30SDavid Virag #define CLK_GOUT_FSYS_USB30DRD 60 72*cd268e30SDavid Virag #define TOP_NR_CLK 61 73591020a5SDavid Virag 74591020a5SDavid Virag /* CMU_CORE */ 75591020a5SDavid Virag #define CLK_MOUT_CORE_BUS_USER 1 76591020a5SDavid Virag #define CLK_MOUT_CORE_CCI_USER 2 77591020a5SDavid Virag #define CLK_MOUT_CORE_G3D_USER 3 78591020a5SDavid Virag #define CLK_MOUT_CORE_GIC 4 79591020a5SDavid Virag #define CLK_DOUT_CORE_BUSP 5 80591020a5SDavid Virag #define CLK_GOUT_CCI_ACLK 6 81591020a5SDavid Virag #define CLK_GOUT_GIC400_CLK 7 82591020a5SDavid Virag #define CORE_NR_CLK 8 83591020a5SDavid Virag 84591020a5SDavid Virag /* CMU_PERI */ 85591020a5SDavid Virag #define CLK_MOUT_PERI_BUS_USER 1 86591020a5SDavid Virag #define CLK_MOUT_PERI_SPI0_USER 2 87591020a5SDavid Virag #define CLK_MOUT_PERI_SPI1_USER 3 88591020a5SDavid Virag #define CLK_MOUT_PERI_UART0_USER 4 89591020a5SDavid Virag #define CLK_MOUT_PERI_UART1_USER 5 90591020a5SDavid Virag #define CLK_MOUT_PERI_UART2_USER 6 91591020a5SDavid Virag #define CLK_MOUT_PERI_USI0_USER 7 92591020a5SDavid Virag #define CLK_MOUT_PERI_USI1_USER 8 93591020a5SDavid Virag #define CLK_MOUT_PERI_USI2_USER 9 94591020a5SDavid Virag #define CLK_GOUT_GPIO_TOP_PCLK 10 95591020a5SDavid Virag #define CLK_GOUT_HSI2C0_PCLK 11 96591020a5SDavid Virag #define CLK_GOUT_HSI2C1_PCLK 12 97591020a5SDavid Virag #define CLK_GOUT_HSI2C2_PCLK 13 98591020a5SDavid Virag #define CLK_GOUT_HSI2C3_PCLK 14 99591020a5SDavid Virag #define CLK_GOUT_I2C0_PCLK 15 100591020a5SDavid Virag #define CLK_GOUT_I2C1_PCLK 16 101591020a5SDavid Virag #define CLK_GOUT_I2C2_PCLK 17 102591020a5SDavid Virag #define CLK_GOUT_I2C3_PCLK 18 103591020a5SDavid Virag #define CLK_GOUT_I2C4_PCLK 19 104591020a5SDavid Virag #define CLK_GOUT_I2C5_PCLK 20 105591020a5SDavid Virag #define CLK_GOUT_I2C6_PCLK 21 106591020a5SDavid Virag #define CLK_GOUT_I2C7_PCLK 22 107591020a5SDavid Virag #define CLK_GOUT_PWM_MOTOR_PCLK 23 108591020a5SDavid Virag #define CLK_GOUT_SPI0_PCLK 24 109591020a5SDavid Virag #define CLK_GOUT_SPI0_EXT_CLK 25 110591020a5SDavid Virag #define CLK_GOUT_SPI1_PCLK 26 111591020a5SDavid Virag #define CLK_GOUT_SPI1_EXT_CLK 27 112591020a5SDavid Virag #define CLK_GOUT_UART0_EXT_UCLK 28 113591020a5SDavid Virag #define CLK_GOUT_UART0_PCLK 29 114591020a5SDavid Virag #define CLK_GOUT_UART1_EXT_UCLK 30 115591020a5SDavid Virag #define CLK_GOUT_UART1_PCLK 31 116591020a5SDavid Virag #define CLK_GOUT_UART2_EXT_UCLK 32 117591020a5SDavid Virag #define CLK_GOUT_UART2_PCLK 33 118591020a5SDavid Virag #define CLK_GOUT_USI0_PCLK 34 119591020a5SDavid Virag #define CLK_GOUT_USI0_SCLK 35 120591020a5SDavid Virag #define CLK_GOUT_USI1_PCLK 36 121591020a5SDavid Virag #define CLK_GOUT_USI1_SCLK 37 122591020a5SDavid Virag #define CLK_GOUT_USI2_PCLK 38 123591020a5SDavid Virag #define CLK_GOUT_USI2_SCLK 39 124591020a5SDavid Virag #define CLK_GOUT_MCT_PCLK 40 125591020a5SDavid Virag #define CLK_GOUT_SYSREG_PERI_PCLK 41 126591020a5SDavid Virag #define CLK_GOUT_WDT0_PCLK 42 127591020a5SDavid Virag #define CLK_GOUT_WDT1_PCLK 43 128591020a5SDavid Virag #define PERI_NR_CLK 44 129591020a5SDavid Virag 130*cd268e30SDavid Virag /* CMU_FSYS */ 131*cd268e30SDavid Virag #define CLK_MOUT_FSYS_BUS_USER 1 132*cd268e30SDavid Virag #define CLK_MOUT_FSYS_MMC_CARD_USER 2 133*cd268e30SDavid Virag #define CLK_MOUT_FSYS_MMC_EMBD_USER 3 134*cd268e30SDavid Virag #define CLK_MOUT_FSYS_MMC_SDIO_USER 4 135*cd268e30SDavid Virag #define CLK_MOUT_FSYS_USB30DRD_USER 4 136*cd268e30SDavid Virag #define CLK_GOUT_MMC_CARD_ACLK 5 137*cd268e30SDavid Virag #define CLK_GOUT_MMC_CARD_SDCLKIN 6 138*cd268e30SDavid Virag #define CLK_GOUT_MMC_EMBD_ACLK 7 139*cd268e30SDavid Virag #define CLK_GOUT_MMC_EMBD_SDCLKIN 8 140*cd268e30SDavid Virag #define CLK_GOUT_MMC_SDIO_ACLK 9 141*cd268e30SDavid Virag #define CLK_GOUT_MMC_SDIO_SDCLKIN 10 142*cd268e30SDavid Virag #define FSYS_NR_CLK 11 143*cd268e30SDavid Virag 144591020a5SDavid Virag #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */ 145