1*591020a5SDavid Virag /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*591020a5SDavid Virag /* 3*591020a5SDavid Virag * Copyright (c) 2021 Dávid Virág 4*591020a5SDavid Virag * 5*591020a5SDavid Virag * Device Tree binding constants for Exynos7885 clock controller. 6*591020a5SDavid Virag */ 7*591020a5SDavid Virag 8*591020a5SDavid Virag #ifndef _DT_BINDINGS_CLOCK_EXYNOS_7885_H 9*591020a5SDavid Virag #define _DT_BINDINGS_CLOCK_EXYNOS_7885_H 10*591020a5SDavid Virag 11*591020a5SDavid Virag /* CMU_TOP */ 12*591020a5SDavid Virag #define CLK_FOUT_SHARED0_PLL 1 13*591020a5SDavid Virag #define CLK_FOUT_SHARED1_PLL 2 14*591020a5SDavid Virag #define CLK_DOUT_SHARED0_DIV2 3 15*591020a5SDavid Virag #define CLK_DOUT_SHARED0_DIV3 4 16*591020a5SDavid Virag #define CLK_DOUT_SHARED0_DIV4 5 17*591020a5SDavid Virag #define CLK_DOUT_SHARED0_DIV5 6 18*591020a5SDavid Virag #define CLK_DOUT_SHARED1_DIV2 7 19*591020a5SDavid Virag #define CLK_DOUT_SHARED1_DIV3 8 20*591020a5SDavid Virag #define CLK_DOUT_SHARED1_DIV4 9 21*591020a5SDavid Virag #define CLK_MOUT_CORE_BUS 10 22*591020a5SDavid Virag #define CLK_MOUT_CORE_CCI 11 23*591020a5SDavid Virag #define CLK_MOUT_CORE_G3D 12 24*591020a5SDavid Virag #define CLK_DOUT_CORE_BUS 13 25*591020a5SDavid Virag #define CLK_DOUT_CORE_CCI 14 26*591020a5SDavid Virag #define CLK_DOUT_CORE_G3D 15 27*591020a5SDavid Virag #define CLK_GOUT_CORE_BUS 16 28*591020a5SDavid Virag #define CLK_GOUT_CORE_CCI 17 29*591020a5SDavid Virag #define CLK_GOUT_CORE_G3D 18 30*591020a5SDavid Virag #define CLK_MOUT_PERI_BUS 19 31*591020a5SDavid Virag #define CLK_MOUT_PERI_SPI0 20 32*591020a5SDavid Virag #define CLK_MOUT_PERI_SPI1 21 33*591020a5SDavid Virag #define CLK_MOUT_PERI_UART0 22 34*591020a5SDavid Virag #define CLK_MOUT_PERI_UART1 23 35*591020a5SDavid Virag #define CLK_MOUT_PERI_UART2 24 36*591020a5SDavid Virag #define CLK_MOUT_PERI_USI0 25 37*591020a5SDavid Virag #define CLK_MOUT_PERI_USI1 26 38*591020a5SDavid Virag #define CLK_MOUT_PERI_USI2 27 39*591020a5SDavid Virag #define CLK_DOUT_PERI_BUS 28 40*591020a5SDavid Virag #define CLK_DOUT_PERI_SPI0 29 41*591020a5SDavid Virag #define CLK_DOUT_PERI_SPI1 30 42*591020a5SDavid Virag #define CLK_DOUT_PERI_UART0 31 43*591020a5SDavid Virag #define CLK_DOUT_PERI_UART1 32 44*591020a5SDavid Virag #define CLK_DOUT_PERI_UART2 33 45*591020a5SDavid Virag #define CLK_DOUT_PERI_USI0 34 46*591020a5SDavid Virag #define CLK_DOUT_PERI_USI1 35 47*591020a5SDavid Virag #define CLK_DOUT_PERI_USI2 36 48*591020a5SDavid Virag #define CLK_GOUT_PERI_BUS 37 49*591020a5SDavid Virag #define CLK_GOUT_PERI_SPI0 38 50*591020a5SDavid Virag #define CLK_GOUT_PERI_SPI1 39 51*591020a5SDavid Virag #define CLK_GOUT_PERI_UART0 40 52*591020a5SDavid Virag #define CLK_GOUT_PERI_UART1 41 53*591020a5SDavid Virag #define CLK_GOUT_PERI_UART2 42 54*591020a5SDavid Virag #define CLK_GOUT_PERI_USI0 43 55*591020a5SDavid Virag #define CLK_GOUT_PERI_USI1 44 56*591020a5SDavid Virag #define CLK_GOUT_PERI_USI2 45 57*591020a5SDavid Virag #define TOP_NR_CLK 46 58*591020a5SDavid Virag 59*591020a5SDavid Virag /* CMU_CORE */ 60*591020a5SDavid Virag #define CLK_MOUT_CORE_BUS_USER 1 61*591020a5SDavid Virag #define CLK_MOUT_CORE_CCI_USER 2 62*591020a5SDavid Virag #define CLK_MOUT_CORE_G3D_USER 3 63*591020a5SDavid Virag #define CLK_MOUT_CORE_GIC 4 64*591020a5SDavid Virag #define CLK_DOUT_CORE_BUSP 5 65*591020a5SDavid Virag #define CLK_GOUT_CCI_ACLK 6 66*591020a5SDavid Virag #define CLK_GOUT_GIC400_CLK 7 67*591020a5SDavid Virag #define CORE_NR_CLK 8 68*591020a5SDavid Virag 69*591020a5SDavid Virag /* CMU_PERI */ 70*591020a5SDavid Virag #define CLK_MOUT_PERI_BUS_USER 1 71*591020a5SDavid Virag #define CLK_MOUT_PERI_SPI0_USER 2 72*591020a5SDavid Virag #define CLK_MOUT_PERI_SPI1_USER 3 73*591020a5SDavid Virag #define CLK_MOUT_PERI_UART0_USER 4 74*591020a5SDavid Virag #define CLK_MOUT_PERI_UART1_USER 5 75*591020a5SDavid Virag #define CLK_MOUT_PERI_UART2_USER 6 76*591020a5SDavid Virag #define CLK_MOUT_PERI_USI0_USER 7 77*591020a5SDavid Virag #define CLK_MOUT_PERI_USI1_USER 8 78*591020a5SDavid Virag #define CLK_MOUT_PERI_USI2_USER 9 79*591020a5SDavid Virag #define CLK_GOUT_GPIO_TOP_PCLK 10 80*591020a5SDavid Virag #define CLK_GOUT_HSI2C0_PCLK 11 81*591020a5SDavid Virag #define CLK_GOUT_HSI2C1_PCLK 12 82*591020a5SDavid Virag #define CLK_GOUT_HSI2C2_PCLK 13 83*591020a5SDavid Virag #define CLK_GOUT_HSI2C3_PCLK 14 84*591020a5SDavid Virag #define CLK_GOUT_I2C0_PCLK 15 85*591020a5SDavid Virag #define CLK_GOUT_I2C1_PCLK 16 86*591020a5SDavid Virag #define CLK_GOUT_I2C2_PCLK 17 87*591020a5SDavid Virag #define CLK_GOUT_I2C3_PCLK 18 88*591020a5SDavid Virag #define CLK_GOUT_I2C4_PCLK 19 89*591020a5SDavid Virag #define CLK_GOUT_I2C5_PCLK 20 90*591020a5SDavid Virag #define CLK_GOUT_I2C6_PCLK 21 91*591020a5SDavid Virag #define CLK_GOUT_I2C7_PCLK 22 92*591020a5SDavid Virag #define CLK_GOUT_PWM_MOTOR_PCLK 23 93*591020a5SDavid Virag #define CLK_GOUT_SPI0_PCLK 24 94*591020a5SDavid Virag #define CLK_GOUT_SPI0_EXT_CLK 25 95*591020a5SDavid Virag #define CLK_GOUT_SPI1_PCLK 26 96*591020a5SDavid Virag #define CLK_GOUT_SPI1_EXT_CLK 27 97*591020a5SDavid Virag #define CLK_GOUT_UART0_EXT_UCLK 28 98*591020a5SDavid Virag #define CLK_GOUT_UART0_PCLK 29 99*591020a5SDavid Virag #define CLK_GOUT_UART1_EXT_UCLK 30 100*591020a5SDavid Virag #define CLK_GOUT_UART1_PCLK 31 101*591020a5SDavid Virag #define CLK_GOUT_UART2_EXT_UCLK 32 102*591020a5SDavid Virag #define CLK_GOUT_UART2_PCLK 33 103*591020a5SDavid Virag #define CLK_GOUT_USI0_PCLK 34 104*591020a5SDavid Virag #define CLK_GOUT_USI0_SCLK 35 105*591020a5SDavid Virag #define CLK_GOUT_USI1_PCLK 36 106*591020a5SDavid Virag #define CLK_GOUT_USI1_SCLK 37 107*591020a5SDavid Virag #define CLK_GOUT_USI2_PCLK 38 108*591020a5SDavid Virag #define CLK_GOUT_USI2_SCLK 39 109*591020a5SDavid Virag #define CLK_GOUT_MCT_PCLK 40 110*591020a5SDavid Virag #define CLK_GOUT_SYSREG_PERI_PCLK 41 111*591020a5SDavid Virag #define CLK_GOUT_WDT0_PCLK 42 112*591020a5SDavid Virag #define CLK_GOUT_WDT1_PCLK 43 113*591020a5SDavid Virag #define PERI_NR_CLK 44 114*591020a5SDavid Virag 115*591020a5SDavid Virag #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */ 116