1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Chanwoo Choi <cw00.choi@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 11 #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 12 13 /* CMU_TOP */ 14 #define CLK_FOUT_ISP_PLL 1 15 #define CLK_FOUT_AUD_PLL 2 16 17 #define CLK_MOUT_AUD_PLL 10 18 #define CLK_MOUT_ISP_PLL 11 19 #define CLK_MOUT_AUD_PLL_USER_T 12 20 #define CLK_MOUT_MPHY_PLL_USER 13 21 #define CLK_MOUT_MFC_PLL_USER 14 22 #define CLK_MOUT_BUS_PLL_USER 15 23 #define CLK_MOUT_ACLK_HEVC_400 16 24 #define CLK_MOUT_ACLK_CAM1_333 17 25 #define CLK_MOUT_ACLK_CAM1_552_B 18 26 #define CLK_MOUT_ACLK_CAM1_552_A 19 27 #define CLK_MOUT_ACLK_ISP_DIS_400 20 28 #define CLK_MOUT_ACLK_ISP_400 21 29 #define CLK_MOUT_ACLK_BUS0_400 22 30 #define CLK_MOUT_ACLK_MSCL_400_B 23 31 #define CLK_MOUT_ACLK_MSCL_400_A 24 32 #define CLK_MOUT_ACLK_GSCL_333 25 33 #define CLK_MOUT_ACLK_G2D_400_B 26 34 #define CLK_MOUT_ACLK_G2D_400_A 27 35 #define CLK_MOUT_SCLK_JPEG_C 28 36 #define CLK_MOUT_SCLK_JPEG_B 29 37 #define CLK_MOUT_SCLK_JPEG_A 30 38 #define CLK_MOUT_SCLK_MMC2_B 31 39 #define CLK_MOUT_SCLK_MMC2_A 32 40 #define CLK_MOUT_SCLK_MMC1_B 33 41 #define CLK_MOUT_SCLK_MMC1_A 34 42 #define CLK_MOUT_SCLK_MMC0_D 35 43 #define CLK_MOUT_SCLK_MMC0_C 36 44 #define CLK_MOUT_SCLK_MMC0_B 37 45 #define CLK_MOUT_SCLK_MMC0_A 38 46 #define CLK_MOUT_SCLK_SPI4 39 47 #define CLK_MOUT_SCLK_SPI3 40 48 #define CLK_MOUT_SCLK_UART2 41 49 #define CLK_MOUT_SCLK_UART1 42 50 #define CLK_MOUT_SCLK_UART0 43 51 #define CLK_MOUT_SCLK_SPI2 44 52 #define CLK_MOUT_SCLK_SPI1 45 53 #define CLK_MOUT_SCLK_SPI0 46 54 #define CLK_MOUT_ACLK_MFC_400_C 47 55 #define CLK_MOUT_ACLK_MFC_400_B 48 56 #define CLK_MOUT_ACLK_MFC_400_A 49 57 #define CLK_MOUT_SCLK_ISP_SENSOR2 50 58 #define CLK_MOUT_SCLK_ISP_SENSOR1 51 59 #define CLK_MOUT_SCLK_ISP_SENSOR0 52 60 #define CLK_MOUT_SCLK_ISP_UART 53 61 #define CLK_MOUT_SCLK_ISP_SPI1 54 62 #define CLK_MOUT_SCLK_ISP_SPI0 55 63 #define CLK_MOUT_SCLK_PCIE_100 56 64 #define CLK_MOUT_SCLK_UFSUNIPRO 57 65 #define CLK_MOUT_SCLK_USBHOST30 58 66 #define CLK_MOUT_SCLK_USBDRD30 59 67 #define CLK_MOUT_SCLK_SLIMBUS 60 68 #define CLK_MOUT_SCLK_SPDIF 61 69 #define CLK_MOUT_SCLK_AUDIO1 62 70 #define CLK_MOUT_SCLK_AUDIO0 63 71 #define CLK_MOUT_SCLK_HDMI_SPDIF 64 72 73 #define CLK_DIV_ACLK_FSYS_200 100 74 #define CLK_DIV_ACLK_IMEM_SSSX_266 101 75 #define CLK_DIV_ACLK_IMEM_200 102 76 #define CLK_DIV_ACLK_IMEM_266 103 77 #define CLK_DIV_ACLK_PERIC_66_B 104 78 #define CLK_DIV_ACLK_PERIC_66_A 105 79 #define CLK_DIV_ACLK_PERIS_66_B 106 80 #define CLK_DIV_ACLK_PERIS_66_A 107 81 #define CLK_DIV_SCLK_MMC1_B 108 82 #define CLK_DIV_SCLK_MMC1_A 109 83 #define CLK_DIV_SCLK_MMC0_B 110 84 #define CLK_DIV_SCLK_MMC0_A 111 85 #define CLK_DIV_SCLK_MMC2_B 112 86 #define CLK_DIV_SCLK_MMC2_A 113 87 #define CLK_DIV_SCLK_SPI1_B 114 88 #define CLK_DIV_SCLK_SPI1_A 115 89 #define CLK_DIV_SCLK_SPI0_B 116 90 #define CLK_DIV_SCLK_SPI0_A 117 91 #define CLK_DIV_SCLK_SPI2_B 118 92 #define CLK_DIV_SCLK_SPI2_A 119 93 #define CLK_DIV_SCLK_UART2 120 94 #define CLK_DIV_SCLK_UART1 121 95 #define CLK_DIV_SCLK_UART0 122 96 #define CLK_DIV_SCLK_SPI4_B 123 97 #define CLK_DIV_SCLK_SPI4_A 124 98 #define CLK_DIV_SCLK_SPI3_B 125 99 #define CLK_DIV_SCLK_SPI3_A 126 100 #define CLK_DIV_SCLK_I2S1 127 101 #define CLK_DIV_SCLK_PCM1 128 102 #define CLK_DIV_SCLK_AUDIO1 129 103 #define CLK_DIV_SCLK_AUDIO0 130 104 #define CLK_DIV_ACLK_GSCL_111 131 105 #define CLK_DIV_ACLK_GSCL_333 132 106 #define CLK_DIV_ACLK_HEVC_400 133 107 #define CLK_DIV_ACLK_MFC_400 134 108 #define CLK_DIV_ACLK_G2D_266 135 109 #define CLK_DIV_ACLK_G2D_400 136 110 #define CLK_DIV_ACLK_G3D_400 137 111 #define CLK_DIV_ACLK_BUS0_400 138 112 #define CLK_DIV_ACLK_BUS1_400 139 113 #define CLK_DIV_SCLK_PCIE_100 140 114 #define CLK_DIV_SCLK_USBHOST30 141 115 #define CLK_DIV_SCLK_UFSUNIPRO 142 116 #define CLK_DIV_SCLK_USBDRD30 143 117 #define CLK_DIV_SCLK_JPEG 144 118 #define CLK_DIV_ACLK_MSCL_400 145 119 120 #define CLK_ACLK_PERIC_66 200 121 #define CLK_ACLK_PERIS_66 201 122 #define CLK_ACLK_FSYS_200 202 123 #define CLK_SCLK_MMC2_FSYS 203 124 #define CLK_SCLK_MMC1_FSYS 204 125 #define CLK_SCLK_MMC0_FSYS 205 126 #define CLK_SCLK_SPI4_PERIC 206 127 #define CLK_SCLK_SPI3_PERIC 207 128 #define CLK_SCLK_UART2_PERIC 208 129 #define CLK_SCLK_UART1_PERIC 209 130 #define CLK_SCLK_UART0_PERIC 210 131 #define CLK_SCLK_SPI2_PERIC 211 132 #define CLK_SCLK_SPI1_PERIC 212 133 #define CLK_SCLK_SPI0_PERIC 213 134 #define CLK_SCLK_SPDIF_PERIC 214 135 #define CLK_SCLK_I2S1_PERIC 215 136 #define CLK_SCLK_PCM1_PERIC 216 137 #define CLK_SCLK_SLIMBUS 217 138 #define CLK_SCLK_AUDIO1 218 139 #define CLK_SCLK_AUDIO0 219 140 #define CLK_ACLK_G2D_266 220 141 #define CLK_ACLK_G2D_400 221 142 #define CLK_ACLK_G3D_400 222 143 #define CLK_ACLK_IMEM_SSX_266 223 144 #define CLK_ACLK_BUS0_400 224 145 #define CLK_ACLK_BUS1_400 225 146 #define CLK_ACLK_IMEM_200 226 147 #define CLK_ACLK_IMEM_266 227 148 #define CLK_SCLK_PCIE_100_FSYS 228 149 #define CLK_SCLK_UFSUNIPRO_FSYS 229 150 #define CLK_SCLK_USBHOST30_FSYS 230 151 #define CLK_SCLK_USBDRD30_FSYS 231 152 #define CLK_ACLK_GSCL_111 232 153 #define CLK_ACLK_GSCL_333 233 154 #define CLK_SCLK_JPEG_MSCL 234 155 #define CLK_ACLK_MSCL_400 235 156 157 #define TOP_NR_CLK 236 158 159 /* CMU_CPIF */ 160 #define CLK_FOUT_MPHY_PLL 1 161 162 #define CLK_MOUT_MPHY_PLL 2 163 164 #define CLK_DIV_SCLK_MPHY 10 165 166 #define CLK_SCLK_MPHY_PLL 11 167 #define CLK_SCLK_UFS_MPHY 11 168 169 #define CPIF_NR_CLK 12 170 171 /* CMU_MIF */ 172 #define CLK_FOUT_MEM0_PLL 1 173 #define CLK_FOUT_MEM1_PLL 2 174 #define CLK_FOUT_BUS_PLL 3 175 #define CLK_FOUT_MFC_PLL 4 176 #define CLK_DOUT_MFC_PLL 5 177 #define CLK_DOUT_BUS_PLL 6 178 #define CLK_DOUT_MEM1_PLL 7 179 #define CLK_DOUT_MEM0_PLL 8 180 181 #define CLK_MOUT_MFC_PLL_DIV2 10 182 #define CLK_MOUT_BUS_PLL_DIV2 11 183 #define CLK_MOUT_MEM1_PLL_DIV2 12 184 #define CLK_MOUT_MEM0_PLL_DIV2 13 185 #define CLK_MOUT_MFC_PLL 14 186 #define CLK_MOUT_BUS_PLL 15 187 #define CLK_MOUT_MEM1_PLL 16 188 #define CLK_MOUT_MEM0_PLL 17 189 #define CLK_MOUT_CLK2X_PHY_C 18 190 #define CLK_MOUT_CLK2X_PHY_B 19 191 #define CLK_MOUT_CLK2X_PHY_A 20 192 #define CLK_MOUT_CLKM_PHY_C 21 193 #define CLK_MOUT_CLKM_PHY_B 22 194 #define CLK_MOUT_CLKM_PHY_A 23 195 #define CLK_MOUT_ACLK_MIFNM_200 24 196 #define CLK_MOUT_ACLK_MIFNM_400 25 197 #define CLK_MOUT_ACLK_DISP_333_B 26 198 #define CLK_MOUT_ACLK_DISP_333_A 27 199 #define CLK_MOUT_SCLK_DECON_VCLK_C 28 200 #define CLK_MOUT_SCLK_DECON_VCLK_B 29 201 #define CLK_MOUT_SCLK_DECON_VCLK_A 30 202 #define CLK_MOUT_SCLK_DECON_ECLK_C 31 203 #define CLK_MOUT_SCLK_DECON_ECLK_B 32 204 #define CLK_MOUT_SCLK_DECON_ECLK_A 33 205 #define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34 206 #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35 207 #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36 208 #define CLK_MOUT_SCLK_DSD_C 37 209 #define CLK_MOUT_SCLK_DSD_B 38 210 #define CLK_MOUT_SCLK_DSD_A 39 211 #define CLK_MOUT_SCLK_DSIM0_C 40 212 #define CLK_MOUT_SCLK_DSIM0_B 41 213 #define CLK_MOUT_SCLK_DSIM0_A 42 214 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46 215 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47 216 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48 217 #define CLK_MOUT_SCLK_DSIM1_C 49 218 #define CLK_MOUT_SCLK_DSIM1_B 50 219 #define CLK_MOUT_SCLK_DSIM1_A 51 220 221 #define CLK_DIV_SCLK_HPM_MIF 55 222 #define CLK_DIV_ACLK_DREX1 56 223 #define CLK_DIV_ACLK_DREX0 57 224 #define CLK_DIV_CLK2XPHY 58 225 #define CLK_DIV_ACLK_MIF_266 59 226 #define CLK_DIV_ACLK_MIFND_133 60 227 #define CLK_DIV_ACLK_MIF_133 61 228 #define CLK_DIV_ACLK_MIFNM_200 62 229 #define CLK_DIV_ACLK_MIF_200 63 230 #define CLK_DIV_ACLK_MIF_400 64 231 #define CLK_DIV_ACLK_BUS2_400 65 232 #define CLK_DIV_ACLK_DISP_333 66 233 #define CLK_DIV_ACLK_CPIF_200 67 234 #define CLK_DIV_SCLK_DSIM1 68 235 #define CLK_DIV_SCLK_DECON_TV_VCLK 69 236 #define CLK_DIV_SCLK_DSIM0 70 237 #define CLK_DIV_SCLK_DSD 71 238 #define CLK_DIV_SCLK_DECON_TV_ECLK 72 239 #define CLK_DIV_SCLK_DECON_VCLK 73 240 #define CLK_DIV_SCLK_DECON_ECLK 74 241 #define CLK_DIV_MIF_PRE 75 242 243 #define CLK_CLK2X_PHY1 80 244 #define CLK_CLK2X_PHY0 81 245 #define CLK_CLKM_PHY1 82 246 #define CLK_CLKM_PHY0 83 247 #define CLK_RCLK_DREX1 84 248 #define CLK_RCLK_DREX0 85 249 #define CLK_ACLK_DREX1_TZ 86 250 #define CLK_ACLK_DREX0_TZ 87 251 #define CLK_ACLK_DREX1_PEREV 88 252 #define CLK_ACLK_DREX0_PEREV 89 253 #define CLK_ACLK_DREX1_MEMIF 90 254 #define CLK_ACLK_DREX0_MEMIF 91 255 #define CLK_ACLK_DREX1_SCH 92 256 #define CLK_ACLK_DREX0_SCH 93 257 #define CLK_ACLK_DREX1_BUSIF 94 258 #define CLK_ACLK_DREX0_BUSIF 95 259 #define CLK_ACLK_DREX1_BUSIF_RD 96 260 #define CLK_ACLK_DREX0_BUSIF_RD 97 261 #define CLK_ACLK_DREX1 98 262 #define CLK_ACLK_DREX0 99 263 #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100 264 #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101 265 #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102 266 #define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103 267 #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104 268 #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105 269 #define CLK_ACLK_ASYNCAXIS_CP1 106 270 #define CLK_ACLK_ASYNCAXIM_CP1 107 271 #define CLK_ACLK_ASYNCAXIS_CP0 108 272 #define CLK_ACLK_ASYNCAXIM_CP0 109 273 #define CLK_ACLK_ASYNCAXIS_DREX1_3 110 274 #define CLK_ACLK_ASYNCAXIM_DREX1_3 111 275 #define CLK_ACLK_ASYNCAXIS_DREX1_1 112 276 #define CLK_ACLK_ASYNCAXIM_DREX1_1 113 277 #define CLK_ACLK_ASYNCAXIS_DREX1_0 114 278 #define CLK_ACLK_ASYNCAXIM_DREX1_0 115 279 #define CLK_ACLK_ASYNCAXIS_DREX0_3 116 280 #define CLK_ACLK_ASYNCAXIM_DREX0_3 117 281 #define CLK_ACLK_ASYNCAXIS_DREX0_1 118 282 #define CLK_ACLK_ASYNCAXIM_DREX0_1 119 283 #define CLK_ACLK_ASYNCAXIS_DREX0_0 120 284 #define CLK_ACLK_ASYNCAXIM_DREX0_0 121 285 #define CLK_ACLK_AHB2APB_MIF2P 122 286 #define CLK_ACLK_AHB2APB_MIF1P 123 287 #define CLK_ACLK_AHB2APB_MIF0P 124 288 #define CLK_ACLK_IXIU_CCI 125 289 #define CLK_ACLK_XIU_MIFSFRX 126 290 #define CLK_ACLK_MIFNP_133 127 291 #define CLK_ACLK_MIFNM_200 128 292 #define CLK_ACLK_MIFND_133 129 293 #define CLK_ACLK_MIFND_400 130 294 #define CLK_ACLK_CCI 131 295 #define CLK_ACLK_MIFND_266 132 296 #define CLK_ACLK_PPMU_DREX1S3 133 297 #define CLK_ACLK_PPMU_DREX1S1 134 298 #define CLK_ACLK_PPMU_DREX1S0 135 299 #define CLK_ACLK_PPMU_DREX0S3 136 300 #define CLK_ACLK_PPMU_DREX0S1 137 301 #define CLK_ACLK_PPMU_DREX0S0 138 302 #define CLK_ACLK_BTS_APOLLO 139 303 #define CLK_ACLK_BTS_ATLAS 140 304 #define CLK_ACLK_ACE_SEL_APOLL 141 305 #define CLK_ACLK_ACE_SEL_ATLAS 142 306 #define CLK_ACLK_AXIDS_CCI_MIFSFRX 143 307 #define CLK_ACLK_AXIUS_ATLAS_CCI 144 308 #define CLK_ACLK_AXISYNCDNS_CCI 145 309 #define CLK_ACLK_AXISYNCDN_CCI 146 310 #define CLK_ACLK_AXISYNCDN_NOC_D 147 311 #define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148 312 #define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149 313 #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150 314 #define CLK_ACLK_BUS2_400 151 315 #define CLK_ACLK_DISP_333 152 316 #define CLK_ACLK_CPIF_200 153 317 #define CLK_PCLK_PPMU_DREX1S3 154 318 #define CLK_PCLK_PPMU_DREX1S1 155 319 #define CLK_PCLK_PPMU_DREX1S0 156 320 #define CLK_PCLK_PPMU_DREX0S3 157 321 #define CLK_PCLK_PPMU_DREX0S1 158 322 #define CLK_PCLK_PPMU_DREX0S0 159 323 #define CLK_PCLK_BTS_APOLLO 160 324 #define CLK_PCLK_BTS_ATLAS 161 325 #define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162 326 #define CLK_PCLK_ASYNCAXI_CP1 163 327 #define CLK_PCLK_ASYNCAXI_CP0 164 328 #define CLK_PCLK_ASYNCAXI_DREX1_3 165 329 #define CLK_PCLK_ASYNCAXI_DREX1_1 166 330 #define CLK_PCLK_ASYNCAXI_DREX1_0 167 331 #define CLK_PCLK_ASYNCAXI_DREX0_3 168 332 #define CLK_PCLK_ASYNCAXI_DREX0_1 169 333 #define CLK_PCLK_ASYNCAXI_DREX0_0 170 334 #define CLK_PCLK_MIFSRVND_133 171 335 #define CLK_PCLK_PMU_MIF 172 336 #define CLK_PCLK_SYSREG_MIF 173 337 #define CLK_PCLK_GPIO_ALIVE 174 338 #define CLK_PCLK_ABB 175 339 #define CLK_PCLK_PMU_APBIF 176 340 #define CLK_PCLK_DDR_PHY1 177 341 #define CLK_PCLK_DREX1 178 342 #define CLK_PCLK_DDR_PHY0 179 343 #define CLK_PCLK_DREX0 180 344 #define CLK_PCLK_DREX0_TZ 181 345 #define CLK_PCLK_DREX1_TZ 182 346 #define CLK_PCLK_MONOTONIC_CNT 183 347 #define CLK_PCLK_RTC 184 348 #define CLK_SCLK_DSIM1_DISP 185 349 #define CLK_SCLK_DECON_TV_VCLK_DISP 186 350 #define CLK_SCLK_FREQ_DET_BUS_PLL 187 351 #define CLK_SCLK_FREQ_DET_MFC_PLL 188 352 #define CLK_SCLK_FREQ_DET_MEM0_PLL 189 353 #define CLK_SCLK_FREQ_DET_MEM1_PLL 190 354 #define CLK_SCLK_DSIM0_DISP 191 355 #define CLK_SCLK_DSD_DISP 192 356 #define CLK_SCLK_DECON_TV_ECLK_DISP 193 357 #define CLK_SCLK_DECON_VCLK_DISP 194 358 #define CLK_SCLK_DECON_ECLK_DISP 195 359 #define CLK_SCLK_HPM_MIF 196 360 #define CLK_SCLK_MFC_PLL 197 361 #define CLK_SCLK_BUS_PLL 198 362 #define CLK_SCLK_BUS_PLL_APOLLO 199 363 #define CLK_SCLK_BUS_PLL_ATLAS 200 364 #define CLK_SCLK_HDMI_SPDIF_DISP 201 365 366 #define MIF_NR_CLK 202 367 368 /* CMU_PERIC */ 369 #define CLK_PCLK_SPI2 1 370 #define CLK_PCLK_SPI1 2 371 #define CLK_PCLK_SPI0 3 372 #define CLK_PCLK_UART2 4 373 #define CLK_PCLK_UART1 5 374 #define CLK_PCLK_UART0 6 375 #define CLK_PCLK_HSI2C3 7 376 #define CLK_PCLK_HSI2C2 8 377 #define CLK_PCLK_HSI2C1 9 378 #define CLK_PCLK_HSI2C0 10 379 #define CLK_PCLK_I2C7 11 380 #define CLK_PCLK_I2C6 12 381 #define CLK_PCLK_I2C5 13 382 #define CLK_PCLK_I2C4 14 383 #define CLK_PCLK_I2C3 15 384 #define CLK_PCLK_I2C2 16 385 #define CLK_PCLK_I2C1 17 386 #define CLK_PCLK_I2C0 18 387 #define CLK_PCLK_SPI4 19 388 #define CLK_PCLK_SPI3 20 389 #define CLK_PCLK_HSI2C11 21 390 #define CLK_PCLK_HSI2C10 22 391 #define CLK_PCLK_HSI2C9 23 392 #define CLK_PCLK_HSI2C8 24 393 #define CLK_PCLK_HSI2C7 25 394 #define CLK_PCLK_HSI2C6 26 395 #define CLK_PCLK_HSI2C5 27 396 #define CLK_PCLK_HSI2C4 28 397 #define CLK_SCLK_SPI4 29 398 #define CLK_SCLK_SPI3 30 399 #define CLK_SCLK_SPI2 31 400 #define CLK_SCLK_SPI1 32 401 #define CLK_SCLK_SPI0 33 402 #define CLK_SCLK_UART2 34 403 #define CLK_SCLK_UART1 35 404 #define CLK_SCLK_UART0 36 405 #define CLK_ACLK_AHB2APB_PERIC2P 37 406 #define CLK_ACLK_AHB2APB_PERIC1P 38 407 #define CLK_ACLK_AHB2APB_PERIC0P 39 408 #define CLK_ACLK_PERICNP_66 40 409 #define CLK_PCLK_SCI 41 410 #define CLK_PCLK_GPIO_FINGER 42 411 #define CLK_PCLK_GPIO_ESE 43 412 #define CLK_PCLK_PWM 44 413 #define CLK_PCLK_SPDIF 45 414 #define CLK_PCLK_PCM1 46 415 #define CLK_PCLK_I2S1 47 416 #define CLK_PCLK_ADCIF 48 417 #define CLK_PCLK_GPIO_TOUCH 49 418 #define CLK_PCLK_GPIO_NFC 50 419 #define CLK_PCLK_GPIO_PERIC 51 420 #define CLK_PCLK_PMU_PERIC 52 421 #define CLK_PCLK_SYSREG_PERIC 53 422 #define CLK_SCLK_IOCLK_SPI4 54 423 #define CLK_SCLK_IOCLK_SPI3 55 424 #define CLK_SCLK_SCI 56 425 #define CLK_SCLK_SC_IN 57 426 #define CLK_SCLK_PWM 58 427 #define CLK_SCLK_IOCLK_SPI2 59 428 #define CLK_SCLK_IOCLK_SPI1 60 429 #define CLK_SCLK_IOCLK_SPI0 61 430 #define CLK_SCLK_IOCLK_I2S1_BCLK 62 431 #define CLK_SCLK_SPDIF 63 432 #define CLK_SCLK_PCM1 64 433 #define CLK_SCLK_I2S1 65 434 435 #define CLK_DIV_SCLK_SCI 70 436 #define CLK_DIV_SCLK_SC_IN 71 437 438 #define PERIC_NR_CLK 72 439 440 /* CMU_PERIS */ 441 #define CLK_PCLK_HPM_APBIF 1 442 #define CLK_PCLK_TMU1_APBIF 2 443 #define CLK_PCLK_TMU0_APBIF 3 444 #define CLK_PCLK_PMU_PERIS 4 445 #define CLK_PCLK_SYSREG_PERIS 5 446 #define CLK_PCLK_CMU_TOP_APBIF 6 447 #define CLK_PCLK_WDT_APOLLO 7 448 #define CLK_PCLK_WDT_ATLAS 8 449 #define CLK_PCLK_MCT 9 450 #define CLK_PCLK_HDMI_CEC 10 451 #define CLK_ACLK_AHB2APB_PERIS1P 11 452 #define CLK_ACLK_AHB2APB_PERIS0P 12 453 #define CLK_ACLK_PERISNP_66 13 454 #define CLK_PCLK_TZPC12 14 455 #define CLK_PCLK_TZPC11 15 456 #define CLK_PCLK_TZPC10 16 457 #define CLK_PCLK_TZPC9 17 458 #define CLK_PCLK_TZPC8 18 459 #define CLK_PCLK_TZPC7 19 460 #define CLK_PCLK_TZPC6 20 461 #define CLK_PCLK_TZPC5 21 462 #define CLK_PCLK_TZPC4 22 463 #define CLK_PCLK_TZPC3 23 464 #define CLK_PCLK_TZPC2 24 465 #define CLK_PCLK_TZPC1 25 466 #define CLK_PCLK_TZPC0 26 467 #define CLK_PCLK_SECKEY_APBIF 27 468 #define CLK_PCLK_CHIPID_APBIF 28 469 #define CLK_PCLK_TOPRTC 29 470 #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 471 #define CLK_PCLK_ANTIRBK_CNT_APBIF 31 472 #define CLK_PCLK_OTP_CON_APBIF 32 473 #define CLK_SCLK_ASV_TB 33 474 #define CLK_SCLK_TMU1 34 475 #define CLK_SCLK_TMU0 35 476 #define CLK_SCLK_SECKEY 36 477 #define CLK_SCLK_CHIPID 37 478 #define CLK_SCLK_TOPRTC 38 479 #define CLK_SCLK_CUSTOM_EFUSE 39 480 #define CLK_SCLK_ANTIRBK_CNT 40 481 #define CLK_SCLK_OTP_CON 41 482 483 #define PERIS_NR_CLK 42 484 485 /* CMU_FSYS */ 486 #define CLK_MOUT_ACLK_FSYS_200_USER 1 487 #define CLK_MOUT_SCLK_MMC2_USER 2 488 #define CLK_MOUT_SCLK_MMC1_USER 3 489 #define CLK_MOUT_SCLK_MMC0_USER 4 490 #define CLK_MOUT_SCLK_UFS_MPHY_USER 5 491 #define CLK_MOUT_SCLK_PCIE_100_USER 6 492 #define CLK_MOUT_SCLK_UFSUNIPRO_USER 7 493 #define CLK_MOUT_SCLK_USBHOST30_USER 8 494 #define CLK_MOUT_SCLK_USBDRD30_USER 9 495 #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10 496 #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11 497 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12 498 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13 499 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14 500 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15 501 #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16 502 #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17 503 #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18 504 #define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19 505 #define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20 506 #define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21 507 #define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22 508 #define CLK_MOUT_SCLK_MPHY 23 509 510 #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25 511 #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26 512 #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27 513 #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28 514 #define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29 515 #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30 516 #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31 517 #define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32 518 #define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33 519 #define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34 520 #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35 521 #define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36 522 #define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37 523 524 #define CLK_ACLK_PCIE 50 525 #define CLK_ACLK_PDMA1 51 526 #define CLK_ACLK_TSI 52 527 #define CLK_ACLK_MMC2 53 528 #define CLK_ACLK_MMC1 54 529 #define CLK_ACLK_MMC0 55 530 #define CLK_ACLK_UFS 56 531 #define CLK_ACLK_USBHOST20 57 532 #define CLK_ACLK_USBHOST30 58 533 #define CLK_ACLK_USBDRD30 59 534 #define CLK_ACLK_PDMA0 60 535 #define CLK_SCLK_MMC2 61 536 #define CLK_SCLK_MMC1 62 537 #define CLK_SCLK_MMC0 63 538 #define CLK_PDMA1 64 539 #define CLK_PDMA0 65 540 #define CLK_ACLK_XIU_FSYSPX 66 541 #define CLK_ACLK_AHB_USBLINKH1 67 542 #define CLK_ACLK_SMMU_PDMA1 68 543 #define CLK_ACLK_BTS_PCIE 69 544 #define CLK_ACLK_AXIUS_PDMA1 70 545 #define CLK_ACLK_SMMU_PDMA0 71 546 #define CLK_ACLK_BTS_UFS 72 547 #define CLK_ACLK_BTS_USBHOST30 73 548 #define CLK_ACLK_BTS_USBDRD30 74 549 #define CLK_ACLK_AXIUS_PDMA0 75 550 #define CLK_ACLK_AXIUS_USBHS 76 551 #define CLK_ACLK_AXIUS_FSYSSX 77 552 #define CLK_ACLK_AHB2APB_FSYSP 78 553 #define CLK_ACLK_AHB2AXI_USBHS 79 554 #define CLK_ACLK_AHB_USBLINKH0 80 555 #define CLK_ACLK_AHB_USBHS 81 556 #define CLK_ACLK_AHB_FSYSH 82 557 #define CLK_ACLK_XIU_FSYSX 83 558 #define CLK_ACLK_XIU_FSYSSX 84 559 #define CLK_ACLK_FSYSNP_200 85 560 #define CLK_ACLK_FSYSND_200 86 561 #define CLK_PCLK_PCIE_CTRL 87 562 #define CLK_PCLK_SMMU_PDMA1 88 563 #define CLK_PCLK_PCIE_PHY 89 564 #define CLK_PCLK_BTS_PCIE 90 565 #define CLK_PCLK_SMMU_PDMA0 91 566 #define CLK_PCLK_BTS_UFS 92 567 #define CLK_PCLK_BTS_USBHOST30 93 568 #define CLK_PCLK_BTS_USBDRD30 94 569 #define CLK_PCLK_GPIO_FSYS 95 570 #define CLK_PCLK_PMU_FSYS 96 571 #define CLK_PCLK_SYSREG_FSYS 97 572 #define CLK_SCLK_PCIE_100 98 573 #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99 574 #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100 575 #define CLK_PHYCLK_UFS_RX1_SYMBOL 101 576 #define CLK_PHYCLK_UFS_RX0_SYMBOL 102 577 #define CLK_PHYCLK_UFS_TX1_SYMBOL 103 578 #define CLK_PHYCLK_UFS_TX0_SYMBOL 104 579 #define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105 580 #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106 581 #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107 582 #define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108 583 #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109 584 #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110 585 #define CLK_SCLK_MPHY 111 586 #define CLK_SCLK_UFSUNIPRO 112 587 #define CLK_SCLK_USBHOST30 113 588 #define CLK_SCLK_USBDRD30 114 589 590 #define FSYS_NR_CLK 115 591 592 /* CMU_G2D */ 593 #define CLK_MUX_ACLK_G2D_266_USER 1 594 #define CLK_MUX_ACLK_G2D_400_USER 2 595 596 #define CLK_DIV_PCLK_G2D 3 597 598 #define CLK_ACLK_SMMU_MDMA1 4 599 #define CLK_ACLK_BTS_MDMA1 5 600 #define CLK_ACLK_BTS_G2D 6 601 #define CLK_ACLK_ALB_G2D 7 602 #define CLK_ACLK_AXIUS_G2DX 8 603 #define CLK_ACLK_ASYNCAXI_SYSX 9 604 #define CLK_ACLK_AHB2APB_G2D1P 10 605 #define CLK_ACLK_AHB2APB_G2D0P 11 606 #define CLK_ACLK_XIU_G2DX 12 607 #define CLK_ACLK_G2DNP_133 13 608 #define CLK_ACLK_G2DND_400 14 609 #define CLK_ACLK_MDMA1 15 610 #define CLK_ACLK_G2D 16 611 #define CLK_ACLK_SMMU_G2D 17 612 #define CLK_PCLK_SMMU_MDMA1 18 613 #define CLK_PCLK_BTS_MDMA1 19 614 #define CLK_PCLK_BTS_G2D 20 615 #define CLK_PCLK_ALB_G2D 21 616 #define CLK_PCLK_ASYNCAXI_SYSX 22 617 #define CLK_PCLK_PMU_G2D 23 618 #define CLK_PCLK_SYSREG_G2D 24 619 #define CLK_PCLK_G2D 25 620 #define CLK_PCLK_SMMU_G2D 26 621 622 #define G2D_NR_CLK 27 623 624 /* CMU_DISP */ 625 #define CLK_FOUT_DISP_PLL 1 626 627 #define CLK_MOUT_DISP_PLL 2 628 #define CLK_MOUT_SCLK_DSIM1_USER 3 629 #define CLK_MOUT_SCLK_DSIM0_USER 4 630 #define CLK_MOUT_SCLK_DSD_USER 5 631 #define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6 632 #define CLK_MOUT_SCLK_DECON_VCLK_USER 7 633 #define CLK_MOUT_SCLK_DECON_ECLK_USER 8 634 #define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9 635 #define CLK_MOUT_ACLK_DISP_333_USER 10 636 #define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11 637 #define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12 638 #define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13 639 #define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14 640 #define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15 641 #define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16 642 #define CLK_MOUT_SCLK_DSIM0 17 643 #define CLK_MOUT_SCLK_DECON_TV_ECLK 18 644 #define CLK_MOUT_SCLK_DECON_VCLK 19 645 #define CLK_MOUT_SCLK_DECON_ECLK 20 646 #define CLK_MOUT_SCLK_DSIM1_B_DISP 21 647 #define CLK_MOUT_SCLK_DSIM1_A_DISP 22 648 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23 649 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24 650 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25 651 652 #define CLK_DIV_SCLK_DSIM1_DISP 30 653 #define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31 654 #define CLK_DIV_SCLK_DSIM0_DISP 32 655 #define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33 656 #define CLK_DIV_SCLK_DECON_VCLK_DISP 34 657 #define CLK_DIV_SCLK_DECON_ECLK_DISP 35 658 #define CLK_DIV_PCLK_DISP 36 659 660 #define CLK_ACLK_DECON_TV 40 661 #define CLK_ACLK_DECON 41 662 #define CLK_ACLK_SMMU_TV1X 42 663 #define CLK_ACLK_SMMU_TV0X 43 664 #define CLK_ACLK_SMMU_DECON1X 44 665 #define CLK_ACLK_SMMU_DECON0X 45 666 #define CLK_ACLK_BTS_DECON_TV_M3 46 667 #define CLK_ACLK_BTS_DECON_TV_M2 47 668 #define CLK_ACLK_BTS_DECON_TV_M1 48 669 #define CLK_ACLK_BTS_DECON_TV_M0 49 670 #define CLK_ACLK_BTS_DECON_NM4 50 671 #define CLK_ACLK_BTS_DECON_NM3 51 672 #define CLK_ACLK_BTS_DECON_NM2 52 673 #define CLK_ACLK_BTS_DECON_NM1 53 674 #define CLK_ACLK_BTS_DECON_NM0 54 675 #define CLK_ACLK_AHB2APB_DISPSFR2P 55 676 #define CLK_ACLK_AHB2APB_DISPSFR1P 56 677 #define CLK_ACLK_AHB2APB_DISPSFR0P 57 678 #define CLK_ACLK_AHB_DISPH 58 679 #define CLK_ACLK_XIU_TV1X 59 680 #define CLK_ACLK_XIU_TV0X 60 681 #define CLK_ACLK_XIU_DECON1X 61 682 #define CLK_ACLK_XIU_DECON0X 62 683 #define CLK_ACLK_XIU_DISP1X 63 684 #define CLK_ACLK_XIU_DISPNP_100 64 685 #define CLK_ACLK_DISP1ND_333 65 686 #define CLK_ACLK_DISP0ND_333 66 687 #define CLK_PCLK_SMMU_TV1X 67 688 #define CLK_PCLK_SMMU_TV0X 68 689 #define CLK_PCLK_SMMU_DECON1X 69 690 #define CLK_PCLK_SMMU_DECON0X 70 691 #define CLK_PCLK_BTS_DECON_TV_M3 71 692 #define CLK_PCLK_BTS_DECON_TV_M2 72 693 #define CLK_PCLK_BTS_DECON_TV_M1 73 694 #define CLK_PCLK_BTS_DECON_TV_M0 74 695 #define CLK_PCLK_BTS_DECONM4 75 696 #define CLK_PCLK_BTS_DECONM3 76 697 #define CLK_PCLK_BTS_DECONM2 77 698 #define CLK_PCLK_BTS_DECONM1 78 699 #define CLK_PCLK_BTS_DECONM0 79 700 #define CLK_PCLK_MIC1 80 701 #define CLK_PCLK_PMU_DISP 81 702 #define CLK_PCLK_SYSREG_DISP 82 703 #define CLK_PCLK_HDMIPHY 83 704 #define CLK_PCLK_HDMI 84 705 #define CLK_PCLK_MIC0 85 706 #define CLK_PCLK_DSIM1 86 707 #define CLK_PCLK_DSIM0 87 708 #define CLK_PCLK_DECON_TV 88 709 #define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89 710 #define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90 711 #define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91 712 #define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92 713 #define CLK_SCLK_DSIM1 93 714 #define CLK_SCLK_DECON_TV_VCLK 94 715 #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95 716 #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96 717 #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97 718 #define CLK_PHYCLK_HDMI_PIXEL 98 719 #define CLK_SCLK_RGB_VCLK_TO_SMIES 99 720 #define CLK_SCLK_FREQ_DET_DISP_PLL 100 721 #define CLK_SCLK_RGB_VCLK_TO_DSIM0 101 722 #define CLK_SCLK_RGB_VCLK_TO_MIC0 102 723 #define CLK_SCLK_DSD 103 724 #define CLK_SCLK_HDMI_SPDIF 104 725 #define CLK_SCLK_DSIM0 105 726 #define CLK_SCLK_DECON_TV_ECLK 106 727 #define CLK_SCLK_DECON_VCLK 107 728 #define CLK_SCLK_DECON_ECLK 108 729 #define CLK_SCLK_RGB_VCLK 109 730 #define CLK_SCLK_RGB_TV_VCLK 110 731 732 #define DISP_NR_CLK 111 733 734 /* CMU_AUD */ 735 #define CLK_MOUT_AUD_PLL_USER 1 736 #define CLK_MOUT_SCLK_AUD_PCM 2 737 #define CLK_MOUT_SCLK_AUD_I2S 3 738 739 #define CLK_DIV_ATCLK_AUD 4 740 #define CLK_DIV_PCLK_DBG_AUD 5 741 #define CLK_DIV_ACLK_AUD 6 742 #define CLK_DIV_AUD_CA5 7 743 #define CLK_DIV_SCLK_AUD_SLIMBUS 8 744 #define CLK_DIV_SCLK_AUD_UART 9 745 #define CLK_DIV_SCLK_AUD_PCM 10 746 #define CLK_DIV_SCLK_AUD_I2S 11 747 748 #define CLK_ACLK_INTR_CTRL 12 749 #define CLK_ACLK_AXIDS2_LPASSP 13 750 #define CLK_ACLK_AXIDS1_LPASSP 14 751 #define CLK_ACLK_AXI2APB1_LPASSP 15 752 #define CLK_ACLK_AXI2APH_LPASSP 16 753 #define CLK_ACLK_SMMU_LPASSX 17 754 #define CLK_ACLK_AXIDS0_LPASSP 18 755 #define CLK_ACLK_AXI2APB0_LPASSP 19 756 #define CLK_ACLK_XIU_LPASSX 20 757 #define CLK_ACLK_AUDNP_133 21 758 #define CLK_ACLK_AUDND_133 22 759 #define CLK_ACLK_SRAMC 23 760 #define CLK_ACLK_DMAC 24 761 #define CLK_PCLK_WDT1 25 762 #define CLK_PCLK_WDT0 26 763 #define CLK_PCLK_SFR1 27 764 #define CLK_PCLK_SMMU_LPASSX 28 765 #define CLK_PCLK_GPIO_AUD 29 766 #define CLK_PCLK_PMU_AUD 30 767 #define CLK_PCLK_SYSREG_AUD 31 768 #define CLK_PCLK_AUD_SLIMBUS 32 769 #define CLK_PCLK_AUD_UART 33 770 #define CLK_PCLK_AUD_PCM 34 771 #define CLK_PCLK_AUD_I2S 35 772 #define CLK_PCLK_TIMER 36 773 #define CLK_PCLK_SFR0_CTRL 37 774 #define CLK_ATCLK_AUD 38 775 #define CLK_PCLK_DBG_AUD 39 776 #define CLK_SCLK_AUD_CA5 40 777 #define CLK_SCLK_JTAG_TCK 41 778 #define CLK_SCLK_SLIMBUS_CLKIN 42 779 #define CLK_SCLK_AUD_SLIMBUS 43 780 #define CLK_SCLK_AUD_UART 44 781 #define CLK_SCLK_AUD_PCM 45 782 #define CLK_SCLK_I2S_BCLK 46 783 #define CLK_SCLK_AUD_I2S 47 784 785 #define AUD_NR_CLK 48 786 787 /* CMU_BUS{0|1|2} */ 788 #define CLK_DIV_PCLK_BUS_133 1 789 790 #define CLK_ACLK_AHB2APB_BUSP 2 791 #define CLK_ACLK_BUSNP_133 3 792 #define CLK_ACLK_BUSND_400 4 793 #define CLK_PCLK_BUSSRVND_133 5 794 #define CLK_PCLK_PMU_BUS 6 795 #define CLK_PCLK_SYSREG_BUS 7 796 797 #define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */ 798 #define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ 799 #define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ 800 801 #define BUSx_NR_CLK 11 802 803 /* CMU_G3D */ 804 #define CLK_FOUT_G3D_PLL 1 805 806 #define CLK_MOUT_ACLK_G3D_400 2 807 #define CLK_MOUT_G3D_PLL 3 808 809 #define CLK_DIV_SCLK_HPM_G3D 4 810 #define CLK_DIV_PCLK_G3D 5 811 #define CLK_DIV_ACLK_G3D 6 812 #define CLK_ACLK_BTS_G3D1 7 813 #define CLK_ACLK_BTS_G3D0 8 814 #define CLK_ACLK_ASYNCAPBS_G3D 9 815 #define CLK_ACLK_ASYNCAPBM_G3D 10 816 #define CLK_ACLK_AHB2APB_G3DP 11 817 #define CLK_ACLK_G3DNP_150 12 818 #define CLK_ACLK_G3DND_600 13 819 #define CLK_ACLK_G3D 14 820 #define CLK_PCLK_BTS_G3D1 15 821 #define CLK_PCLK_BTS_G3D0 16 822 #define CLK_PCLK_PMU_G3D 17 823 #define CLK_PCLK_SYSREG_G3D 18 824 #define CLK_SCLK_HPM_G3D 19 825 826 #define G3D_NR_CLK 20 827 828 /* CMU_GSCL */ 829 #define CLK_MOUT_ACLK_GSCL_111_USER 1 830 #define CLK_MOUT_ACLK_GSCL_333_USER 2 831 832 #define CLK_ACLK_BTS_GSCL2 3 833 #define CLK_ACLK_BTS_GSCL1 4 834 #define CLK_ACLK_BTS_GSCL0 5 835 #define CLK_ACLK_AHB2APB_GSCLP 6 836 #define CLK_ACLK_XIU_GSCLX 7 837 #define CLK_ACLK_GSCLNP_111 8 838 #define CLK_ACLK_GSCLRTND_333 9 839 #define CLK_ACLK_GSCLBEND_333 10 840 #define CLK_ACLK_GSD 11 841 #define CLK_ACLK_GSCL2 12 842 #define CLK_ACLK_GSCL1 13 843 #define CLK_ACLK_GSCL0 14 844 #define CLK_ACLK_SMMU_GSCL0 15 845 #define CLK_ACLK_SMMU_GSCL1 16 846 #define CLK_ACLK_SMMU_GSCL2 17 847 #define CLK_PCLK_BTS_GSCL2 18 848 #define CLK_PCLK_BTS_GSCL1 19 849 #define CLK_PCLK_BTS_GSCL0 20 850 #define CLK_PCLK_PMU_GSCL 21 851 #define CLK_PCLK_SYSREG_GSCL 22 852 #define CLK_PCLK_GSCL2 23 853 #define CLK_PCLK_GSCL1 24 854 #define CLK_PCLK_GSCL0 25 855 #define CLK_PCLK_SMMU_GSCL0 26 856 #define CLK_PCLK_SMMU_GSCL1 27 857 #define CLK_PCLK_SMMU_GSCL2 28 858 859 #define GSCL_NR_CLK 29 860 861 /* CMU_APOLLO */ 862 #define CLK_FOUT_APOLLO_PLL 1 863 864 #define CLK_MOUT_APOLLO_PLL 2 865 #define CLK_MOUT_BUS_PLL_APOLLO_USER 3 866 #define CLK_MOUT_APOLLO 4 867 868 #define CLK_DIV_CNTCLK_APOLLO 5 869 #define CLK_DIV_PCLK_DBG_APOLLO 6 870 #define CLK_DIV_ATCLK_APOLLO 7 871 #define CLK_DIV_PCLK_APOLLO 8 872 #define CLK_DIV_ACLK_APOLLO 9 873 #define CLK_DIV_APOLLO2 10 874 #define CLK_DIV_APOLLO1 11 875 #define CLK_DIV_SCLK_HPM_APOLLO 12 876 #define CLK_DIV_APOLLO_PLL 13 877 878 #define CLK_ACLK_ATBDS_APOLLO_3 14 879 #define CLK_ACLK_ATBDS_APOLLO_2 15 880 #define CLK_ACLK_ATBDS_APOLLO_1 16 881 #define CLK_ACLK_ATBDS_APOLLO_0 17 882 #define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18 883 #define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19 884 #define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20 885 #define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21 886 #define CLK_ACLK_ASYNCACES_APOLLO_CCI 22 887 #define CLK_ACLK_AHB2APB_APOLLOP 23 888 #define CLK_ACLK_APOLLONP_200 24 889 #define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25 890 #define CLK_PCLK_PMU_APOLLO 26 891 #define CLK_PCLK_SYSREG_APOLLO 27 892 #define CLK_CNTCLK_APOLLO 28 893 #define CLK_SCLK_HPM_APOLLO 29 894 #define CLK_SCLK_APOLLO 30 895 896 #define APOLLO_NR_CLK 31 897 898 /* CMU_ATLAS */ 899 #define CLK_FOUT_ATLAS_PLL 1 900 901 #define CLK_MOUT_ATLAS_PLL 2 902 #define CLK_MOUT_BUS_PLL_ATLAS_USER 3 903 #define CLK_MOUT_ATLAS 4 904 905 #define CLK_DIV_CNTCLK_ATLAS 5 906 #define CLK_DIV_PCLK_DBG_ATLAS 6 907 #define CLK_DIV_ATCLK_ATLASO 7 908 #define CLK_DIV_PCLK_ATLAS 8 909 #define CLK_DIV_ACLK_ATLAS 9 910 #define CLK_DIV_ATLAS2 10 911 #define CLK_DIV_ATLAS1 11 912 #define CLK_DIV_SCLK_HPM_ATLAS 12 913 #define CLK_DIV_ATLAS_PLL 13 914 915 #define CLK_ACLK_ATB_AUD_CSSYS 14 916 #define CLK_ACLK_ATB_APOLLO3_CSSYS 15 917 #define CLK_ACLK_ATB_APOLLO2_CSSYS 16 918 #define CLK_ACLK_ATB_APOLLO1_CSSYS 17 919 #define CLK_ACLK_ATB_APOLLO0_CSSYS 18 920 #define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19 921 #define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20 922 #define CLK_ACLK_ASYNCACES_ATLAS_CCI 21 923 #define CLK_ACLK_AHB2APB_ATLASP 22 924 #define CLK_ACLK_ATLASNP_200 23 925 #define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24 926 #define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25 927 #define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26 928 #define CLK_PCLK_PMU_ATLAS 27 929 #define CLK_PCLK_SYSREG_ATLAS 28 930 #define CLK_PCLK_SECJTAG 29 931 #define CLK_CNTCLK_ATLAS 30 932 #define CLK_SCLK_FREQ_DET_ATLAS_PLL 31 933 #define CLK_SCLK_HPM_ATLAS 32 934 #define CLK_TRACECLK 33 935 #define CLK_CTMCLK 34 936 #define CLK_HCLK_CSSYS 35 937 #define CLK_PCLK_DBG_CSSYS 36 938 #define CLK_PCLK_DBG 37 939 #define CLK_ATCLK 38 940 #define CLK_SCLK_ATLAS 39 941 942 #define ATLAS_NR_CLK 40 943 944 /* CMU_MSCL */ 945 #define CLK_MOUT_SCLK_JPEG_USER 1 946 #define CLK_MOUT_ACLK_MSCL_400_USER 2 947 #define CLK_MOUT_SCLK_JPEG 3 948 949 #define CLK_DIV_PCLK_MSCL 4 950 951 #define CLK_ACLK_BTS_JPEG 5 952 #define CLK_ACLK_BTS_M2MSCALER1 6 953 #define CLK_ACLK_BTS_M2MSCALER0 7 954 #define CLK_ACLK_AHB2APB_MSCL0P 8 955 #define CLK_ACLK_XIU_MSCLX 9 956 #define CLK_ACLK_MSCLNP_100 10 957 #define CLK_ACLK_MSCLND_400 11 958 #define CLK_ACLK_JPEG 12 959 #define CLK_ACLK_M2MSCALER1 13 960 #define CLK_ACLK_M2MSCALER0 14 961 #define CLK_ACLK_SMMU_M2MSCALER0 15 962 #define CLK_ACLK_SMMU_M2MSCALER1 16 963 #define CLK_ACLK_SMMU_JPEG 17 964 #define CLK_PCLK_BTS_JPEG 18 965 #define CLK_PCLK_BTS_M2MSCALER1 19 966 #define CLK_PCLK_BTS_M2MSCALER0 20 967 #define CLK_PCLK_PMU_MSCL 21 968 #define CLK_PCLK_SYSREG_MSCL 22 969 #define CLK_PCLK_JPEG 23 970 #define CLK_PCLK_M2MSCALER1 24 971 #define CLK_PCLK_M2MSCALER0 25 972 #define CLK_PCLK_SMMU_M2MSCALER0 26 973 #define CLK_PCLK_SMMU_M2MSCALER1 27 974 #define CLK_PCLK_SMMU_JPEG 28 975 #define CLK_SCLK_JPEG 29 976 977 #define MSCL_NR_CLK 30 978 979 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 980