1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Chanwoo Choi <cw00.choi@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 11 #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 12 13 /* CMU_TOP */ 14 #define CLK_FOUT_ISP_PLL 1 15 #define CLK_FOUT_AUD_PLL 2 16 17 #define CLK_MOUT_AUD_PLL 10 18 #define CLK_MOUT_ISP_PLL 11 19 #define CLK_MOUT_AUD_PLL_USER_T 12 20 #define CLK_MOUT_MPHY_PLL_USER 13 21 #define CLK_MOUT_MFC_PLL_USER 14 22 #define CLK_MOUT_BUS_PLL_USER 15 23 #define CLK_MOUT_ACLK_HEVC_400 16 24 #define CLK_MOUT_ACLK_CAM1_333 17 25 #define CLK_MOUT_ACLK_CAM1_552_B 18 26 #define CLK_MOUT_ACLK_CAM1_552_A 19 27 #define CLK_MOUT_ACLK_ISP_DIS_400 20 28 #define CLK_MOUT_ACLK_ISP_400 21 29 #define CLK_MOUT_ACLK_BUS0_400 22 30 #define CLK_MOUT_ACLK_MSCL_400_B 23 31 #define CLK_MOUT_ACLK_MSCL_400_A 24 32 #define CLK_MOUT_ACLK_GSCL_333 25 33 #define CLK_MOUT_ACLK_G2D_400_B 26 34 #define CLK_MOUT_ACLK_G2D_400_A 27 35 #define CLK_MOUT_SCLK_JPEG_C 28 36 #define CLK_MOUT_SCLK_JPEG_B 29 37 #define CLK_MOUT_SCLK_JPEG_A 30 38 #define CLK_MOUT_SCLK_MMC2_B 31 39 #define CLK_MOUT_SCLK_MMC2_A 32 40 #define CLK_MOUT_SCLK_MMC1_B 33 41 #define CLK_MOUT_SCLK_MMC1_A 34 42 #define CLK_MOUT_SCLK_MMC0_D 35 43 #define CLK_MOUT_SCLK_MMC0_C 36 44 #define CLK_MOUT_SCLK_MMC0_B 37 45 #define CLK_MOUT_SCLK_MMC0_A 38 46 #define CLK_MOUT_SCLK_SPI4 39 47 #define CLK_MOUT_SCLK_SPI3 40 48 #define CLK_MOUT_SCLK_UART2 41 49 #define CLK_MOUT_SCLK_UART1 42 50 #define CLK_MOUT_SCLK_UART0 43 51 #define CLK_MOUT_SCLK_SPI2 44 52 #define CLK_MOUT_SCLK_SPI1 45 53 #define CLK_MOUT_SCLK_SPI0 46 54 #define CLK_MOUT_ACLK_MFC_400_C 47 55 #define CLK_MOUT_ACLK_MFC_400_B 48 56 #define CLK_MOUT_ACLK_MFC_400_A 49 57 #define CLK_MOUT_SCLK_ISP_SENSOR2 50 58 #define CLK_MOUT_SCLK_ISP_SENSOR1 51 59 #define CLK_MOUT_SCLK_ISP_SENSOR0 52 60 #define CLK_MOUT_SCLK_ISP_UART 53 61 #define CLK_MOUT_SCLK_ISP_SPI1 54 62 #define CLK_MOUT_SCLK_ISP_SPI0 55 63 #define CLK_MOUT_SCLK_PCIE_100 56 64 #define CLK_MOUT_SCLK_UFSUNIPRO 57 65 #define CLK_MOUT_SCLK_USBHOST30 58 66 #define CLK_MOUT_SCLK_USBDRD30 59 67 #define CLK_MOUT_SCLK_SLIMBUS 60 68 #define CLK_MOUT_SCLK_SPDIF 61 69 #define CLK_MOUT_SCLK_AUDIO1 62 70 #define CLK_MOUT_SCLK_AUDIO0 63 71 #define CLK_MOUT_SCLK_HDMI_SPDIF 64 72 73 #define CLK_DIV_ACLK_FSYS_200 100 74 #define CLK_DIV_ACLK_IMEM_SSSX_266 101 75 #define CLK_DIV_ACLK_IMEM_200 102 76 #define CLK_DIV_ACLK_IMEM_266 103 77 #define CLK_DIV_ACLK_PERIC_66_B 104 78 #define CLK_DIV_ACLK_PERIC_66_A 105 79 #define CLK_DIV_ACLK_PERIS_66_B 106 80 #define CLK_DIV_ACLK_PERIS_66_A 107 81 #define CLK_DIV_SCLK_MMC1_B 108 82 #define CLK_DIV_SCLK_MMC1_A 109 83 #define CLK_DIV_SCLK_MMC0_B 110 84 #define CLK_DIV_SCLK_MMC0_A 111 85 #define CLK_DIV_SCLK_MMC2_B 112 86 #define CLK_DIV_SCLK_MMC2_A 113 87 #define CLK_DIV_SCLK_SPI1_B 114 88 #define CLK_DIV_SCLK_SPI1_A 115 89 #define CLK_DIV_SCLK_SPI0_B 116 90 #define CLK_DIV_SCLK_SPI0_A 117 91 #define CLK_DIV_SCLK_SPI2_B 118 92 #define CLK_DIV_SCLK_SPI2_A 119 93 #define CLK_DIV_SCLK_UART2 120 94 #define CLK_DIV_SCLK_UART1 121 95 #define CLK_DIV_SCLK_UART0 122 96 #define CLK_DIV_SCLK_SPI4_B 123 97 #define CLK_DIV_SCLK_SPI4_A 124 98 #define CLK_DIV_SCLK_SPI3_B 125 99 #define CLK_DIV_SCLK_SPI3_A 126 100 #define CLK_DIV_SCLK_I2S1 127 101 #define CLK_DIV_SCLK_PCM1 128 102 #define CLK_DIV_SCLK_AUDIO1 129 103 #define CLK_DIV_SCLK_AUDIO0 130 104 #define CLK_DIV_ACLK_GSCL_111 131 105 #define CLK_DIV_ACLK_GSCL_333 132 106 #define CLK_DIV_ACLK_HEVC_400 133 107 #define CLK_DIV_ACLK_MFC_400 134 108 #define CLK_DIV_ACLK_G2D_266 135 109 #define CLK_DIV_ACLK_G2D_400 136 110 #define CLK_DIV_ACLK_G3D_400 137 111 #define CLK_DIV_ACLK_BUS0_400 138 112 #define CLK_DIV_ACLK_BUS1_400 139 113 #define CLK_DIV_SCLK_PCIE_100 140 114 #define CLK_DIV_SCLK_USBHOST30 141 115 #define CLK_DIV_SCLK_UFSUNIPRO 142 116 #define CLK_DIV_SCLK_USBDRD30 143 117 #define CLK_DIV_SCLK_JPEG 144 118 #define CLK_DIV_ACLK_MSCL_400 145 119 120 #define CLK_ACLK_PERIC_66 200 121 #define CLK_ACLK_PERIS_66 201 122 #define CLK_ACLK_FSYS_200 202 123 #define CLK_SCLK_MMC2_FSYS 203 124 #define CLK_SCLK_MMC1_FSYS 204 125 #define CLK_SCLK_MMC0_FSYS 205 126 #define CLK_SCLK_SPI4_PERIC 206 127 #define CLK_SCLK_SPI3_PERIC 207 128 #define CLK_SCLK_UART2_PERIC 208 129 #define CLK_SCLK_UART1_PERIC 209 130 #define CLK_SCLK_UART0_PERIC 210 131 #define CLK_SCLK_SPI2_PERIC 211 132 #define CLK_SCLK_SPI1_PERIC 212 133 #define CLK_SCLK_SPI0_PERIC 213 134 #define CLK_SCLK_SPDIF_PERIC 214 135 #define CLK_SCLK_I2S1_PERIC 215 136 #define CLK_SCLK_PCM1_PERIC 216 137 #define CLK_SCLK_SLIMBUS 217 138 #define CLK_SCLK_AUDIO1 218 139 #define CLK_SCLK_AUDIO0 219 140 #define CLK_ACLK_G2D_266 220 141 #define CLK_ACLK_G2D_400 221 142 #define CLK_ACLK_G3D_400 222 143 #define CLK_ACLK_IMEM_SSX_266 223 144 #define CLK_ACLK_BUS0_400 224 145 #define CLK_ACLK_BUS1_400 225 146 #define CLK_ACLK_IMEM_200 226 147 #define CLK_ACLK_IMEM_266 227 148 #define CLK_SCLK_PCIE_100_FSYS 228 149 #define CLK_SCLK_UFSUNIPRO_FSYS 229 150 #define CLK_SCLK_USBHOST30_FSYS 230 151 #define CLK_SCLK_USBDRD30_FSYS 231 152 #define CLK_ACLK_GSCL_111 232 153 #define CLK_ACLK_GSCL_333 233 154 #define CLK_SCLK_JPEG_MSCL 234 155 #define CLK_ACLK_MSCL_400 235 156 #define CLK_ACLK_MFC_400 236 157 158 #define TOP_NR_CLK 237 159 160 /* CMU_CPIF */ 161 #define CLK_FOUT_MPHY_PLL 1 162 163 #define CLK_MOUT_MPHY_PLL 2 164 165 #define CLK_DIV_SCLK_MPHY 10 166 167 #define CLK_SCLK_MPHY_PLL 11 168 #define CLK_SCLK_UFS_MPHY 11 169 170 #define CPIF_NR_CLK 12 171 172 /* CMU_MIF */ 173 #define CLK_FOUT_MEM0_PLL 1 174 #define CLK_FOUT_MEM1_PLL 2 175 #define CLK_FOUT_BUS_PLL 3 176 #define CLK_FOUT_MFC_PLL 4 177 #define CLK_DOUT_MFC_PLL 5 178 #define CLK_DOUT_BUS_PLL 6 179 #define CLK_DOUT_MEM1_PLL 7 180 #define CLK_DOUT_MEM0_PLL 8 181 182 #define CLK_MOUT_MFC_PLL_DIV2 10 183 #define CLK_MOUT_BUS_PLL_DIV2 11 184 #define CLK_MOUT_MEM1_PLL_DIV2 12 185 #define CLK_MOUT_MEM0_PLL_DIV2 13 186 #define CLK_MOUT_MFC_PLL 14 187 #define CLK_MOUT_BUS_PLL 15 188 #define CLK_MOUT_MEM1_PLL 16 189 #define CLK_MOUT_MEM0_PLL 17 190 #define CLK_MOUT_CLK2X_PHY_C 18 191 #define CLK_MOUT_CLK2X_PHY_B 19 192 #define CLK_MOUT_CLK2X_PHY_A 20 193 #define CLK_MOUT_CLKM_PHY_C 21 194 #define CLK_MOUT_CLKM_PHY_B 22 195 #define CLK_MOUT_CLKM_PHY_A 23 196 #define CLK_MOUT_ACLK_MIFNM_200 24 197 #define CLK_MOUT_ACLK_MIFNM_400 25 198 #define CLK_MOUT_ACLK_DISP_333_B 26 199 #define CLK_MOUT_ACLK_DISP_333_A 27 200 #define CLK_MOUT_SCLK_DECON_VCLK_C 28 201 #define CLK_MOUT_SCLK_DECON_VCLK_B 29 202 #define CLK_MOUT_SCLK_DECON_VCLK_A 30 203 #define CLK_MOUT_SCLK_DECON_ECLK_C 31 204 #define CLK_MOUT_SCLK_DECON_ECLK_B 32 205 #define CLK_MOUT_SCLK_DECON_ECLK_A 33 206 #define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34 207 #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35 208 #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36 209 #define CLK_MOUT_SCLK_DSD_C 37 210 #define CLK_MOUT_SCLK_DSD_B 38 211 #define CLK_MOUT_SCLK_DSD_A 39 212 #define CLK_MOUT_SCLK_DSIM0_C 40 213 #define CLK_MOUT_SCLK_DSIM0_B 41 214 #define CLK_MOUT_SCLK_DSIM0_A 42 215 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46 216 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47 217 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48 218 #define CLK_MOUT_SCLK_DSIM1_C 49 219 #define CLK_MOUT_SCLK_DSIM1_B 50 220 #define CLK_MOUT_SCLK_DSIM1_A 51 221 222 #define CLK_DIV_SCLK_HPM_MIF 55 223 #define CLK_DIV_ACLK_DREX1 56 224 #define CLK_DIV_ACLK_DREX0 57 225 #define CLK_DIV_CLK2XPHY 58 226 #define CLK_DIV_ACLK_MIF_266 59 227 #define CLK_DIV_ACLK_MIFND_133 60 228 #define CLK_DIV_ACLK_MIF_133 61 229 #define CLK_DIV_ACLK_MIFNM_200 62 230 #define CLK_DIV_ACLK_MIF_200 63 231 #define CLK_DIV_ACLK_MIF_400 64 232 #define CLK_DIV_ACLK_BUS2_400 65 233 #define CLK_DIV_ACLK_DISP_333 66 234 #define CLK_DIV_ACLK_CPIF_200 67 235 #define CLK_DIV_SCLK_DSIM1 68 236 #define CLK_DIV_SCLK_DECON_TV_VCLK 69 237 #define CLK_DIV_SCLK_DSIM0 70 238 #define CLK_DIV_SCLK_DSD 71 239 #define CLK_DIV_SCLK_DECON_TV_ECLK 72 240 #define CLK_DIV_SCLK_DECON_VCLK 73 241 #define CLK_DIV_SCLK_DECON_ECLK 74 242 #define CLK_DIV_MIF_PRE 75 243 244 #define CLK_CLK2X_PHY1 80 245 #define CLK_CLK2X_PHY0 81 246 #define CLK_CLKM_PHY1 82 247 #define CLK_CLKM_PHY0 83 248 #define CLK_RCLK_DREX1 84 249 #define CLK_RCLK_DREX0 85 250 #define CLK_ACLK_DREX1_TZ 86 251 #define CLK_ACLK_DREX0_TZ 87 252 #define CLK_ACLK_DREX1_PEREV 88 253 #define CLK_ACLK_DREX0_PEREV 89 254 #define CLK_ACLK_DREX1_MEMIF 90 255 #define CLK_ACLK_DREX0_MEMIF 91 256 #define CLK_ACLK_DREX1_SCH 92 257 #define CLK_ACLK_DREX0_SCH 93 258 #define CLK_ACLK_DREX1_BUSIF 94 259 #define CLK_ACLK_DREX0_BUSIF 95 260 #define CLK_ACLK_DREX1_BUSIF_RD 96 261 #define CLK_ACLK_DREX0_BUSIF_RD 97 262 #define CLK_ACLK_DREX1 98 263 #define CLK_ACLK_DREX0 99 264 #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100 265 #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101 266 #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102 267 #define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103 268 #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104 269 #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105 270 #define CLK_ACLK_ASYNCAXIS_CP1 106 271 #define CLK_ACLK_ASYNCAXIM_CP1 107 272 #define CLK_ACLK_ASYNCAXIS_CP0 108 273 #define CLK_ACLK_ASYNCAXIM_CP0 109 274 #define CLK_ACLK_ASYNCAXIS_DREX1_3 110 275 #define CLK_ACLK_ASYNCAXIM_DREX1_3 111 276 #define CLK_ACLK_ASYNCAXIS_DREX1_1 112 277 #define CLK_ACLK_ASYNCAXIM_DREX1_1 113 278 #define CLK_ACLK_ASYNCAXIS_DREX1_0 114 279 #define CLK_ACLK_ASYNCAXIM_DREX1_0 115 280 #define CLK_ACLK_ASYNCAXIS_DREX0_3 116 281 #define CLK_ACLK_ASYNCAXIM_DREX0_3 117 282 #define CLK_ACLK_ASYNCAXIS_DREX0_1 118 283 #define CLK_ACLK_ASYNCAXIM_DREX0_1 119 284 #define CLK_ACLK_ASYNCAXIS_DREX0_0 120 285 #define CLK_ACLK_ASYNCAXIM_DREX0_0 121 286 #define CLK_ACLK_AHB2APB_MIF2P 122 287 #define CLK_ACLK_AHB2APB_MIF1P 123 288 #define CLK_ACLK_AHB2APB_MIF0P 124 289 #define CLK_ACLK_IXIU_CCI 125 290 #define CLK_ACLK_XIU_MIFSFRX 126 291 #define CLK_ACLK_MIFNP_133 127 292 #define CLK_ACLK_MIFNM_200 128 293 #define CLK_ACLK_MIFND_133 129 294 #define CLK_ACLK_MIFND_400 130 295 #define CLK_ACLK_CCI 131 296 #define CLK_ACLK_MIFND_266 132 297 #define CLK_ACLK_PPMU_DREX1S3 133 298 #define CLK_ACLK_PPMU_DREX1S1 134 299 #define CLK_ACLK_PPMU_DREX1S0 135 300 #define CLK_ACLK_PPMU_DREX0S3 136 301 #define CLK_ACLK_PPMU_DREX0S1 137 302 #define CLK_ACLK_PPMU_DREX0S0 138 303 #define CLK_ACLK_BTS_APOLLO 139 304 #define CLK_ACLK_BTS_ATLAS 140 305 #define CLK_ACLK_ACE_SEL_APOLL 141 306 #define CLK_ACLK_ACE_SEL_ATLAS 142 307 #define CLK_ACLK_AXIDS_CCI_MIFSFRX 143 308 #define CLK_ACLK_AXIUS_ATLAS_CCI 144 309 #define CLK_ACLK_AXISYNCDNS_CCI 145 310 #define CLK_ACLK_AXISYNCDN_CCI 146 311 #define CLK_ACLK_AXISYNCDN_NOC_D 147 312 #define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148 313 #define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149 314 #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150 315 #define CLK_ACLK_BUS2_400 151 316 #define CLK_ACLK_DISP_333 152 317 #define CLK_ACLK_CPIF_200 153 318 #define CLK_PCLK_PPMU_DREX1S3 154 319 #define CLK_PCLK_PPMU_DREX1S1 155 320 #define CLK_PCLK_PPMU_DREX1S0 156 321 #define CLK_PCLK_PPMU_DREX0S3 157 322 #define CLK_PCLK_PPMU_DREX0S1 158 323 #define CLK_PCLK_PPMU_DREX0S0 159 324 #define CLK_PCLK_BTS_APOLLO 160 325 #define CLK_PCLK_BTS_ATLAS 161 326 #define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162 327 #define CLK_PCLK_ASYNCAXI_CP1 163 328 #define CLK_PCLK_ASYNCAXI_CP0 164 329 #define CLK_PCLK_ASYNCAXI_DREX1_3 165 330 #define CLK_PCLK_ASYNCAXI_DREX1_1 166 331 #define CLK_PCLK_ASYNCAXI_DREX1_0 167 332 #define CLK_PCLK_ASYNCAXI_DREX0_3 168 333 #define CLK_PCLK_ASYNCAXI_DREX0_1 169 334 #define CLK_PCLK_ASYNCAXI_DREX0_0 170 335 #define CLK_PCLK_MIFSRVND_133 171 336 #define CLK_PCLK_PMU_MIF 172 337 #define CLK_PCLK_SYSREG_MIF 173 338 #define CLK_PCLK_GPIO_ALIVE 174 339 #define CLK_PCLK_ABB 175 340 #define CLK_PCLK_PMU_APBIF 176 341 #define CLK_PCLK_DDR_PHY1 177 342 #define CLK_PCLK_DREX1 178 343 #define CLK_PCLK_DDR_PHY0 179 344 #define CLK_PCLK_DREX0 180 345 #define CLK_PCLK_DREX0_TZ 181 346 #define CLK_PCLK_DREX1_TZ 182 347 #define CLK_PCLK_MONOTONIC_CNT 183 348 #define CLK_PCLK_RTC 184 349 #define CLK_SCLK_DSIM1_DISP 185 350 #define CLK_SCLK_DECON_TV_VCLK_DISP 186 351 #define CLK_SCLK_FREQ_DET_BUS_PLL 187 352 #define CLK_SCLK_FREQ_DET_MFC_PLL 188 353 #define CLK_SCLK_FREQ_DET_MEM0_PLL 189 354 #define CLK_SCLK_FREQ_DET_MEM1_PLL 190 355 #define CLK_SCLK_DSIM0_DISP 191 356 #define CLK_SCLK_DSD_DISP 192 357 #define CLK_SCLK_DECON_TV_ECLK_DISP 193 358 #define CLK_SCLK_DECON_VCLK_DISP 194 359 #define CLK_SCLK_DECON_ECLK_DISP 195 360 #define CLK_SCLK_HPM_MIF 196 361 #define CLK_SCLK_MFC_PLL 197 362 #define CLK_SCLK_BUS_PLL 198 363 #define CLK_SCLK_BUS_PLL_APOLLO 199 364 #define CLK_SCLK_BUS_PLL_ATLAS 200 365 #define CLK_SCLK_HDMI_SPDIF_DISP 201 366 367 #define MIF_NR_CLK 202 368 369 /* CMU_PERIC */ 370 #define CLK_PCLK_SPI2 1 371 #define CLK_PCLK_SPI1 2 372 #define CLK_PCLK_SPI0 3 373 #define CLK_PCLK_UART2 4 374 #define CLK_PCLK_UART1 5 375 #define CLK_PCLK_UART0 6 376 #define CLK_PCLK_HSI2C3 7 377 #define CLK_PCLK_HSI2C2 8 378 #define CLK_PCLK_HSI2C1 9 379 #define CLK_PCLK_HSI2C0 10 380 #define CLK_PCLK_I2C7 11 381 #define CLK_PCLK_I2C6 12 382 #define CLK_PCLK_I2C5 13 383 #define CLK_PCLK_I2C4 14 384 #define CLK_PCLK_I2C3 15 385 #define CLK_PCLK_I2C2 16 386 #define CLK_PCLK_I2C1 17 387 #define CLK_PCLK_I2C0 18 388 #define CLK_PCLK_SPI4 19 389 #define CLK_PCLK_SPI3 20 390 #define CLK_PCLK_HSI2C11 21 391 #define CLK_PCLK_HSI2C10 22 392 #define CLK_PCLK_HSI2C9 23 393 #define CLK_PCLK_HSI2C8 24 394 #define CLK_PCLK_HSI2C7 25 395 #define CLK_PCLK_HSI2C6 26 396 #define CLK_PCLK_HSI2C5 27 397 #define CLK_PCLK_HSI2C4 28 398 #define CLK_SCLK_SPI4 29 399 #define CLK_SCLK_SPI3 30 400 #define CLK_SCLK_SPI2 31 401 #define CLK_SCLK_SPI1 32 402 #define CLK_SCLK_SPI0 33 403 #define CLK_SCLK_UART2 34 404 #define CLK_SCLK_UART1 35 405 #define CLK_SCLK_UART0 36 406 #define CLK_ACLK_AHB2APB_PERIC2P 37 407 #define CLK_ACLK_AHB2APB_PERIC1P 38 408 #define CLK_ACLK_AHB2APB_PERIC0P 39 409 #define CLK_ACLK_PERICNP_66 40 410 #define CLK_PCLK_SCI 41 411 #define CLK_PCLK_GPIO_FINGER 42 412 #define CLK_PCLK_GPIO_ESE 43 413 #define CLK_PCLK_PWM 44 414 #define CLK_PCLK_SPDIF 45 415 #define CLK_PCLK_PCM1 46 416 #define CLK_PCLK_I2S1 47 417 #define CLK_PCLK_ADCIF 48 418 #define CLK_PCLK_GPIO_TOUCH 49 419 #define CLK_PCLK_GPIO_NFC 50 420 #define CLK_PCLK_GPIO_PERIC 51 421 #define CLK_PCLK_PMU_PERIC 52 422 #define CLK_PCLK_SYSREG_PERIC 53 423 #define CLK_SCLK_IOCLK_SPI4 54 424 #define CLK_SCLK_IOCLK_SPI3 55 425 #define CLK_SCLK_SCI 56 426 #define CLK_SCLK_SC_IN 57 427 #define CLK_SCLK_PWM 58 428 #define CLK_SCLK_IOCLK_SPI2 59 429 #define CLK_SCLK_IOCLK_SPI1 60 430 #define CLK_SCLK_IOCLK_SPI0 61 431 #define CLK_SCLK_IOCLK_I2S1_BCLK 62 432 #define CLK_SCLK_SPDIF 63 433 #define CLK_SCLK_PCM1 64 434 #define CLK_SCLK_I2S1 65 435 436 #define CLK_DIV_SCLK_SCI 70 437 #define CLK_DIV_SCLK_SC_IN 71 438 439 #define PERIC_NR_CLK 72 440 441 /* CMU_PERIS */ 442 #define CLK_PCLK_HPM_APBIF 1 443 #define CLK_PCLK_TMU1_APBIF 2 444 #define CLK_PCLK_TMU0_APBIF 3 445 #define CLK_PCLK_PMU_PERIS 4 446 #define CLK_PCLK_SYSREG_PERIS 5 447 #define CLK_PCLK_CMU_TOP_APBIF 6 448 #define CLK_PCLK_WDT_APOLLO 7 449 #define CLK_PCLK_WDT_ATLAS 8 450 #define CLK_PCLK_MCT 9 451 #define CLK_PCLK_HDMI_CEC 10 452 #define CLK_ACLK_AHB2APB_PERIS1P 11 453 #define CLK_ACLK_AHB2APB_PERIS0P 12 454 #define CLK_ACLK_PERISNP_66 13 455 #define CLK_PCLK_TZPC12 14 456 #define CLK_PCLK_TZPC11 15 457 #define CLK_PCLK_TZPC10 16 458 #define CLK_PCLK_TZPC9 17 459 #define CLK_PCLK_TZPC8 18 460 #define CLK_PCLK_TZPC7 19 461 #define CLK_PCLK_TZPC6 20 462 #define CLK_PCLK_TZPC5 21 463 #define CLK_PCLK_TZPC4 22 464 #define CLK_PCLK_TZPC3 23 465 #define CLK_PCLK_TZPC2 24 466 #define CLK_PCLK_TZPC1 25 467 #define CLK_PCLK_TZPC0 26 468 #define CLK_PCLK_SECKEY_APBIF 27 469 #define CLK_PCLK_CHIPID_APBIF 28 470 #define CLK_PCLK_TOPRTC 29 471 #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 472 #define CLK_PCLK_ANTIRBK_CNT_APBIF 31 473 #define CLK_PCLK_OTP_CON_APBIF 32 474 #define CLK_SCLK_ASV_TB 33 475 #define CLK_SCLK_TMU1 34 476 #define CLK_SCLK_TMU0 35 477 #define CLK_SCLK_SECKEY 36 478 #define CLK_SCLK_CHIPID 37 479 #define CLK_SCLK_TOPRTC 38 480 #define CLK_SCLK_CUSTOM_EFUSE 39 481 #define CLK_SCLK_ANTIRBK_CNT 40 482 #define CLK_SCLK_OTP_CON 41 483 484 #define PERIS_NR_CLK 42 485 486 /* CMU_FSYS */ 487 #define CLK_MOUT_ACLK_FSYS_200_USER 1 488 #define CLK_MOUT_SCLK_MMC2_USER 2 489 #define CLK_MOUT_SCLK_MMC1_USER 3 490 #define CLK_MOUT_SCLK_MMC0_USER 4 491 #define CLK_MOUT_SCLK_UFS_MPHY_USER 5 492 #define CLK_MOUT_SCLK_PCIE_100_USER 6 493 #define CLK_MOUT_SCLK_UFSUNIPRO_USER 7 494 #define CLK_MOUT_SCLK_USBHOST30_USER 8 495 #define CLK_MOUT_SCLK_USBDRD30_USER 9 496 #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10 497 #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11 498 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12 499 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13 500 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14 501 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15 502 #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16 503 #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17 504 #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18 505 #define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19 506 #define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20 507 #define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21 508 #define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22 509 #define CLK_MOUT_SCLK_MPHY 23 510 511 #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25 512 #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26 513 #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27 514 #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28 515 #define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29 516 #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30 517 #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31 518 #define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32 519 #define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33 520 #define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34 521 #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35 522 #define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36 523 #define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37 524 525 #define CLK_ACLK_PCIE 50 526 #define CLK_ACLK_PDMA1 51 527 #define CLK_ACLK_TSI 52 528 #define CLK_ACLK_MMC2 53 529 #define CLK_ACLK_MMC1 54 530 #define CLK_ACLK_MMC0 55 531 #define CLK_ACLK_UFS 56 532 #define CLK_ACLK_USBHOST20 57 533 #define CLK_ACLK_USBHOST30 58 534 #define CLK_ACLK_USBDRD30 59 535 #define CLK_ACLK_PDMA0 60 536 #define CLK_SCLK_MMC2 61 537 #define CLK_SCLK_MMC1 62 538 #define CLK_SCLK_MMC0 63 539 #define CLK_PDMA1 64 540 #define CLK_PDMA0 65 541 #define CLK_ACLK_XIU_FSYSPX 66 542 #define CLK_ACLK_AHB_USBLINKH1 67 543 #define CLK_ACLK_SMMU_PDMA1 68 544 #define CLK_ACLK_BTS_PCIE 69 545 #define CLK_ACLK_AXIUS_PDMA1 70 546 #define CLK_ACLK_SMMU_PDMA0 71 547 #define CLK_ACLK_BTS_UFS 72 548 #define CLK_ACLK_BTS_USBHOST30 73 549 #define CLK_ACLK_BTS_USBDRD30 74 550 #define CLK_ACLK_AXIUS_PDMA0 75 551 #define CLK_ACLK_AXIUS_USBHS 76 552 #define CLK_ACLK_AXIUS_FSYSSX 77 553 #define CLK_ACLK_AHB2APB_FSYSP 78 554 #define CLK_ACLK_AHB2AXI_USBHS 79 555 #define CLK_ACLK_AHB_USBLINKH0 80 556 #define CLK_ACLK_AHB_USBHS 81 557 #define CLK_ACLK_AHB_FSYSH 82 558 #define CLK_ACLK_XIU_FSYSX 83 559 #define CLK_ACLK_XIU_FSYSSX 84 560 #define CLK_ACLK_FSYSNP_200 85 561 #define CLK_ACLK_FSYSND_200 86 562 #define CLK_PCLK_PCIE_CTRL 87 563 #define CLK_PCLK_SMMU_PDMA1 88 564 #define CLK_PCLK_PCIE_PHY 89 565 #define CLK_PCLK_BTS_PCIE 90 566 #define CLK_PCLK_SMMU_PDMA0 91 567 #define CLK_PCLK_BTS_UFS 92 568 #define CLK_PCLK_BTS_USBHOST30 93 569 #define CLK_PCLK_BTS_USBDRD30 94 570 #define CLK_PCLK_GPIO_FSYS 95 571 #define CLK_PCLK_PMU_FSYS 96 572 #define CLK_PCLK_SYSREG_FSYS 97 573 #define CLK_SCLK_PCIE_100 98 574 #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99 575 #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100 576 #define CLK_PHYCLK_UFS_RX1_SYMBOL 101 577 #define CLK_PHYCLK_UFS_RX0_SYMBOL 102 578 #define CLK_PHYCLK_UFS_TX1_SYMBOL 103 579 #define CLK_PHYCLK_UFS_TX0_SYMBOL 104 580 #define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105 581 #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106 582 #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107 583 #define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108 584 #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109 585 #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110 586 #define CLK_SCLK_MPHY 111 587 #define CLK_SCLK_UFSUNIPRO 112 588 #define CLK_SCLK_USBHOST30 113 589 #define CLK_SCLK_USBDRD30 114 590 591 #define FSYS_NR_CLK 115 592 593 /* CMU_G2D */ 594 #define CLK_MUX_ACLK_G2D_266_USER 1 595 #define CLK_MUX_ACLK_G2D_400_USER 2 596 597 #define CLK_DIV_PCLK_G2D 3 598 599 #define CLK_ACLK_SMMU_MDMA1 4 600 #define CLK_ACLK_BTS_MDMA1 5 601 #define CLK_ACLK_BTS_G2D 6 602 #define CLK_ACLK_ALB_G2D 7 603 #define CLK_ACLK_AXIUS_G2DX 8 604 #define CLK_ACLK_ASYNCAXI_SYSX 9 605 #define CLK_ACLK_AHB2APB_G2D1P 10 606 #define CLK_ACLK_AHB2APB_G2D0P 11 607 #define CLK_ACLK_XIU_G2DX 12 608 #define CLK_ACLK_G2DNP_133 13 609 #define CLK_ACLK_G2DND_400 14 610 #define CLK_ACLK_MDMA1 15 611 #define CLK_ACLK_G2D 16 612 #define CLK_ACLK_SMMU_G2D 17 613 #define CLK_PCLK_SMMU_MDMA1 18 614 #define CLK_PCLK_BTS_MDMA1 19 615 #define CLK_PCLK_BTS_G2D 20 616 #define CLK_PCLK_ALB_G2D 21 617 #define CLK_PCLK_ASYNCAXI_SYSX 22 618 #define CLK_PCLK_PMU_G2D 23 619 #define CLK_PCLK_SYSREG_G2D 24 620 #define CLK_PCLK_G2D 25 621 #define CLK_PCLK_SMMU_G2D 26 622 623 #define G2D_NR_CLK 27 624 625 /* CMU_DISP */ 626 #define CLK_FOUT_DISP_PLL 1 627 628 #define CLK_MOUT_DISP_PLL 2 629 #define CLK_MOUT_SCLK_DSIM1_USER 3 630 #define CLK_MOUT_SCLK_DSIM0_USER 4 631 #define CLK_MOUT_SCLK_DSD_USER 5 632 #define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6 633 #define CLK_MOUT_SCLK_DECON_VCLK_USER 7 634 #define CLK_MOUT_SCLK_DECON_ECLK_USER 8 635 #define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9 636 #define CLK_MOUT_ACLK_DISP_333_USER 10 637 #define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11 638 #define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12 639 #define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13 640 #define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14 641 #define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15 642 #define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16 643 #define CLK_MOUT_SCLK_DSIM0 17 644 #define CLK_MOUT_SCLK_DECON_TV_ECLK 18 645 #define CLK_MOUT_SCLK_DECON_VCLK 19 646 #define CLK_MOUT_SCLK_DECON_ECLK 20 647 #define CLK_MOUT_SCLK_DSIM1_B_DISP 21 648 #define CLK_MOUT_SCLK_DSIM1_A_DISP 22 649 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23 650 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24 651 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25 652 653 #define CLK_DIV_SCLK_DSIM1_DISP 30 654 #define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31 655 #define CLK_DIV_SCLK_DSIM0_DISP 32 656 #define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33 657 #define CLK_DIV_SCLK_DECON_VCLK_DISP 34 658 #define CLK_DIV_SCLK_DECON_ECLK_DISP 35 659 #define CLK_DIV_PCLK_DISP 36 660 661 #define CLK_ACLK_DECON_TV 40 662 #define CLK_ACLK_DECON 41 663 #define CLK_ACLK_SMMU_TV1X 42 664 #define CLK_ACLK_SMMU_TV0X 43 665 #define CLK_ACLK_SMMU_DECON1X 44 666 #define CLK_ACLK_SMMU_DECON0X 45 667 #define CLK_ACLK_BTS_DECON_TV_M3 46 668 #define CLK_ACLK_BTS_DECON_TV_M2 47 669 #define CLK_ACLK_BTS_DECON_TV_M1 48 670 #define CLK_ACLK_BTS_DECON_TV_M0 49 671 #define CLK_ACLK_BTS_DECON_NM4 50 672 #define CLK_ACLK_BTS_DECON_NM3 51 673 #define CLK_ACLK_BTS_DECON_NM2 52 674 #define CLK_ACLK_BTS_DECON_NM1 53 675 #define CLK_ACLK_BTS_DECON_NM0 54 676 #define CLK_ACLK_AHB2APB_DISPSFR2P 55 677 #define CLK_ACLK_AHB2APB_DISPSFR1P 56 678 #define CLK_ACLK_AHB2APB_DISPSFR0P 57 679 #define CLK_ACLK_AHB_DISPH 58 680 #define CLK_ACLK_XIU_TV1X 59 681 #define CLK_ACLK_XIU_TV0X 60 682 #define CLK_ACLK_XIU_DECON1X 61 683 #define CLK_ACLK_XIU_DECON0X 62 684 #define CLK_ACLK_XIU_DISP1X 63 685 #define CLK_ACLK_XIU_DISPNP_100 64 686 #define CLK_ACLK_DISP1ND_333 65 687 #define CLK_ACLK_DISP0ND_333 66 688 #define CLK_PCLK_SMMU_TV1X 67 689 #define CLK_PCLK_SMMU_TV0X 68 690 #define CLK_PCLK_SMMU_DECON1X 69 691 #define CLK_PCLK_SMMU_DECON0X 70 692 #define CLK_PCLK_BTS_DECON_TV_M3 71 693 #define CLK_PCLK_BTS_DECON_TV_M2 72 694 #define CLK_PCLK_BTS_DECON_TV_M1 73 695 #define CLK_PCLK_BTS_DECON_TV_M0 74 696 #define CLK_PCLK_BTS_DECONM4 75 697 #define CLK_PCLK_BTS_DECONM3 76 698 #define CLK_PCLK_BTS_DECONM2 77 699 #define CLK_PCLK_BTS_DECONM1 78 700 #define CLK_PCLK_BTS_DECONM0 79 701 #define CLK_PCLK_MIC1 80 702 #define CLK_PCLK_PMU_DISP 81 703 #define CLK_PCLK_SYSREG_DISP 82 704 #define CLK_PCLK_HDMIPHY 83 705 #define CLK_PCLK_HDMI 84 706 #define CLK_PCLK_MIC0 85 707 #define CLK_PCLK_DSIM1 86 708 #define CLK_PCLK_DSIM0 87 709 #define CLK_PCLK_DECON_TV 88 710 #define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89 711 #define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90 712 #define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91 713 #define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92 714 #define CLK_SCLK_DSIM1 93 715 #define CLK_SCLK_DECON_TV_VCLK 94 716 #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95 717 #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96 718 #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97 719 #define CLK_PHYCLK_HDMI_PIXEL 98 720 #define CLK_SCLK_RGB_VCLK_TO_SMIES 99 721 #define CLK_SCLK_FREQ_DET_DISP_PLL 100 722 #define CLK_SCLK_RGB_VCLK_TO_DSIM0 101 723 #define CLK_SCLK_RGB_VCLK_TO_MIC0 102 724 #define CLK_SCLK_DSD 103 725 #define CLK_SCLK_HDMI_SPDIF 104 726 #define CLK_SCLK_DSIM0 105 727 #define CLK_SCLK_DECON_TV_ECLK 106 728 #define CLK_SCLK_DECON_VCLK 107 729 #define CLK_SCLK_DECON_ECLK 108 730 #define CLK_SCLK_RGB_VCLK 109 731 #define CLK_SCLK_RGB_TV_VCLK 110 732 733 #define DISP_NR_CLK 111 734 735 /* CMU_AUD */ 736 #define CLK_MOUT_AUD_PLL_USER 1 737 #define CLK_MOUT_SCLK_AUD_PCM 2 738 #define CLK_MOUT_SCLK_AUD_I2S 3 739 740 #define CLK_DIV_ATCLK_AUD 4 741 #define CLK_DIV_PCLK_DBG_AUD 5 742 #define CLK_DIV_ACLK_AUD 6 743 #define CLK_DIV_AUD_CA5 7 744 #define CLK_DIV_SCLK_AUD_SLIMBUS 8 745 #define CLK_DIV_SCLK_AUD_UART 9 746 #define CLK_DIV_SCLK_AUD_PCM 10 747 #define CLK_DIV_SCLK_AUD_I2S 11 748 749 #define CLK_ACLK_INTR_CTRL 12 750 #define CLK_ACLK_AXIDS2_LPASSP 13 751 #define CLK_ACLK_AXIDS1_LPASSP 14 752 #define CLK_ACLK_AXI2APB1_LPASSP 15 753 #define CLK_ACLK_AXI2APH_LPASSP 16 754 #define CLK_ACLK_SMMU_LPASSX 17 755 #define CLK_ACLK_AXIDS0_LPASSP 18 756 #define CLK_ACLK_AXI2APB0_LPASSP 19 757 #define CLK_ACLK_XIU_LPASSX 20 758 #define CLK_ACLK_AUDNP_133 21 759 #define CLK_ACLK_AUDND_133 22 760 #define CLK_ACLK_SRAMC 23 761 #define CLK_ACLK_DMAC 24 762 #define CLK_PCLK_WDT1 25 763 #define CLK_PCLK_WDT0 26 764 #define CLK_PCLK_SFR1 27 765 #define CLK_PCLK_SMMU_LPASSX 28 766 #define CLK_PCLK_GPIO_AUD 29 767 #define CLK_PCLK_PMU_AUD 30 768 #define CLK_PCLK_SYSREG_AUD 31 769 #define CLK_PCLK_AUD_SLIMBUS 32 770 #define CLK_PCLK_AUD_UART 33 771 #define CLK_PCLK_AUD_PCM 34 772 #define CLK_PCLK_AUD_I2S 35 773 #define CLK_PCLK_TIMER 36 774 #define CLK_PCLK_SFR0_CTRL 37 775 #define CLK_ATCLK_AUD 38 776 #define CLK_PCLK_DBG_AUD 39 777 #define CLK_SCLK_AUD_CA5 40 778 #define CLK_SCLK_JTAG_TCK 41 779 #define CLK_SCLK_SLIMBUS_CLKIN 42 780 #define CLK_SCLK_AUD_SLIMBUS 43 781 #define CLK_SCLK_AUD_UART 44 782 #define CLK_SCLK_AUD_PCM 45 783 #define CLK_SCLK_I2S_BCLK 46 784 #define CLK_SCLK_AUD_I2S 47 785 786 #define AUD_NR_CLK 48 787 788 /* CMU_BUS{0|1|2} */ 789 #define CLK_DIV_PCLK_BUS_133 1 790 791 #define CLK_ACLK_AHB2APB_BUSP 2 792 #define CLK_ACLK_BUSNP_133 3 793 #define CLK_ACLK_BUSND_400 4 794 #define CLK_PCLK_BUSSRVND_133 5 795 #define CLK_PCLK_PMU_BUS 6 796 #define CLK_PCLK_SYSREG_BUS 7 797 798 #define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */ 799 #define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ 800 #define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ 801 802 #define BUSx_NR_CLK 11 803 804 /* CMU_G3D */ 805 #define CLK_FOUT_G3D_PLL 1 806 807 #define CLK_MOUT_ACLK_G3D_400 2 808 #define CLK_MOUT_G3D_PLL 3 809 810 #define CLK_DIV_SCLK_HPM_G3D 4 811 #define CLK_DIV_PCLK_G3D 5 812 #define CLK_DIV_ACLK_G3D 6 813 #define CLK_ACLK_BTS_G3D1 7 814 #define CLK_ACLK_BTS_G3D0 8 815 #define CLK_ACLK_ASYNCAPBS_G3D 9 816 #define CLK_ACLK_ASYNCAPBM_G3D 10 817 #define CLK_ACLK_AHB2APB_G3DP 11 818 #define CLK_ACLK_G3DNP_150 12 819 #define CLK_ACLK_G3DND_600 13 820 #define CLK_ACLK_G3D 14 821 #define CLK_PCLK_BTS_G3D1 15 822 #define CLK_PCLK_BTS_G3D0 16 823 #define CLK_PCLK_PMU_G3D 17 824 #define CLK_PCLK_SYSREG_G3D 18 825 #define CLK_SCLK_HPM_G3D 19 826 827 #define G3D_NR_CLK 20 828 829 /* CMU_GSCL */ 830 #define CLK_MOUT_ACLK_GSCL_111_USER 1 831 #define CLK_MOUT_ACLK_GSCL_333_USER 2 832 833 #define CLK_ACLK_BTS_GSCL2 3 834 #define CLK_ACLK_BTS_GSCL1 4 835 #define CLK_ACLK_BTS_GSCL0 5 836 #define CLK_ACLK_AHB2APB_GSCLP 6 837 #define CLK_ACLK_XIU_GSCLX 7 838 #define CLK_ACLK_GSCLNP_111 8 839 #define CLK_ACLK_GSCLRTND_333 9 840 #define CLK_ACLK_GSCLBEND_333 10 841 #define CLK_ACLK_GSD 11 842 #define CLK_ACLK_GSCL2 12 843 #define CLK_ACLK_GSCL1 13 844 #define CLK_ACLK_GSCL0 14 845 #define CLK_ACLK_SMMU_GSCL0 15 846 #define CLK_ACLK_SMMU_GSCL1 16 847 #define CLK_ACLK_SMMU_GSCL2 17 848 #define CLK_PCLK_BTS_GSCL2 18 849 #define CLK_PCLK_BTS_GSCL1 19 850 #define CLK_PCLK_BTS_GSCL0 20 851 #define CLK_PCLK_PMU_GSCL 21 852 #define CLK_PCLK_SYSREG_GSCL 22 853 #define CLK_PCLK_GSCL2 23 854 #define CLK_PCLK_GSCL1 24 855 #define CLK_PCLK_GSCL0 25 856 #define CLK_PCLK_SMMU_GSCL0 26 857 #define CLK_PCLK_SMMU_GSCL1 27 858 #define CLK_PCLK_SMMU_GSCL2 28 859 860 #define GSCL_NR_CLK 29 861 862 /* CMU_APOLLO */ 863 #define CLK_FOUT_APOLLO_PLL 1 864 865 #define CLK_MOUT_APOLLO_PLL 2 866 #define CLK_MOUT_BUS_PLL_APOLLO_USER 3 867 #define CLK_MOUT_APOLLO 4 868 869 #define CLK_DIV_CNTCLK_APOLLO 5 870 #define CLK_DIV_PCLK_DBG_APOLLO 6 871 #define CLK_DIV_ATCLK_APOLLO 7 872 #define CLK_DIV_PCLK_APOLLO 8 873 #define CLK_DIV_ACLK_APOLLO 9 874 #define CLK_DIV_APOLLO2 10 875 #define CLK_DIV_APOLLO1 11 876 #define CLK_DIV_SCLK_HPM_APOLLO 12 877 #define CLK_DIV_APOLLO_PLL 13 878 879 #define CLK_ACLK_ATBDS_APOLLO_3 14 880 #define CLK_ACLK_ATBDS_APOLLO_2 15 881 #define CLK_ACLK_ATBDS_APOLLO_1 16 882 #define CLK_ACLK_ATBDS_APOLLO_0 17 883 #define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18 884 #define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19 885 #define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20 886 #define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21 887 #define CLK_ACLK_ASYNCACES_APOLLO_CCI 22 888 #define CLK_ACLK_AHB2APB_APOLLOP 23 889 #define CLK_ACLK_APOLLONP_200 24 890 #define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25 891 #define CLK_PCLK_PMU_APOLLO 26 892 #define CLK_PCLK_SYSREG_APOLLO 27 893 #define CLK_CNTCLK_APOLLO 28 894 #define CLK_SCLK_HPM_APOLLO 29 895 #define CLK_SCLK_APOLLO 30 896 897 #define APOLLO_NR_CLK 31 898 899 /* CMU_ATLAS */ 900 #define CLK_FOUT_ATLAS_PLL 1 901 902 #define CLK_MOUT_ATLAS_PLL 2 903 #define CLK_MOUT_BUS_PLL_ATLAS_USER 3 904 #define CLK_MOUT_ATLAS 4 905 906 #define CLK_DIV_CNTCLK_ATLAS 5 907 #define CLK_DIV_PCLK_DBG_ATLAS 6 908 #define CLK_DIV_ATCLK_ATLASO 7 909 #define CLK_DIV_PCLK_ATLAS 8 910 #define CLK_DIV_ACLK_ATLAS 9 911 #define CLK_DIV_ATLAS2 10 912 #define CLK_DIV_ATLAS1 11 913 #define CLK_DIV_SCLK_HPM_ATLAS 12 914 #define CLK_DIV_ATLAS_PLL 13 915 916 #define CLK_ACLK_ATB_AUD_CSSYS 14 917 #define CLK_ACLK_ATB_APOLLO3_CSSYS 15 918 #define CLK_ACLK_ATB_APOLLO2_CSSYS 16 919 #define CLK_ACLK_ATB_APOLLO1_CSSYS 17 920 #define CLK_ACLK_ATB_APOLLO0_CSSYS 18 921 #define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19 922 #define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20 923 #define CLK_ACLK_ASYNCACES_ATLAS_CCI 21 924 #define CLK_ACLK_AHB2APB_ATLASP 22 925 #define CLK_ACLK_ATLASNP_200 23 926 #define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24 927 #define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25 928 #define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26 929 #define CLK_PCLK_PMU_ATLAS 27 930 #define CLK_PCLK_SYSREG_ATLAS 28 931 #define CLK_PCLK_SECJTAG 29 932 #define CLK_CNTCLK_ATLAS 30 933 #define CLK_SCLK_FREQ_DET_ATLAS_PLL 31 934 #define CLK_SCLK_HPM_ATLAS 32 935 #define CLK_TRACECLK 33 936 #define CLK_CTMCLK 34 937 #define CLK_HCLK_CSSYS 35 938 #define CLK_PCLK_DBG_CSSYS 36 939 #define CLK_PCLK_DBG 37 940 #define CLK_ATCLK 38 941 #define CLK_SCLK_ATLAS 39 942 943 #define ATLAS_NR_CLK 40 944 945 /* CMU_MSCL */ 946 #define CLK_MOUT_SCLK_JPEG_USER 1 947 #define CLK_MOUT_ACLK_MSCL_400_USER 2 948 #define CLK_MOUT_SCLK_JPEG 3 949 950 #define CLK_DIV_PCLK_MSCL 4 951 952 #define CLK_ACLK_BTS_JPEG 5 953 #define CLK_ACLK_BTS_M2MSCALER1 6 954 #define CLK_ACLK_BTS_M2MSCALER0 7 955 #define CLK_ACLK_AHB2APB_MSCL0P 8 956 #define CLK_ACLK_XIU_MSCLX 9 957 #define CLK_ACLK_MSCLNP_100 10 958 #define CLK_ACLK_MSCLND_400 11 959 #define CLK_ACLK_JPEG 12 960 #define CLK_ACLK_M2MSCALER1 13 961 #define CLK_ACLK_M2MSCALER0 14 962 #define CLK_ACLK_SMMU_M2MSCALER0 15 963 #define CLK_ACLK_SMMU_M2MSCALER1 16 964 #define CLK_ACLK_SMMU_JPEG 17 965 #define CLK_PCLK_BTS_JPEG 18 966 #define CLK_PCLK_BTS_M2MSCALER1 19 967 #define CLK_PCLK_BTS_M2MSCALER0 20 968 #define CLK_PCLK_PMU_MSCL 21 969 #define CLK_PCLK_SYSREG_MSCL 22 970 #define CLK_PCLK_JPEG 23 971 #define CLK_PCLK_M2MSCALER1 24 972 #define CLK_PCLK_M2MSCALER0 25 973 #define CLK_PCLK_SMMU_M2MSCALER0 26 974 #define CLK_PCLK_SMMU_M2MSCALER1 27 975 #define CLK_PCLK_SMMU_JPEG 28 976 #define CLK_SCLK_JPEG 29 977 978 #define MSCL_NR_CLK 30 979 980 /* CMU_MFC */ 981 #define CLK_MOUT_ACLK_MFC_400_USER 1 982 983 #define CLK_DIV_PCLK_MFC 2 984 985 #define CLK_ACLK_BTS_MFC_1 3 986 #define CLK_ACLK_BTS_MFC_0 4 987 #define CLK_ACLK_AHB2APB_MFCP 5 988 #define CLK_ACLK_XIU_MFCX 6 989 #define CLK_ACLK_MFCNP_100 7 990 #define CLK_ACLK_MFCND_400 8 991 #define CLK_ACLK_MFC 9 992 #define CLK_ACLK_SMMU_MFC_1 10 993 #define CLK_ACLK_SMMU_MFC_0 11 994 #define CLK_PCLK_BTS_MFC_1 12 995 #define CLK_PCLK_BTS_MFC_0 13 996 #define CLK_PCLK_PMU_MFC 14 997 #define CLK_PCLK_SYSREG_MFC 15 998 #define CLK_PCLK_MFC 16 999 #define CLK_PCLK_SMMU_MFC_1 17 1000 #define CLK_PCLK_SMMU_MFC_0 18 1001 1002 #define MFC_NR_CLK 19 1003 1004 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 1005