1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Chanwoo Choi <cw00.choi@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 11 #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 12 13 /* CMU_TOP */ 14 #define CLK_FOUT_ISP_PLL 1 15 #define CLK_FOUT_AUD_PLL 2 16 17 #define CLK_MOUT_AUD_PLL 10 18 #define CLK_MOUT_ISP_PLL 11 19 #define CLK_MOUT_AUD_PLL_USER_T 12 20 #define CLK_MOUT_MPHY_PLL_USER 13 21 #define CLK_MOUT_MFC_PLL_USER 14 22 #define CLK_MOUT_BUS_PLL_USER 15 23 #define CLK_MOUT_ACLK_HEVC_400 16 24 #define CLK_MOUT_ACLK_CAM1_333 17 25 #define CLK_MOUT_ACLK_CAM1_552_B 18 26 #define CLK_MOUT_ACLK_CAM1_552_A 19 27 #define CLK_MOUT_ACLK_ISP_DIS_400 20 28 #define CLK_MOUT_ACLK_ISP_400 21 29 #define CLK_MOUT_ACLK_BUS0_400 22 30 #define CLK_MOUT_ACLK_MSCL_400_B 23 31 #define CLK_MOUT_ACLK_MSCL_400_A 24 32 #define CLK_MOUT_ACLK_GSCL_333 25 33 #define CLK_MOUT_ACLK_G2D_400_B 26 34 #define CLK_MOUT_ACLK_G2D_400_A 27 35 #define CLK_MOUT_SCLK_JPEG_C 28 36 #define CLK_MOUT_SCLK_JPEG_B 29 37 #define CLK_MOUT_SCLK_JPEG_A 30 38 #define CLK_MOUT_SCLK_MMC2_B 31 39 #define CLK_MOUT_SCLK_MMC2_A 32 40 #define CLK_MOUT_SCLK_MMC1_B 33 41 #define CLK_MOUT_SCLK_MMC1_A 34 42 #define CLK_MOUT_SCLK_MMC0_D 35 43 #define CLK_MOUT_SCLK_MMC0_C 36 44 #define CLK_MOUT_SCLK_MMC0_B 37 45 #define CLK_MOUT_SCLK_MMC0_A 38 46 #define CLK_MOUT_SCLK_SPI4 39 47 #define CLK_MOUT_SCLK_SPI3 40 48 #define CLK_MOUT_SCLK_UART2 41 49 #define CLK_MOUT_SCLK_UART1 42 50 #define CLK_MOUT_SCLK_UART0 43 51 #define CLK_MOUT_SCLK_SPI2 44 52 #define CLK_MOUT_SCLK_SPI1 45 53 #define CLK_MOUT_SCLK_SPI0 46 54 #define CLK_MOUT_ACLK_MFC_400_C 47 55 #define CLK_MOUT_ACLK_MFC_400_B 48 56 #define CLK_MOUT_ACLK_MFC_400_A 49 57 #define CLK_MOUT_SCLK_ISP_SENSOR2 50 58 #define CLK_MOUT_SCLK_ISP_SENSOR1 51 59 #define CLK_MOUT_SCLK_ISP_SENSOR0 52 60 #define CLK_MOUT_SCLK_ISP_UART 53 61 #define CLK_MOUT_SCLK_ISP_SPI1 54 62 #define CLK_MOUT_SCLK_ISP_SPI0 55 63 #define CLK_MOUT_SCLK_PCIE_100 56 64 #define CLK_MOUT_SCLK_UFSUNIPRO 57 65 #define CLK_MOUT_SCLK_USBHOST30 58 66 #define CLK_MOUT_SCLK_USBDRD30 59 67 #define CLK_MOUT_SCLK_SLIMBUS 60 68 #define CLK_MOUT_SCLK_SPDIF 61 69 #define CLK_MOUT_SCLK_AUDIO1 62 70 #define CLK_MOUT_SCLK_AUDIO0 63 71 #define CLK_MOUT_SCLK_HDMI_SPDIF 64 72 73 #define CLK_DIV_ACLK_FSYS_200 100 74 #define CLK_DIV_ACLK_IMEM_SSSX_266 101 75 #define CLK_DIV_ACLK_IMEM_200 102 76 #define CLK_DIV_ACLK_IMEM_266 103 77 #define CLK_DIV_ACLK_PERIC_66_B 104 78 #define CLK_DIV_ACLK_PERIC_66_A 105 79 #define CLK_DIV_ACLK_PERIS_66_B 106 80 #define CLK_DIV_ACLK_PERIS_66_A 107 81 #define CLK_DIV_SCLK_MMC1_B 108 82 #define CLK_DIV_SCLK_MMC1_A 109 83 #define CLK_DIV_SCLK_MMC0_B 110 84 #define CLK_DIV_SCLK_MMC0_A 111 85 #define CLK_DIV_SCLK_MMC2_B 112 86 #define CLK_DIV_SCLK_MMC2_A 113 87 #define CLK_DIV_SCLK_SPI1_B 114 88 #define CLK_DIV_SCLK_SPI1_A 115 89 #define CLK_DIV_SCLK_SPI0_B 116 90 #define CLK_DIV_SCLK_SPI0_A 117 91 #define CLK_DIV_SCLK_SPI2_B 118 92 #define CLK_DIV_SCLK_SPI2_A 119 93 #define CLK_DIV_SCLK_UART2 120 94 #define CLK_DIV_SCLK_UART1 121 95 #define CLK_DIV_SCLK_UART0 122 96 #define CLK_DIV_SCLK_SPI4_B 123 97 #define CLK_DIV_SCLK_SPI4_A 124 98 #define CLK_DIV_SCLK_SPI3_B 125 99 #define CLK_DIV_SCLK_SPI3_A 126 100 #define CLK_DIV_SCLK_I2S1 127 101 #define CLK_DIV_SCLK_PCM1 128 102 #define CLK_DIV_SCLK_AUDIO1 129 103 #define CLK_DIV_SCLK_AUDIO0 130 104 #define CLK_DIV_ACLK_GSCL_111 131 105 #define CLK_DIV_ACLK_GSCL_333 132 106 #define CLK_DIV_ACLK_HEVC_400 133 107 #define CLK_DIV_ACLK_MFC_400 134 108 #define CLK_DIV_ACLK_G2D_266 135 109 #define CLK_DIV_ACLK_G2D_400 136 110 #define CLK_DIV_ACLK_G3D_400 137 111 #define CLK_DIV_ACLK_BUS0_400 138 112 #define CLK_DIV_ACLK_BUS1_400 139 113 #define CLK_DIV_SCLK_PCIE_100 140 114 #define CLK_DIV_SCLK_USBHOST30 141 115 #define CLK_DIV_SCLK_UFSUNIPRO 142 116 #define CLK_DIV_SCLK_USBDRD30 143 117 #define CLK_DIV_SCLK_JPEG 144 118 #define CLK_DIV_ACLK_MSCL_400 145 119 #define CLK_DIV_ACLK_ISP_DIS_400 146 120 #define CLK_DIV_ACLK_ISP_400 147 121 122 #define CLK_ACLK_PERIC_66 200 123 #define CLK_ACLK_PERIS_66 201 124 #define CLK_ACLK_FSYS_200 202 125 #define CLK_SCLK_MMC2_FSYS 203 126 #define CLK_SCLK_MMC1_FSYS 204 127 #define CLK_SCLK_MMC0_FSYS 205 128 #define CLK_SCLK_SPI4_PERIC 206 129 #define CLK_SCLK_SPI3_PERIC 207 130 #define CLK_SCLK_UART2_PERIC 208 131 #define CLK_SCLK_UART1_PERIC 209 132 #define CLK_SCLK_UART0_PERIC 210 133 #define CLK_SCLK_SPI2_PERIC 211 134 #define CLK_SCLK_SPI1_PERIC 212 135 #define CLK_SCLK_SPI0_PERIC 213 136 #define CLK_SCLK_SPDIF_PERIC 214 137 #define CLK_SCLK_I2S1_PERIC 215 138 #define CLK_SCLK_PCM1_PERIC 216 139 #define CLK_SCLK_SLIMBUS 217 140 #define CLK_SCLK_AUDIO1 218 141 #define CLK_SCLK_AUDIO0 219 142 #define CLK_ACLK_G2D_266 220 143 #define CLK_ACLK_G2D_400 221 144 #define CLK_ACLK_G3D_400 222 145 #define CLK_ACLK_IMEM_SSX_266 223 146 #define CLK_ACLK_BUS0_400 224 147 #define CLK_ACLK_BUS1_400 225 148 #define CLK_ACLK_IMEM_200 226 149 #define CLK_ACLK_IMEM_266 227 150 #define CLK_SCLK_PCIE_100_FSYS 228 151 #define CLK_SCLK_UFSUNIPRO_FSYS 229 152 #define CLK_SCLK_USBHOST30_FSYS 230 153 #define CLK_SCLK_USBDRD30_FSYS 231 154 #define CLK_ACLK_GSCL_111 232 155 #define CLK_ACLK_GSCL_333 233 156 #define CLK_SCLK_JPEG_MSCL 234 157 #define CLK_ACLK_MSCL_400 235 158 #define CLK_ACLK_MFC_400 236 159 #define CLK_ACLK_HEVC_400 237 160 #define CLK_ACLK_ISP_DIS_400 238 161 #define CLK_ACLK_ISP_400 239 162 163 #define TOP_NR_CLK 240 164 165 /* CMU_CPIF */ 166 #define CLK_FOUT_MPHY_PLL 1 167 168 #define CLK_MOUT_MPHY_PLL 2 169 170 #define CLK_DIV_SCLK_MPHY 10 171 172 #define CLK_SCLK_MPHY_PLL 11 173 #define CLK_SCLK_UFS_MPHY 11 174 175 #define CPIF_NR_CLK 12 176 177 /* CMU_MIF */ 178 #define CLK_FOUT_MEM0_PLL 1 179 #define CLK_FOUT_MEM1_PLL 2 180 #define CLK_FOUT_BUS_PLL 3 181 #define CLK_FOUT_MFC_PLL 4 182 #define CLK_DOUT_MFC_PLL 5 183 #define CLK_DOUT_BUS_PLL 6 184 #define CLK_DOUT_MEM1_PLL 7 185 #define CLK_DOUT_MEM0_PLL 8 186 187 #define CLK_MOUT_MFC_PLL_DIV2 10 188 #define CLK_MOUT_BUS_PLL_DIV2 11 189 #define CLK_MOUT_MEM1_PLL_DIV2 12 190 #define CLK_MOUT_MEM0_PLL_DIV2 13 191 #define CLK_MOUT_MFC_PLL 14 192 #define CLK_MOUT_BUS_PLL 15 193 #define CLK_MOUT_MEM1_PLL 16 194 #define CLK_MOUT_MEM0_PLL 17 195 #define CLK_MOUT_CLK2X_PHY_C 18 196 #define CLK_MOUT_CLK2X_PHY_B 19 197 #define CLK_MOUT_CLK2X_PHY_A 20 198 #define CLK_MOUT_CLKM_PHY_C 21 199 #define CLK_MOUT_CLKM_PHY_B 22 200 #define CLK_MOUT_CLKM_PHY_A 23 201 #define CLK_MOUT_ACLK_MIFNM_200 24 202 #define CLK_MOUT_ACLK_MIFNM_400 25 203 #define CLK_MOUT_ACLK_DISP_333_B 26 204 #define CLK_MOUT_ACLK_DISP_333_A 27 205 #define CLK_MOUT_SCLK_DECON_VCLK_C 28 206 #define CLK_MOUT_SCLK_DECON_VCLK_B 29 207 #define CLK_MOUT_SCLK_DECON_VCLK_A 30 208 #define CLK_MOUT_SCLK_DECON_ECLK_C 31 209 #define CLK_MOUT_SCLK_DECON_ECLK_B 32 210 #define CLK_MOUT_SCLK_DECON_ECLK_A 33 211 #define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34 212 #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35 213 #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36 214 #define CLK_MOUT_SCLK_DSD_C 37 215 #define CLK_MOUT_SCLK_DSD_B 38 216 #define CLK_MOUT_SCLK_DSD_A 39 217 #define CLK_MOUT_SCLK_DSIM0_C 40 218 #define CLK_MOUT_SCLK_DSIM0_B 41 219 #define CLK_MOUT_SCLK_DSIM0_A 42 220 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46 221 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47 222 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48 223 #define CLK_MOUT_SCLK_DSIM1_C 49 224 #define CLK_MOUT_SCLK_DSIM1_B 50 225 #define CLK_MOUT_SCLK_DSIM1_A 51 226 227 #define CLK_DIV_SCLK_HPM_MIF 55 228 #define CLK_DIV_ACLK_DREX1 56 229 #define CLK_DIV_ACLK_DREX0 57 230 #define CLK_DIV_CLK2XPHY 58 231 #define CLK_DIV_ACLK_MIF_266 59 232 #define CLK_DIV_ACLK_MIFND_133 60 233 #define CLK_DIV_ACLK_MIF_133 61 234 #define CLK_DIV_ACLK_MIFNM_200 62 235 #define CLK_DIV_ACLK_MIF_200 63 236 #define CLK_DIV_ACLK_MIF_400 64 237 #define CLK_DIV_ACLK_BUS2_400 65 238 #define CLK_DIV_ACLK_DISP_333 66 239 #define CLK_DIV_ACLK_CPIF_200 67 240 #define CLK_DIV_SCLK_DSIM1 68 241 #define CLK_DIV_SCLK_DECON_TV_VCLK 69 242 #define CLK_DIV_SCLK_DSIM0 70 243 #define CLK_DIV_SCLK_DSD 71 244 #define CLK_DIV_SCLK_DECON_TV_ECLK 72 245 #define CLK_DIV_SCLK_DECON_VCLK 73 246 #define CLK_DIV_SCLK_DECON_ECLK 74 247 #define CLK_DIV_MIF_PRE 75 248 249 #define CLK_CLK2X_PHY1 80 250 #define CLK_CLK2X_PHY0 81 251 #define CLK_CLKM_PHY1 82 252 #define CLK_CLKM_PHY0 83 253 #define CLK_RCLK_DREX1 84 254 #define CLK_RCLK_DREX0 85 255 #define CLK_ACLK_DREX1_TZ 86 256 #define CLK_ACLK_DREX0_TZ 87 257 #define CLK_ACLK_DREX1_PEREV 88 258 #define CLK_ACLK_DREX0_PEREV 89 259 #define CLK_ACLK_DREX1_MEMIF 90 260 #define CLK_ACLK_DREX0_MEMIF 91 261 #define CLK_ACLK_DREX1_SCH 92 262 #define CLK_ACLK_DREX0_SCH 93 263 #define CLK_ACLK_DREX1_BUSIF 94 264 #define CLK_ACLK_DREX0_BUSIF 95 265 #define CLK_ACLK_DREX1_BUSIF_RD 96 266 #define CLK_ACLK_DREX0_BUSIF_RD 97 267 #define CLK_ACLK_DREX1 98 268 #define CLK_ACLK_DREX0 99 269 #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100 270 #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101 271 #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102 272 #define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103 273 #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104 274 #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105 275 #define CLK_ACLK_ASYNCAXIS_CP1 106 276 #define CLK_ACLK_ASYNCAXIM_CP1 107 277 #define CLK_ACLK_ASYNCAXIS_CP0 108 278 #define CLK_ACLK_ASYNCAXIM_CP0 109 279 #define CLK_ACLK_ASYNCAXIS_DREX1_3 110 280 #define CLK_ACLK_ASYNCAXIM_DREX1_3 111 281 #define CLK_ACLK_ASYNCAXIS_DREX1_1 112 282 #define CLK_ACLK_ASYNCAXIM_DREX1_1 113 283 #define CLK_ACLK_ASYNCAXIS_DREX1_0 114 284 #define CLK_ACLK_ASYNCAXIM_DREX1_0 115 285 #define CLK_ACLK_ASYNCAXIS_DREX0_3 116 286 #define CLK_ACLK_ASYNCAXIM_DREX0_3 117 287 #define CLK_ACLK_ASYNCAXIS_DREX0_1 118 288 #define CLK_ACLK_ASYNCAXIM_DREX0_1 119 289 #define CLK_ACLK_ASYNCAXIS_DREX0_0 120 290 #define CLK_ACLK_ASYNCAXIM_DREX0_0 121 291 #define CLK_ACLK_AHB2APB_MIF2P 122 292 #define CLK_ACLK_AHB2APB_MIF1P 123 293 #define CLK_ACLK_AHB2APB_MIF0P 124 294 #define CLK_ACLK_IXIU_CCI 125 295 #define CLK_ACLK_XIU_MIFSFRX 126 296 #define CLK_ACLK_MIFNP_133 127 297 #define CLK_ACLK_MIFNM_200 128 298 #define CLK_ACLK_MIFND_133 129 299 #define CLK_ACLK_MIFND_400 130 300 #define CLK_ACLK_CCI 131 301 #define CLK_ACLK_MIFND_266 132 302 #define CLK_ACLK_PPMU_DREX1S3 133 303 #define CLK_ACLK_PPMU_DREX1S1 134 304 #define CLK_ACLK_PPMU_DREX1S0 135 305 #define CLK_ACLK_PPMU_DREX0S3 136 306 #define CLK_ACLK_PPMU_DREX0S1 137 307 #define CLK_ACLK_PPMU_DREX0S0 138 308 #define CLK_ACLK_BTS_APOLLO 139 309 #define CLK_ACLK_BTS_ATLAS 140 310 #define CLK_ACLK_ACE_SEL_APOLL 141 311 #define CLK_ACLK_ACE_SEL_ATLAS 142 312 #define CLK_ACLK_AXIDS_CCI_MIFSFRX 143 313 #define CLK_ACLK_AXIUS_ATLAS_CCI 144 314 #define CLK_ACLK_AXISYNCDNS_CCI 145 315 #define CLK_ACLK_AXISYNCDN_CCI 146 316 #define CLK_ACLK_AXISYNCDN_NOC_D 147 317 #define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148 318 #define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149 319 #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150 320 #define CLK_ACLK_BUS2_400 151 321 #define CLK_ACLK_DISP_333 152 322 #define CLK_ACLK_CPIF_200 153 323 #define CLK_PCLK_PPMU_DREX1S3 154 324 #define CLK_PCLK_PPMU_DREX1S1 155 325 #define CLK_PCLK_PPMU_DREX1S0 156 326 #define CLK_PCLK_PPMU_DREX0S3 157 327 #define CLK_PCLK_PPMU_DREX0S1 158 328 #define CLK_PCLK_PPMU_DREX0S0 159 329 #define CLK_PCLK_BTS_APOLLO 160 330 #define CLK_PCLK_BTS_ATLAS 161 331 #define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162 332 #define CLK_PCLK_ASYNCAXI_CP1 163 333 #define CLK_PCLK_ASYNCAXI_CP0 164 334 #define CLK_PCLK_ASYNCAXI_DREX1_3 165 335 #define CLK_PCLK_ASYNCAXI_DREX1_1 166 336 #define CLK_PCLK_ASYNCAXI_DREX1_0 167 337 #define CLK_PCLK_ASYNCAXI_DREX0_3 168 338 #define CLK_PCLK_ASYNCAXI_DREX0_1 169 339 #define CLK_PCLK_ASYNCAXI_DREX0_0 170 340 #define CLK_PCLK_MIFSRVND_133 171 341 #define CLK_PCLK_PMU_MIF 172 342 #define CLK_PCLK_SYSREG_MIF 173 343 #define CLK_PCLK_GPIO_ALIVE 174 344 #define CLK_PCLK_ABB 175 345 #define CLK_PCLK_PMU_APBIF 176 346 #define CLK_PCLK_DDR_PHY1 177 347 #define CLK_PCLK_DREX1 178 348 #define CLK_PCLK_DDR_PHY0 179 349 #define CLK_PCLK_DREX0 180 350 #define CLK_PCLK_DREX0_TZ 181 351 #define CLK_PCLK_DREX1_TZ 182 352 #define CLK_PCLK_MONOTONIC_CNT 183 353 #define CLK_PCLK_RTC 184 354 #define CLK_SCLK_DSIM1_DISP 185 355 #define CLK_SCLK_DECON_TV_VCLK_DISP 186 356 #define CLK_SCLK_FREQ_DET_BUS_PLL 187 357 #define CLK_SCLK_FREQ_DET_MFC_PLL 188 358 #define CLK_SCLK_FREQ_DET_MEM0_PLL 189 359 #define CLK_SCLK_FREQ_DET_MEM1_PLL 190 360 #define CLK_SCLK_DSIM0_DISP 191 361 #define CLK_SCLK_DSD_DISP 192 362 #define CLK_SCLK_DECON_TV_ECLK_DISP 193 363 #define CLK_SCLK_DECON_VCLK_DISP 194 364 #define CLK_SCLK_DECON_ECLK_DISP 195 365 #define CLK_SCLK_HPM_MIF 196 366 #define CLK_SCLK_MFC_PLL 197 367 #define CLK_SCLK_BUS_PLL 198 368 #define CLK_SCLK_BUS_PLL_APOLLO 199 369 #define CLK_SCLK_BUS_PLL_ATLAS 200 370 #define CLK_SCLK_HDMI_SPDIF_DISP 201 371 372 #define MIF_NR_CLK 202 373 374 /* CMU_PERIC */ 375 #define CLK_PCLK_SPI2 1 376 #define CLK_PCLK_SPI1 2 377 #define CLK_PCLK_SPI0 3 378 #define CLK_PCLK_UART2 4 379 #define CLK_PCLK_UART1 5 380 #define CLK_PCLK_UART0 6 381 #define CLK_PCLK_HSI2C3 7 382 #define CLK_PCLK_HSI2C2 8 383 #define CLK_PCLK_HSI2C1 9 384 #define CLK_PCLK_HSI2C0 10 385 #define CLK_PCLK_I2C7 11 386 #define CLK_PCLK_I2C6 12 387 #define CLK_PCLK_I2C5 13 388 #define CLK_PCLK_I2C4 14 389 #define CLK_PCLK_I2C3 15 390 #define CLK_PCLK_I2C2 16 391 #define CLK_PCLK_I2C1 17 392 #define CLK_PCLK_I2C0 18 393 #define CLK_PCLK_SPI4 19 394 #define CLK_PCLK_SPI3 20 395 #define CLK_PCLK_HSI2C11 21 396 #define CLK_PCLK_HSI2C10 22 397 #define CLK_PCLK_HSI2C9 23 398 #define CLK_PCLK_HSI2C8 24 399 #define CLK_PCLK_HSI2C7 25 400 #define CLK_PCLK_HSI2C6 26 401 #define CLK_PCLK_HSI2C5 27 402 #define CLK_PCLK_HSI2C4 28 403 #define CLK_SCLK_SPI4 29 404 #define CLK_SCLK_SPI3 30 405 #define CLK_SCLK_SPI2 31 406 #define CLK_SCLK_SPI1 32 407 #define CLK_SCLK_SPI0 33 408 #define CLK_SCLK_UART2 34 409 #define CLK_SCLK_UART1 35 410 #define CLK_SCLK_UART0 36 411 #define CLK_ACLK_AHB2APB_PERIC2P 37 412 #define CLK_ACLK_AHB2APB_PERIC1P 38 413 #define CLK_ACLK_AHB2APB_PERIC0P 39 414 #define CLK_ACLK_PERICNP_66 40 415 #define CLK_PCLK_SCI 41 416 #define CLK_PCLK_GPIO_FINGER 42 417 #define CLK_PCLK_GPIO_ESE 43 418 #define CLK_PCLK_PWM 44 419 #define CLK_PCLK_SPDIF 45 420 #define CLK_PCLK_PCM1 46 421 #define CLK_PCLK_I2S1 47 422 #define CLK_PCLK_ADCIF 48 423 #define CLK_PCLK_GPIO_TOUCH 49 424 #define CLK_PCLK_GPIO_NFC 50 425 #define CLK_PCLK_GPIO_PERIC 51 426 #define CLK_PCLK_PMU_PERIC 52 427 #define CLK_PCLK_SYSREG_PERIC 53 428 #define CLK_SCLK_IOCLK_SPI4 54 429 #define CLK_SCLK_IOCLK_SPI3 55 430 #define CLK_SCLK_SCI 56 431 #define CLK_SCLK_SC_IN 57 432 #define CLK_SCLK_PWM 58 433 #define CLK_SCLK_IOCLK_SPI2 59 434 #define CLK_SCLK_IOCLK_SPI1 60 435 #define CLK_SCLK_IOCLK_SPI0 61 436 #define CLK_SCLK_IOCLK_I2S1_BCLK 62 437 #define CLK_SCLK_SPDIF 63 438 #define CLK_SCLK_PCM1 64 439 #define CLK_SCLK_I2S1 65 440 441 #define CLK_DIV_SCLK_SCI 70 442 #define CLK_DIV_SCLK_SC_IN 71 443 444 #define PERIC_NR_CLK 72 445 446 /* CMU_PERIS */ 447 #define CLK_PCLK_HPM_APBIF 1 448 #define CLK_PCLK_TMU1_APBIF 2 449 #define CLK_PCLK_TMU0_APBIF 3 450 #define CLK_PCLK_PMU_PERIS 4 451 #define CLK_PCLK_SYSREG_PERIS 5 452 #define CLK_PCLK_CMU_TOP_APBIF 6 453 #define CLK_PCLK_WDT_APOLLO 7 454 #define CLK_PCLK_WDT_ATLAS 8 455 #define CLK_PCLK_MCT 9 456 #define CLK_PCLK_HDMI_CEC 10 457 #define CLK_ACLK_AHB2APB_PERIS1P 11 458 #define CLK_ACLK_AHB2APB_PERIS0P 12 459 #define CLK_ACLK_PERISNP_66 13 460 #define CLK_PCLK_TZPC12 14 461 #define CLK_PCLK_TZPC11 15 462 #define CLK_PCLK_TZPC10 16 463 #define CLK_PCLK_TZPC9 17 464 #define CLK_PCLK_TZPC8 18 465 #define CLK_PCLK_TZPC7 19 466 #define CLK_PCLK_TZPC6 20 467 #define CLK_PCLK_TZPC5 21 468 #define CLK_PCLK_TZPC4 22 469 #define CLK_PCLK_TZPC3 23 470 #define CLK_PCLK_TZPC2 24 471 #define CLK_PCLK_TZPC1 25 472 #define CLK_PCLK_TZPC0 26 473 #define CLK_PCLK_SECKEY_APBIF 27 474 #define CLK_PCLK_CHIPID_APBIF 28 475 #define CLK_PCLK_TOPRTC 29 476 #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 477 #define CLK_PCLK_ANTIRBK_CNT_APBIF 31 478 #define CLK_PCLK_OTP_CON_APBIF 32 479 #define CLK_SCLK_ASV_TB 33 480 #define CLK_SCLK_TMU1 34 481 #define CLK_SCLK_TMU0 35 482 #define CLK_SCLK_SECKEY 36 483 #define CLK_SCLK_CHIPID 37 484 #define CLK_SCLK_TOPRTC 38 485 #define CLK_SCLK_CUSTOM_EFUSE 39 486 #define CLK_SCLK_ANTIRBK_CNT 40 487 #define CLK_SCLK_OTP_CON 41 488 489 #define PERIS_NR_CLK 42 490 491 /* CMU_FSYS */ 492 #define CLK_MOUT_ACLK_FSYS_200_USER 1 493 #define CLK_MOUT_SCLK_MMC2_USER 2 494 #define CLK_MOUT_SCLK_MMC1_USER 3 495 #define CLK_MOUT_SCLK_MMC0_USER 4 496 #define CLK_MOUT_SCLK_UFS_MPHY_USER 5 497 #define CLK_MOUT_SCLK_PCIE_100_USER 6 498 #define CLK_MOUT_SCLK_UFSUNIPRO_USER 7 499 #define CLK_MOUT_SCLK_USBHOST30_USER 8 500 #define CLK_MOUT_SCLK_USBDRD30_USER 9 501 #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10 502 #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11 503 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12 504 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13 505 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14 506 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15 507 #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16 508 #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17 509 #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18 510 #define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19 511 #define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20 512 #define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21 513 #define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22 514 #define CLK_MOUT_SCLK_MPHY 23 515 516 #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25 517 #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26 518 #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27 519 #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28 520 #define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29 521 #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30 522 #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31 523 #define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32 524 #define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33 525 #define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34 526 #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35 527 #define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36 528 #define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37 529 530 #define CLK_ACLK_PCIE 50 531 #define CLK_ACLK_PDMA1 51 532 #define CLK_ACLK_TSI 52 533 #define CLK_ACLK_MMC2 53 534 #define CLK_ACLK_MMC1 54 535 #define CLK_ACLK_MMC0 55 536 #define CLK_ACLK_UFS 56 537 #define CLK_ACLK_USBHOST20 57 538 #define CLK_ACLK_USBHOST30 58 539 #define CLK_ACLK_USBDRD30 59 540 #define CLK_ACLK_PDMA0 60 541 #define CLK_SCLK_MMC2 61 542 #define CLK_SCLK_MMC1 62 543 #define CLK_SCLK_MMC0 63 544 #define CLK_PDMA1 64 545 #define CLK_PDMA0 65 546 #define CLK_ACLK_XIU_FSYSPX 66 547 #define CLK_ACLK_AHB_USBLINKH1 67 548 #define CLK_ACLK_SMMU_PDMA1 68 549 #define CLK_ACLK_BTS_PCIE 69 550 #define CLK_ACLK_AXIUS_PDMA1 70 551 #define CLK_ACLK_SMMU_PDMA0 71 552 #define CLK_ACLK_BTS_UFS 72 553 #define CLK_ACLK_BTS_USBHOST30 73 554 #define CLK_ACLK_BTS_USBDRD30 74 555 #define CLK_ACLK_AXIUS_PDMA0 75 556 #define CLK_ACLK_AXIUS_USBHS 76 557 #define CLK_ACLK_AXIUS_FSYSSX 77 558 #define CLK_ACLK_AHB2APB_FSYSP 78 559 #define CLK_ACLK_AHB2AXI_USBHS 79 560 #define CLK_ACLK_AHB_USBLINKH0 80 561 #define CLK_ACLK_AHB_USBHS 81 562 #define CLK_ACLK_AHB_FSYSH 82 563 #define CLK_ACLK_XIU_FSYSX 83 564 #define CLK_ACLK_XIU_FSYSSX 84 565 #define CLK_ACLK_FSYSNP_200 85 566 #define CLK_ACLK_FSYSND_200 86 567 #define CLK_PCLK_PCIE_CTRL 87 568 #define CLK_PCLK_SMMU_PDMA1 88 569 #define CLK_PCLK_PCIE_PHY 89 570 #define CLK_PCLK_BTS_PCIE 90 571 #define CLK_PCLK_SMMU_PDMA0 91 572 #define CLK_PCLK_BTS_UFS 92 573 #define CLK_PCLK_BTS_USBHOST30 93 574 #define CLK_PCLK_BTS_USBDRD30 94 575 #define CLK_PCLK_GPIO_FSYS 95 576 #define CLK_PCLK_PMU_FSYS 96 577 #define CLK_PCLK_SYSREG_FSYS 97 578 #define CLK_SCLK_PCIE_100 98 579 #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99 580 #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100 581 #define CLK_PHYCLK_UFS_RX1_SYMBOL 101 582 #define CLK_PHYCLK_UFS_RX0_SYMBOL 102 583 #define CLK_PHYCLK_UFS_TX1_SYMBOL 103 584 #define CLK_PHYCLK_UFS_TX0_SYMBOL 104 585 #define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105 586 #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106 587 #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107 588 #define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108 589 #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109 590 #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110 591 #define CLK_SCLK_MPHY 111 592 #define CLK_SCLK_UFSUNIPRO 112 593 #define CLK_SCLK_USBHOST30 113 594 #define CLK_SCLK_USBDRD30 114 595 596 #define FSYS_NR_CLK 115 597 598 /* CMU_G2D */ 599 #define CLK_MUX_ACLK_G2D_266_USER 1 600 #define CLK_MUX_ACLK_G2D_400_USER 2 601 602 #define CLK_DIV_PCLK_G2D 3 603 604 #define CLK_ACLK_SMMU_MDMA1 4 605 #define CLK_ACLK_BTS_MDMA1 5 606 #define CLK_ACLK_BTS_G2D 6 607 #define CLK_ACLK_ALB_G2D 7 608 #define CLK_ACLK_AXIUS_G2DX 8 609 #define CLK_ACLK_ASYNCAXI_SYSX 9 610 #define CLK_ACLK_AHB2APB_G2D1P 10 611 #define CLK_ACLK_AHB2APB_G2D0P 11 612 #define CLK_ACLK_XIU_G2DX 12 613 #define CLK_ACLK_G2DNP_133 13 614 #define CLK_ACLK_G2DND_400 14 615 #define CLK_ACLK_MDMA1 15 616 #define CLK_ACLK_G2D 16 617 #define CLK_ACLK_SMMU_G2D 17 618 #define CLK_PCLK_SMMU_MDMA1 18 619 #define CLK_PCLK_BTS_MDMA1 19 620 #define CLK_PCLK_BTS_G2D 20 621 #define CLK_PCLK_ALB_G2D 21 622 #define CLK_PCLK_ASYNCAXI_SYSX 22 623 #define CLK_PCLK_PMU_G2D 23 624 #define CLK_PCLK_SYSREG_G2D 24 625 #define CLK_PCLK_G2D 25 626 #define CLK_PCLK_SMMU_G2D 26 627 628 #define G2D_NR_CLK 27 629 630 /* CMU_DISP */ 631 #define CLK_FOUT_DISP_PLL 1 632 633 #define CLK_MOUT_DISP_PLL 2 634 #define CLK_MOUT_SCLK_DSIM1_USER 3 635 #define CLK_MOUT_SCLK_DSIM0_USER 4 636 #define CLK_MOUT_SCLK_DSD_USER 5 637 #define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6 638 #define CLK_MOUT_SCLK_DECON_VCLK_USER 7 639 #define CLK_MOUT_SCLK_DECON_ECLK_USER 8 640 #define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9 641 #define CLK_MOUT_ACLK_DISP_333_USER 10 642 #define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11 643 #define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12 644 #define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13 645 #define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14 646 #define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15 647 #define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16 648 #define CLK_MOUT_SCLK_DSIM0 17 649 #define CLK_MOUT_SCLK_DECON_TV_ECLK 18 650 #define CLK_MOUT_SCLK_DECON_VCLK 19 651 #define CLK_MOUT_SCLK_DECON_ECLK 20 652 #define CLK_MOUT_SCLK_DSIM1_B_DISP 21 653 #define CLK_MOUT_SCLK_DSIM1_A_DISP 22 654 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23 655 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24 656 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25 657 658 #define CLK_DIV_SCLK_DSIM1_DISP 30 659 #define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31 660 #define CLK_DIV_SCLK_DSIM0_DISP 32 661 #define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33 662 #define CLK_DIV_SCLK_DECON_VCLK_DISP 34 663 #define CLK_DIV_SCLK_DECON_ECLK_DISP 35 664 #define CLK_DIV_PCLK_DISP 36 665 666 #define CLK_ACLK_DECON_TV 40 667 #define CLK_ACLK_DECON 41 668 #define CLK_ACLK_SMMU_TV1X 42 669 #define CLK_ACLK_SMMU_TV0X 43 670 #define CLK_ACLK_SMMU_DECON1X 44 671 #define CLK_ACLK_SMMU_DECON0X 45 672 #define CLK_ACLK_BTS_DECON_TV_M3 46 673 #define CLK_ACLK_BTS_DECON_TV_M2 47 674 #define CLK_ACLK_BTS_DECON_TV_M1 48 675 #define CLK_ACLK_BTS_DECON_TV_M0 49 676 #define CLK_ACLK_BTS_DECON_NM4 50 677 #define CLK_ACLK_BTS_DECON_NM3 51 678 #define CLK_ACLK_BTS_DECON_NM2 52 679 #define CLK_ACLK_BTS_DECON_NM1 53 680 #define CLK_ACLK_BTS_DECON_NM0 54 681 #define CLK_ACLK_AHB2APB_DISPSFR2P 55 682 #define CLK_ACLK_AHB2APB_DISPSFR1P 56 683 #define CLK_ACLK_AHB2APB_DISPSFR0P 57 684 #define CLK_ACLK_AHB_DISPH 58 685 #define CLK_ACLK_XIU_TV1X 59 686 #define CLK_ACLK_XIU_TV0X 60 687 #define CLK_ACLK_XIU_DECON1X 61 688 #define CLK_ACLK_XIU_DECON0X 62 689 #define CLK_ACLK_XIU_DISP1X 63 690 #define CLK_ACLK_XIU_DISPNP_100 64 691 #define CLK_ACLK_DISP1ND_333 65 692 #define CLK_ACLK_DISP0ND_333 66 693 #define CLK_PCLK_SMMU_TV1X 67 694 #define CLK_PCLK_SMMU_TV0X 68 695 #define CLK_PCLK_SMMU_DECON1X 69 696 #define CLK_PCLK_SMMU_DECON0X 70 697 #define CLK_PCLK_BTS_DECON_TV_M3 71 698 #define CLK_PCLK_BTS_DECON_TV_M2 72 699 #define CLK_PCLK_BTS_DECON_TV_M1 73 700 #define CLK_PCLK_BTS_DECON_TV_M0 74 701 #define CLK_PCLK_BTS_DECONM4 75 702 #define CLK_PCLK_BTS_DECONM3 76 703 #define CLK_PCLK_BTS_DECONM2 77 704 #define CLK_PCLK_BTS_DECONM1 78 705 #define CLK_PCLK_BTS_DECONM0 79 706 #define CLK_PCLK_MIC1 80 707 #define CLK_PCLK_PMU_DISP 81 708 #define CLK_PCLK_SYSREG_DISP 82 709 #define CLK_PCLK_HDMIPHY 83 710 #define CLK_PCLK_HDMI 84 711 #define CLK_PCLK_MIC0 85 712 #define CLK_PCLK_DSIM1 86 713 #define CLK_PCLK_DSIM0 87 714 #define CLK_PCLK_DECON_TV 88 715 #define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89 716 #define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90 717 #define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91 718 #define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92 719 #define CLK_SCLK_DSIM1 93 720 #define CLK_SCLK_DECON_TV_VCLK 94 721 #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95 722 #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96 723 #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97 724 #define CLK_PHYCLK_HDMI_PIXEL 98 725 #define CLK_SCLK_RGB_VCLK_TO_SMIES 99 726 #define CLK_SCLK_FREQ_DET_DISP_PLL 100 727 #define CLK_SCLK_RGB_VCLK_TO_DSIM0 101 728 #define CLK_SCLK_RGB_VCLK_TO_MIC0 102 729 #define CLK_SCLK_DSD 103 730 #define CLK_SCLK_HDMI_SPDIF 104 731 #define CLK_SCLK_DSIM0 105 732 #define CLK_SCLK_DECON_TV_ECLK 106 733 #define CLK_SCLK_DECON_VCLK 107 734 #define CLK_SCLK_DECON_ECLK 108 735 #define CLK_SCLK_RGB_VCLK 109 736 #define CLK_SCLK_RGB_TV_VCLK 110 737 738 #define DISP_NR_CLK 111 739 740 /* CMU_AUD */ 741 #define CLK_MOUT_AUD_PLL_USER 1 742 #define CLK_MOUT_SCLK_AUD_PCM 2 743 #define CLK_MOUT_SCLK_AUD_I2S 3 744 745 #define CLK_DIV_ATCLK_AUD 4 746 #define CLK_DIV_PCLK_DBG_AUD 5 747 #define CLK_DIV_ACLK_AUD 6 748 #define CLK_DIV_AUD_CA5 7 749 #define CLK_DIV_SCLK_AUD_SLIMBUS 8 750 #define CLK_DIV_SCLK_AUD_UART 9 751 #define CLK_DIV_SCLK_AUD_PCM 10 752 #define CLK_DIV_SCLK_AUD_I2S 11 753 754 #define CLK_ACLK_INTR_CTRL 12 755 #define CLK_ACLK_AXIDS2_LPASSP 13 756 #define CLK_ACLK_AXIDS1_LPASSP 14 757 #define CLK_ACLK_AXI2APB1_LPASSP 15 758 #define CLK_ACLK_AXI2APH_LPASSP 16 759 #define CLK_ACLK_SMMU_LPASSX 17 760 #define CLK_ACLK_AXIDS0_LPASSP 18 761 #define CLK_ACLK_AXI2APB0_LPASSP 19 762 #define CLK_ACLK_XIU_LPASSX 20 763 #define CLK_ACLK_AUDNP_133 21 764 #define CLK_ACLK_AUDND_133 22 765 #define CLK_ACLK_SRAMC 23 766 #define CLK_ACLK_DMAC 24 767 #define CLK_PCLK_WDT1 25 768 #define CLK_PCLK_WDT0 26 769 #define CLK_PCLK_SFR1 27 770 #define CLK_PCLK_SMMU_LPASSX 28 771 #define CLK_PCLK_GPIO_AUD 29 772 #define CLK_PCLK_PMU_AUD 30 773 #define CLK_PCLK_SYSREG_AUD 31 774 #define CLK_PCLK_AUD_SLIMBUS 32 775 #define CLK_PCLK_AUD_UART 33 776 #define CLK_PCLK_AUD_PCM 34 777 #define CLK_PCLK_AUD_I2S 35 778 #define CLK_PCLK_TIMER 36 779 #define CLK_PCLK_SFR0_CTRL 37 780 #define CLK_ATCLK_AUD 38 781 #define CLK_PCLK_DBG_AUD 39 782 #define CLK_SCLK_AUD_CA5 40 783 #define CLK_SCLK_JTAG_TCK 41 784 #define CLK_SCLK_SLIMBUS_CLKIN 42 785 #define CLK_SCLK_AUD_SLIMBUS 43 786 #define CLK_SCLK_AUD_UART 44 787 #define CLK_SCLK_AUD_PCM 45 788 #define CLK_SCLK_I2S_BCLK 46 789 #define CLK_SCLK_AUD_I2S 47 790 791 #define AUD_NR_CLK 48 792 793 /* CMU_BUS{0|1|2} */ 794 #define CLK_DIV_PCLK_BUS_133 1 795 796 #define CLK_ACLK_AHB2APB_BUSP 2 797 #define CLK_ACLK_BUSNP_133 3 798 #define CLK_ACLK_BUSND_400 4 799 #define CLK_PCLK_BUSSRVND_133 5 800 #define CLK_PCLK_PMU_BUS 6 801 #define CLK_PCLK_SYSREG_BUS 7 802 803 #define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */ 804 #define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ 805 #define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ 806 807 #define BUSx_NR_CLK 11 808 809 /* CMU_G3D */ 810 #define CLK_FOUT_G3D_PLL 1 811 812 #define CLK_MOUT_ACLK_G3D_400 2 813 #define CLK_MOUT_G3D_PLL 3 814 815 #define CLK_DIV_SCLK_HPM_G3D 4 816 #define CLK_DIV_PCLK_G3D 5 817 #define CLK_DIV_ACLK_G3D 6 818 #define CLK_ACLK_BTS_G3D1 7 819 #define CLK_ACLK_BTS_G3D0 8 820 #define CLK_ACLK_ASYNCAPBS_G3D 9 821 #define CLK_ACLK_ASYNCAPBM_G3D 10 822 #define CLK_ACLK_AHB2APB_G3DP 11 823 #define CLK_ACLK_G3DNP_150 12 824 #define CLK_ACLK_G3DND_600 13 825 #define CLK_ACLK_G3D 14 826 #define CLK_PCLK_BTS_G3D1 15 827 #define CLK_PCLK_BTS_G3D0 16 828 #define CLK_PCLK_PMU_G3D 17 829 #define CLK_PCLK_SYSREG_G3D 18 830 #define CLK_SCLK_HPM_G3D 19 831 832 #define G3D_NR_CLK 20 833 834 /* CMU_GSCL */ 835 #define CLK_MOUT_ACLK_GSCL_111_USER 1 836 #define CLK_MOUT_ACLK_GSCL_333_USER 2 837 838 #define CLK_ACLK_BTS_GSCL2 3 839 #define CLK_ACLK_BTS_GSCL1 4 840 #define CLK_ACLK_BTS_GSCL0 5 841 #define CLK_ACLK_AHB2APB_GSCLP 6 842 #define CLK_ACLK_XIU_GSCLX 7 843 #define CLK_ACLK_GSCLNP_111 8 844 #define CLK_ACLK_GSCLRTND_333 9 845 #define CLK_ACLK_GSCLBEND_333 10 846 #define CLK_ACLK_GSD 11 847 #define CLK_ACLK_GSCL2 12 848 #define CLK_ACLK_GSCL1 13 849 #define CLK_ACLK_GSCL0 14 850 #define CLK_ACLK_SMMU_GSCL0 15 851 #define CLK_ACLK_SMMU_GSCL1 16 852 #define CLK_ACLK_SMMU_GSCL2 17 853 #define CLK_PCLK_BTS_GSCL2 18 854 #define CLK_PCLK_BTS_GSCL1 19 855 #define CLK_PCLK_BTS_GSCL0 20 856 #define CLK_PCLK_PMU_GSCL 21 857 #define CLK_PCLK_SYSREG_GSCL 22 858 #define CLK_PCLK_GSCL2 23 859 #define CLK_PCLK_GSCL1 24 860 #define CLK_PCLK_GSCL0 25 861 #define CLK_PCLK_SMMU_GSCL0 26 862 #define CLK_PCLK_SMMU_GSCL1 27 863 #define CLK_PCLK_SMMU_GSCL2 28 864 865 #define GSCL_NR_CLK 29 866 867 /* CMU_APOLLO */ 868 #define CLK_FOUT_APOLLO_PLL 1 869 870 #define CLK_MOUT_APOLLO_PLL 2 871 #define CLK_MOUT_BUS_PLL_APOLLO_USER 3 872 #define CLK_MOUT_APOLLO 4 873 874 #define CLK_DIV_CNTCLK_APOLLO 5 875 #define CLK_DIV_PCLK_DBG_APOLLO 6 876 #define CLK_DIV_ATCLK_APOLLO 7 877 #define CLK_DIV_PCLK_APOLLO 8 878 #define CLK_DIV_ACLK_APOLLO 9 879 #define CLK_DIV_APOLLO2 10 880 #define CLK_DIV_APOLLO1 11 881 #define CLK_DIV_SCLK_HPM_APOLLO 12 882 #define CLK_DIV_APOLLO_PLL 13 883 884 #define CLK_ACLK_ATBDS_APOLLO_3 14 885 #define CLK_ACLK_ATBDS_APOLLO_2 15 886 #define CLK_ACLK_ATBDS_APOLLO_1 16 887 #define CLK_ACLK_ATBDS_APOLLO_0 17 888 #define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18 889 #define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19 890 #define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20 891 #define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21 892 #define CLK_ACLK_ASYNCACES_APOLLO_CCI 22 893 #define CLK_ACLK_AHB2APB_APOLLOP 23 894 #define CLK_ACLK_APOLLONP_200 24 895 #define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25 896 #define CLK_PCLK_PMU_APOLLO 26 897 #define CLK_PCLK_SYSREG_APOLLO 27 898 #define CLK_CNTCLK_APOLLO 28 899 #define CLK_SCLK_HPM_APOLLO 29 900 #define CLK_SCLK_APOLLO 30 901 902 #define APOLLO_NR_CLK 31 903 904 /* CMU_ATLAS */ 905 #define CLK_FOUT_ATLAS_PLL 1 906 907 #define CLK_MOUT_ATLAS_PLL 2 908 #define CLK_MOUT_BUS_PLL_ATLAS_USER 3 909 #define CLK_MOUT_ATLAS 4 910 911 #define CLK_DIV_CNTCLK_ATLAS 5 912 #define CLK_DIV_PCLK_DBG_ATLAS 6 913 #define CLK_DIV_ATCLK_ATLASO 7 914 #define CLK_DIV_PCLK_ATLAS 8 915 #define CLK_DIV_ACLK_ATLAS 9 916 #define CLK_DIV_ATLAS2 10 917 #define CLK_DIV_ATLAS1 11 918 #define CLK_DIV_SCLK_HPM_ATLAS 12 919 #define CLK_DIV_ATLAS_PLL 13 920 921 #define CLK_ACLK_ATB_AUD_CSSYS 14 922 #define CLK_ACLK_ATB_APOLLO3_CSSYS 15 923 #define CLK_ACLK_ATB_APOLLO2_CSSYS 16 924 #define CLK_ACLK_ATB_APOLLO1_CSSYS 17 925 #define CLK_ACLK_ATB_APOLLO0_CSSYS 18 926 #define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19 927 #define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20 928 #define CLK_ACLK_ASYNCACES_ATLAS_CCI 21 929 #define CLK_ACLK_AHB2APB_ATLASP 22 930 #define CLK_ACLK_ATLASNP_200 23 931 #define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24 932 #define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25 933 #define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26 934 #define CLK_PCLK_PMU_ATLAS 27 935 #define CLK_PCLK_SYSREG_ATLAS 28 936 #define CLK_PCLK_SECJTAG 29 937 #define CLK_CNTCLK_ATLAS 30 938 #define CLK_SCLK_FREQ_DET_ATLAS_PLL 31 939 #define CLK_SCLK_HPM_ATLAS 32 940 #define CLK_TRACECLK 33 941 #define CLK_CTMCLK 34 942 #define CLK_HCLK_CSSYS 35 943 #define CLK_PCLK_DBG_CSSYS 36 944 #define CLK_PCLK_DBG 37 945 #define CLK_ATCLK 38 946 #define CLK_SCLK_ATLAS 39 947 948 #define ATLAS_NR_CLK 40 949 950 /* CMU_MSCL */ 951 #define CLK_MOUT_SCLK_JPEG_USER 1 952 #define CLK_MOUT_ACLK_MSCL_400_USER 2 953 #define CLK_MOUT_SCLK_JPEG 3 954 955 #define CLK_DIV_PCLK_MSCL 4 956 957 #define CLK_ACLK_BTS_JPEG 5 958 #define CLK_ACLK_BTS_M2MSCALER1 6 959 #define CLK_ACLK_BTS_M2MSCALER0 7 960 #define CLK_ACLK_AHB2APB_MSCL0P 8 961 #define CLK_ACLK_XIU_MSCLX 9 962 #define CLK_ACLK_MSCLNP_100 10 963 #define CLK_ACLK_MSCLND_400 11 964 #define CLK_ACLK_JPEG 12 965 #define CLK_ACLK_M2MSCALER1 13 966 #define CLK_ACLK_M2MSCALER0 14 967 #define CLK_ACLK_SMMU_M2MSCALER0 15 968 #define CLK_ACLK_SMMU_M2MSCALER1 16 969 #define CLK_ACLK_SMMU_JPEG 17 970 #define CLK_PCLK_BTS_JPEG 18 971 #define CLK_PCLK_BTS_M2MSCALER1 19 972 #define CLK_PCLK_BTS_M2MSCALER0 20 973 #define CLK_PCLK_PMU_MSCL 21 974 #define CLK_PCLK_SYSREG_MSCL 22 975 #define CLK_PCLK_JPEG 23 976 #define CLK_PCLK_M2MSCALER1 24 977 #define CLK_PCLK_M2MSCALER0 25 978 #define CLK_PCLK_SMMU_M2MSCALER0 26 979 #define CLK_PCLK_SMMU_M2MSCALER1 27 980 #define CLK_PCLK_SMMU_JPEG 28 981 #define CLK_SCLK_JPEG 29 982 983 #define MSCL_NR_CLK 30 984 985 /* CMU_MFC */ 986 #define CLK_MOUT_ACLK_MFC_400_USER 1 987 988 #define CLK_DIV_PCLK_MFC 2 989 990 #define CLK_ACLK_BTS_MFC_1 3 991 #define CLK_ACLK_BTS_MFC_0 4 992 #define CLK_ACLK_AHB2APB_MFCP 5 993 #define CLK_ACLK_XIU_MFCX 6 994 #define CLK_ACLK_MFCNP_100 7 995 #define CLK_ACLK_MFCND_400 8 996 #define CLK_ACLK_MFC 9 997 #define CLK_ACLK_SMMU_MFC_1 10 998 #define CLK_ACLK_SMMU_MFC_0 11 999 #define CLK_PCLK_BTS_MFC_1 12 1000 #define CLK_PCLK_BTS_MFC_0 13 1001 #define CLK_PCLK_PMU_MFC 14 1002 #define CLK_PCLK_SYSREG_MFC 15 1003 #define CLK_PCLK_MFC 16 1004 #define CLK_PCLK_SMMU_MFC_1 17 1005 #define CLK_PCLK_SMMU_MFC_0 18 1006 1007 #define MFC_NR_CLK 19 1008 1009 /* CMU_HEVC */ 1010 #define CLK_MOUT_ACLK_HEVC_400_USER 1 1011 1012 #define CLK_DIV_PCLK_HEVC 2 1013 1014 #define CLK_ACLK_BTS_HEVC_1 3 1015 #define CLK_ACLK_BTS_HEVC_0 4 1016 #define CLK_ACLK_AHB2APB_HEVCP 5 1017 #define CLK_ACLK_XIU_HEVCX 6 1018 #define CLK_ACLK_HEVCNP_100 7 1019 #define CLK_ACLK_HEVCND_400 8 1020 #define CLK_ACLK_HEVC 9 1021 #define CLK_ACLK_SMMU_HEVC_1 10 1022 #define CLK_ACLK_SMMU_HEVC_0 11 1023 #define CLK_PCLK_BTS_HEVC_1 12 1024 #define CLK_PCLK_BTS_HEVC_0 13 1025 #define CLK_PCLK_PMU_HEVC 14 1026 #define CLK_PCLK_SYSREG_HEVC 15 1027 #define CLK_PCLK_HEVC 16 1028 #define CLK_PCLK_SMMU_HEVC_1 17 1029 #define CLK_PCLK_SMMU_HEVC_0 18 1030 1031 #define HEVC_NR_CLK 19 1032 1033 /* CMU_ISP */ 1034 #define CLK_MOUT_ACLK_ISP_DIS_400_USER 1 1035 #define CLK_MOUT_ACLK_ISP_400_USER 2 1036 1037 #define CLK_DIV_PCLK_ISP_DIS 3 1038 #define CLK_DIV_PCLK_ISP 4 1039 #define CLK_DIV_ACLK_ISP_D_200 5 1040 #define CLK_DIV_ACLK_ISP_C_200 6 1041 1042 #define CLK_ACLK_ISP_D_GLUE 7 1043 #define CLK_ACLK_SCALERP 8 1044 #define CLK_ACLK_3DNR 9 1045 #define CLK_ACLK_DIS 10 1046 #define CLK_ACLK_SCALERC 11 1047 #define CLK_ACLK_DRC 12 1048 #define CLK_ACLK_ISP 13 1049 #define CLK_ACLK_AXIUS_SCALERP 14 1050 #define CLK_ACLK_AXIUS_SCALERC 15 1051 #define CLK_ACLK_AXIUS_DRC 16 1052 #define CLK_ACLK_ASYNCAHBM_ISP2P 17 1053 #define CLK_ACLK_ASYNCAHBM_ISP1P 18 1054 #define CLK_ACLK_ASYNCAXIS_DIS1 19 1055 #define CLK_ACLK_ASYNCAXIS_DIS0 20 1056 #define CLK_ACLK_ASYNCAXIM_DIS1 21 1057 #define CLK_ACLK_ASYNCAXIM_DIS0 22 1058 #define CLK_ACLK_ASYNCAXIM_ISP2P 23 1059 #define CLK_ACLK_ASYNCAXIM_ISP1P 24 1060 #define CLK_ACLK_AHB2APB_ISP2P 25 1061 #define CLK_ACLK_AHB2APB_ISP1P 26 1062 #define CLK_ACLK_AXI2APB_ISP2P 27 1063 #define CLK_ACLK_AXI2APB_ISP1P 28 1064 #define CLK_ACLK_XIU_ISPEX1 29 1065 #define CLK_ACLK_XIU_ISPEX0 30 1066 #define CLK_ACLK_ISPND_400 31 1067 #define CLK_ACLK_SMMU_SCALERP 32 1068 #define CLK_ACLK_SMMU_3DNR 33 1069 #define CLK_ACLK_SMMU_DIS1 34 1070 #define CLK_ACLK_SMMU_DIS0 35 1071 #define CLK_ACLK_SMMU_SCALERC 36 1072 #define CLK_ACLK_SMMU_DRC 37 1073 #define CLK_ACLK_SMMU_ISP 38 1074 #define CLK_ACLK_BTS_SCALERP 39 1075 #define CLK_ACLK_BTS_3DR 40 1076 #define CLK_ACLK_BTS_DIS1 41 1077 #define CLK_ACLK_BTS_DIS0 42 1078 #define CLK_ACLK_BTS_SCALERC 43 1079 #define CLK_ACLK_BTS_DRC 44 1080 #define CLK_ACLK_BTS_ISP 45 1081 #define CLK_PCLK_SMMU_SCALERP 46 1082 #define CLK_PCLK_SMMU_3DNR 47 1083 #define CLK_PCLK_SMMU_DIS1 48 1084 #define CLK_PCLK_SMMU_DIS0 49 1085 #define CLK_PCLK_SMMU_SCALERC 50 1086 #define CLK_PCLK_SMMU_DRC 51 1087 #define CLK_PCLK_SMMU_ISP 52 1088 #define CLK_PCLK_BTS_SCALERP 53 1089 #define CLK_PCLK_BTS_3DNR 54 1090 #define CLK_PCLK_BTS_DIS1 55 1091 #define CLK_PCLK_BTS_DIS0 56 1092 #define CLK_PCLK_BTS_SCALERC 57 1093 #define CLK_PCLK_BTS_DRC 58 1094 #define CLK_PCLK_BTS_ISP 59 1095 #define CLK_PCLK_ASYNCAXI_DIS1 60 1096 #define CLK_PCLK_ASYNCAXI_DIS0 61 1097 #define CLK_PCLK_PMU_ISP 62 1098 #define CLK_PCLK_SYSREG_ISP 63 1099 #define CLK_PCLK_CMU_ISP_LOCAL 64 1100 #define CLK_PCLK_SCALERP 65 1101 #define CLK_PCLK_3DNR 66 1102 #define CLK_PCLK_DIS_CORE 67 1103 #define CLK_PCLK_DIS 68 1104 #define CLK_PCLK_SCALERC 69 1105 #define CLK_PCLK_DRC 70 1106 #define CLK_PCLK_ISP 71 1107 #define CLK_SCLK_PIXELASYNCS_DIS 72 1108 #define CLK_SCLK_PIXELASYNCM_DIS 73 1109 #define CLK_SCLK_PIXELASYNCS_SCALERP 74 1110 #define CLK_SCLK_PIXELASYNCM_ISPD 75 1111 #define CLK_SCLK_PIXELASYNCS_ISPC 76 1112 #define CLK_SCLK_PIXELASYNCM_ISPC 77 1113 1114 #define ISP_NR_CLK 78 1115 1116 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 1117