1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Chanwoo Choi <cw00.choi@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 11 #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 12 13 /* CMU_TOP */ 14 #define CLK_FOUT_ISP_PLL 1 15 #define CLK_FOUT_AUD_PLL 2 16 17 #define CLK_MOUT_AUD_PLL 10 18 #define CLK_MOUT_ISP_PLL 11 19 #define CLK_MOUT_AUD_PLL_USER_T 12 20 #define CLK_MOUT_MPHY_PLL_USER 13 21 #define CLK_MOUT_MFC_PLL_USER 14 22 #define CLK_MOUT_BUS_PLL_USER 15 23 #define CLK_MOUT_ACLK_HEVC_400 16 24 #define CLK_MOUT_ACLK_CAM1_333 17 25 #define CLK_MOUT_ACLK_CAM1_552_B 18 26 #define CLK_MOUT_ACLK_CAM1_552_A 19 27 #define CLK_MOUT_ACLK_ISP_DIS_400 20 28 #define CLK_MOUT_ACLK_ISP_400 21 29 #define CLK_MOUT_ACLK_BUS0_400 22 30 #define CLK_MOUT_ACLK_MSCL_400_B 23 31 #define CLK_MOUT_ACLK_MSCL_400_A 24 32 #define CLK_MOUT_ACLK_GSCL_333 25 33 #define CLK_MOUT_ACLK_G2D_400_B 26 34 #define CLK_MOUT_ACLK_G2D_400_A 27 35 #define CLK_MOUT_SCLK_JPEG_C 28 36 #define CLK_MOUT_SCLK_JPEG_B 29 37 #define CLK_MOUT_SCLK_JPEG_A 30 38 #define CLK_MOUT_SCLK_MMC2_B 31 39 #define CLK_MOUT_SCLK_MMC2_A 32 40 #define CLK_MOUT_SCLK_MMC1_B 33 41 #define CLK_MOUT_SCLK_MMC1_A 34 42 #define CLK_MOUT_SCLK_MMC0_D 35 43 #define CLK_MOUT_SCLK_MMC0_C 36 44 #define CLK_MOUT_SCLK_MMC0_B 37 45 #define CLK_MOUT_SCLK_MMC0_A 38 46 #define CLK_MOUT_SCLK_SPI4 39 47 #define CLK_MOUT_SCLK_SPI3 40 48 #define CLK_MOUT_SCLK_UART2 41 49 #define CLK_MOUT_SCLK_UART1 42 50 #define CLK_MOUT_SCLK_UART0 43 51 #define CLK_MOUT_SCLK_SPI2 44 52 #define CLK_MOUT_SCLK_SPI1 45 53 #define CLK_MOUT_SCLK_SPI0 46 54 #define CLK_MOUT_ACLK_MFC_400_C 47 55 #define CLK_MOUT_ACLK_MFC_400_B 48 56 #define CLK_MOUT_ACLK_MFC_400_A 49 57 #define CLK_MOUT_SCLK_ISP_SENSOR2 50 58 #define CLK_MOUT_SCLK_ISP_SENSOR1 51 59 #define CLK_MOUT_SCLK_ISP_SENSOR0 52 60 #define CLK_MOUT_SCLK_ISP_UART 53 61 #define CLK_MOUT_SCLK_ISP_SPI1 54 62 #define CLK_MOUT_SCLK_ISP_SPI0 55 63 #define CLK_MOUT_SCLK_PCIE_100 56 64 #define CLK_MOUT_SCLK_UFSUNIPRO 57 65 #define CLK_MOUT_SCLK_USBHOST30 58 66 #define CLK_MOUT_SCLK_USBDRD30 59 67 #define CLK_MOUT_SCLK_SLIMBUS 60 68 #define CLK_MOUT_SCLK_SPDIF 61 69 #define CLK_MOUT_SCLK_AUDIO1 62 70 #define CLK_MOUT_SCLK_AUDIO0 63 71 #define CLK_MOUT_SCLK_HDMI_SPDIF 64 72 73 #define CLK_DIV_ACLK_FSYS_200 100 74 #define CLK_DIV_ACLK_IMEM_SSSX_266 101 75 #define CLK_DIV_ACLK_IMEM_200 102 76 #define CLK_DIV_ACLK_IMEM_266 103 77 #define CLK_DIV_ACLK_PERIC_66_B 104 78 #define CLK_DIV_ACLK_PERIC_66_A 105 79 #define CLK_DIV_ACLK_PERIS_66_B 106 80 #define CLK_DIV_ACLK_PERIS_66_A 107 81 #define CLK_DIV_SCLK_MMC1_B 108 82 #define CLK_DIV_SCLK_MMC1_A 109 83 #define CLK_DIV_SCLK_MMC0_B 110 84 #define CLK_DIV_SCLK_MMC0_A 111 85 #define CLK_DIV_SCLK_MMC2_B 112 86 #define CLK_DIV_SCLK_MMC2_A 113 87 #define CLK_DIV_SCLK_SPI1_B 114 88 #define CLK_DIV_SCLK_SPI1_A 115 89 #define CLK_DIV_SCLK_SPI0_B 116 90 #define CLK_DIV_SCLK_SPI0_A 117 91 #define CLK_DIV_SCLK_SPI2_B 118 92 #define CLK_DIV_SCLK_SPI2_A 119 93 #define CLK_DIV_SCLK_UART2 120 94 #define CLK_DIV_SCLK_UART1 121 95 #define CLK_DIV_SCLK_UART0 122 96 #define CLK_DIV_SCLK_SPI4_B 123 97 #define CLK_DIV_SCLK_SPI4_A 124 98 #define CLK_DIV_SCLK_SPI3_B 125 99 #define CLK_DIV_SCLK_SPI3_A 126 100 #define CLK_DIV_SCLK_I2S1 127 101 #define CLK_DIV_SCLK_PCM1 128 102 #define CLK_DIV_SCLK_AUDIO1 129 103 #define CLK_DIV_SCLK_AUDIO0 130 104 #define CLK_DIV_ACLK_GSCL_111 131 105 #define CLK_DIV_ACLK_GSCL_333 132 106 #define CLK_DIV_ACLK_HEVC_400 133 107 #define CLK_DIV_ACLK_MFC_400 134 108 #define CLK_DIV_ACLK_G2D_266 135 109 #define CLK_DIV_ACLK_G2D_400 136 110 #define CLK_DIV_ACLK_G3D_400 137 111 #define CLK_DIV_ACLK_BUS0_400 138 112 #define CLK_DIV_ACLK_BUS1_400 139 113 #define CLK_DIV_SCLK_PCIE_100 140 114 #define CLK_DIV_SCLK_USBHOST30 141 115 #define CLK_DIV_SCLK_UFSUNIPRO 142 116 #define CLK_DIV_SCLK_USBDRD30 143 117 118 #define CLK_ACLK_PERIC_66 200 119 #define CLK_ACLK_PERIS_66 201 120 #define CLK_ACLK_FSYS_200 202 121 #define CLK_SCLK_MMC2_FSYS 203 122 #define CLK_SCLK_MMC1_FSYS 204 123 #define CLK_SCLK_MMC0_FSYS 205 124 #define CLK_SCLK_SPI4_PERIC 206 125 #define CLK_SCLK_SPI3_PERIC 207 126 #define CLK_SCLK_UART2_PERIC 208 127 #define CLK_SCLK_UART1_PERIC 209 128 #define CLK_SCLK_UART0_PERIC 210 129 #define CLK_SCLK_SPI2_PERIC 211 130 #define CLK_SCLK_SPI1_PERIC 212 131 #define CLK_SCLK_SPI0_PERIC 213 132 #define CLK_SCLK_SPDIF_PERIC 214 133 #define CLK_SCLK_I2S1_PERIC 215 134 #define CLK_SCLK_PCM1_PERIC 216 135 #define CLK_SCLK_SLIMBUS 217 136 #define CLK_SCLK_AUDIO1 218 137 #define CLK_SCLK_AUDIO0 219 138 #define CLK_ACLK_G2D_266 220 139 #define CLK_ACLK_G2D_400 221 140 #define CLK_ACLK_G3D_400 222 141 #define CLK_ACLK_IMEM_SSX_266 223 142 #define CLK_ACLK_BUS0_400 224 143 #define CLK_ACLK_BUS1_400 225 144 #define CLK_ACLK_IMEM_200 226 145 #define CLK_ACLK_IMEM_266 227 146 #define CLK_SCLK_PCIE_100_FSYS 228 147 #define CLK_SCLK_UFSUNIPRO_FSYS 229 148 #define CLK_SCLK_USBHOST30_FSYS 230 149 #define CLK_SCLK_USBDRD30_FSYS 231 150 151 #define TOP_NR_CLK 232 152 153 /* CMU_CPIF */ 154 #define CLK_FOUT_MPHY_PLL 1 155 156 #define CLK_MOUT_MPHY_PLL 2 157 158 #define CLK_DIV_SCLK_MPHY 10 159 160 #define CLK_SCLK_MPHY_PLL 11 161 #define CLK_SCLK_UFS_MPHY 11 162 163 #define CPIF_NR_CLK 12 164 165 /* CMU_MIF */ 166 #define CLK_FOUT_MEM0_PLL 1 167 #define CLK_FOUT_MEM1_PLL 2 168 #define CLK_FOUT_BUS_PLL 3 169 #define CLK_FOUT_MFC_PLL 4 170 #define CLK_DOUT_MFC_PLL 5 171 #define CLK_DOUT_BUS_PLL 6 172 #define CLK_DOUT_MEM1_PLL 7 173 #define CLK_DOUT_MEM0_PLL 8 174 175 #define CLK_MOUT_MFC_PLL_DIV2 10 176 #define CLK_MOUT_BUS_PLL_DIV2 11 177 #define CLK_MOUT_MEM1_PLL_DIV2 12 178 #define CLK_MOUT_MEM0_PLL_DIV2 13 179 #define CLK_MOUT_MFC_PLL 14 180 #define CLK_MOUT_BUS_PLL 15 181 #define CLK_MOUT_MEM1_PLL 16 182 #define CLK_MOUT_MEM0_PLL 17 183 #define CLK_MOUT_CLK2X_PHY_C 18 184 #define CLK_MOUT_CLK2X_PHY_B 19 185 #define CLK_MOUT_CLK2X_PHY_A 20 186 #define CLK_MOUT_CLKM_PHY_C 21 187 #define CLK_MOUT_CLKM_PHY_B 22 188 #define CLK_MOUT_CLKM_PHY_A 23 189 #define CLK_MOUT_ACLK_MIFNM_200 24 190 #define CLK_MOUT_ACLK_MIFNM_400 25 191 #define CLK_MOUT_ACLK_DISP_333_B 26 192 #define CLK_MOUT_ACLK_DISP_333_A 27 193 #define CLK_MOUT_SCLK_DECON_VCLK_C 28 194 #define CLK_MOUT_SCLK_DECON_VCLK_B 29 195 #define CLK_MOUT_SCLK_DECON_VCLK_A 30 196 #define CLK_MOUT_SCLK_DECON_ECLK_C 31 197 #define CLK_MOUT_SCLK_DECON_ECLK_B 32 198 #define CLK_MOUT_SCLK_DECON_ECLK_A 33 199 #define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34 200 #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35 201 #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36 202 #define CLK_MOUT_SCLK_DSD_C 37 203 #define CLK_MOUT_SCLK_DSD_B 38 204 #define CLK_MOUT_SCLK_DSD_A 39 205 #define CLK_MOUT_SCLK_DSIM0_C 40 206 #define CLK_MOUT_SCLK_DSIM0_B 41 207 #define CLK_MOUT_SCLK_DSIM0_A 42 208 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46 209 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47 210 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48 211 #define CLK_MOUT_SCLK_DSIM1_C 49 212 #define CLK_MOUT_SCLK_DSIM1_B 50 213 #define CLK_MOUT_SCLK_DSIM1_A 51 214 215 #define CLK_DIV_SCLK_HPM_MIF 55 216 #define CLK_DIV_ACLK_DREX1 56 217 #define CLK_DIV_ACLK_DREX0 57 218 #define CLK_DIV_CLK2XPHY 58 219 #define CLK_DIV_ACLK_MIF_266 59 220 #define CLK_DIV_ACLK_MIFND_133 60 221 #define CLK_DIV_ACLK_MIF_133 61 222 #define CLK_DIV_ACLK_MIFNM_200 62 223 #define CLK_DIV_ACLK_MIF_200 63 224 #define CLK_DIV_ACLK_MIF_400 64 225 #define CLK_DIV_ACLK_BUS2_400 65 226 #define CLK_DIV_ACLK_DISP_333 66 227 #define CLK_DIV_ACLK_CPIF_200 67 228 #define CLK_DIV_SCLK_DSIM1 68 229 #define CLK_DIV_SCLK_DECON_TV_VCLK 69 230 #define CLK_DIV_SCLK_DSIM0 70 231 #define CLK_DIV_SCLK_DSD 71 232 #define CLK_DIV_SCLK_DECON_TV_ECLK 72 233 #define CLK_DIV_SCLK_DECON_VCLK 73 234 #define CLK_DIV_SCLK_DECON_ECLK 74 235 #define CLK_DIV_MIF_PRE 75 236 237 #define CLK_CLK2X_PHY1 80 238 #define CLK_CLK2X_PHY0 81 239 #define CLK_CLKM_PHY1 82 240 #define CLK_CLKM_PHY0 83 241 #define CLK_RCLK_DREX1 84 242 #define CLK_RCLK_DREX0 85 243 #define CLK_ACLK_DREX1_TZ 86 244 #define CLK_ACLK_DREX0_TZ 87 245 #define CLK_ACLK_DREX1_PEREV 88 246 #define CLK_ACLK_DREX0_PEREV 89 247 #define CLK_ACLK_DREX1_MEMIF 90 248 #define CLK_ACLK_DREX0_MEMIF 91 249 #define CLK_ACLK_DREX1_SCH 92 250 #define CLK_ACLK_DREX0_SCH 93 251 #define CLK_ACLK_DREX1_BUSIF 94 252 #define CLK_ACLK_DREX0_BUSIF 95 253 #define CLK_ACLK_DREX1_BUSIF_RD 96 254 #define CLK_ACLK_DREX0_BUSIF_RD 97 255 #define CLK_ACLK_DREX1 98 256 #define CLK_ACLK_DREX0 99 257 #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100 258 #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101 259 #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102 260 #define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103 261 #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104 262 #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105 263 #define CLK_ACLK_ASYNCAXIS_CP1 106 264 #define CLK_ACLK_ASYNCAXIM_CP1 107 265 #define CLK_ACLK_ASYNCAXIS_CP0 108 266 #define CLK_ACLK_ASYNCAXIM_CP0 109 267 #define CLK_ACLK_ASYNCAXIS_DREX1_3 110 268 #define CLK_ACLK_ASYNCAXIM_DREX1_3 111 269 #define CLK_ACLK_ASYNCAXIS_DREX1_1 112 270 #define CLK_ACLK_ASYNCAXIM_DREX1_1 113 271 #define CLK_ACLK_ASYNCAXIS_DREX1_0 114 272 #define CLK_ACLK_ASYNCAXIM_DREX1_0 115 273 #define CLK_ACLK_ASYNCAXIS_DREX0_3 116 274 #define CLK_ACLK_ASYNCAXIM_DREX0_3 117 275 #define CLK_ACLK_ASYNCAXIS_DREX0_1 118 276 #define CLK_ACLK_ASYNCAXIM_DREX0_1 119 277 #define CLK_ACLK_ASYNCAXIS_DREX0_0 120 278 #define CLK_ACLK_ASYNCAXIM_DREX0_0 121 279 #define CLK_ACLK_AHB2APB_MIF2P 122 280 #define CLK_ACLK_AHB2APB_MIF1P 123 281 #define CLK_ACLK_AHB2APB_MIF0P 124 282 #define CLK_ACLK_IXIU_CCI 125 283 #define CLK_ACLK_XIU_MIFSFRX 126 284 #define CLK_ACLK_MIFNP_133 127 285 #define CLK_ACLK_MIFNM_200 128 286 #define CLK_ACLK_MIFND_133 129 287 #define CLK_ACLK_MIFND_400 130 288 #define CLK_ACLK_CCI 131 289 #define CLK_ACLK_MIFND_266 132 290 #define CLK_ACLK_PPMU_DREX1S3 133 291 #define CLK_ACLK_PPMU_DREX1S1 134 292 #define CLK_ACLK_PPMU_DREX1S0 135 293 #define CLK_ACLK_PPMU_DREX0S3 136 294 #define CLK_ACLK_PPMU_DREX0S1 137 295 #define CLK_ACLK_PPMU_DREX0S0 138 296 #define CLK_ACLK_BTS_APOLLO 139 297 #define CLK_ACLK_BTS_ATLAS 140 298 #define CLK_ACLK_ACE_SEL_APOLL 141 299 #define CLK_ACLK_ACE_SEL_ATLAS 142 300 #define CLK_ACLK_AXIDS_CCI_MIFSFRX 143 301 #define CLK_ACLK_AXIUS_ATLAS_CCI 144 302 #define CLK_ACLK_AXISYNCDNS_CCI 145 303 #define CLK_ACLK_AXISYNCDN_CCI 146 304 #define CLK_ACLK_AXISYNCDN_NOC_D 147 305 #define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148 306 #define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149 307 #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150 308 #define CLK_ACLK_BUS2_400 151 309 #define CLK_ACLK_DISP_333 152 310 #define CLK_ACLK_CPIF_200 153 311 #define CLK_PCLK_PPMU_DREX1S3 154 312 #define CLK_PCLK_PPMU_DREX1S1 155 313 #define CLK_PCLK_PPMU_DREX1S0 156 314 #define CLK_PCLK_PPMU_DREX0S3 157 315 #define CLK_PCLK_PPMU_DREX0S1 158 316 #define CLK_PCLK_PPMU_DREX0S0 159 317 #define CLK_PCLK_BTS_APOLLO 160 318 #define CLK_PCLK_BTS_ATLAS 161 319 #define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162 320 #define CLK_PCLK_ASYNCAXI_CP1 163 321 #define CLK_PCLK_ASYNCAXI_CP0 164 322 #define CLK_PCLK_ASYNCAXI_DREX1_3 165 323 #define CLK_PCLK_ASYNCAXI_DREX1_1 166 324 #define CLK_PCLK_ASYNCAXI_DREX1_0 167 325 #define CLK_PCLK_ASYNCAXI_DREX0_3 168 326 #define CLK_PCLK_ASYNCAXI_DREX0_1 169 327 #define CLK_PCLK_ASYNCAXI_DREX0_0 170 328 #define CLK_PCLK_MIFSRVND_133 171 329 #define CLK_PCLK_PMU_MIF 172 330 #define CLK_PCLK_SYSREG_MIF 173 331 #define CLK_PCLK_GPIO_ALIVE 174 332 #define CLK_PCLK_ABB 175 333 #define CLK_PCLK_PMU_APBIF 176 334 #define CLK_PCLK_DDR_PHY1 177 335 #define CLK_PCLK_DREX1 178 336 #define CLK_PCLK_DDR_PHY0 179 337 #define CLK_PCLK_DREX0 180 338 #define CLK_PCLK_DREX0_TZ 181 339 #define CLK_PCLK_DREX1_TZ 182 340 #define CLK_PCLK_MONOTONIC_CNT 183 341 #define CLK_PCLK_RTC 184 342 #define CLK_SCLK_DSIM1_DISP 185 343 #define CLK_SCLK_DECON_TV_VCLK_DISP 186 344 #define CLK_SCLK_FREQ_DET_BUS_PLL 187 345 #define CLK_SCLK_FREQ_DET_MFC_PLL 188 346 #define CLK_SCLK_FREQ_DET_MEM0_PLL 189 347 #define CLK_SCLK_FREQ_DET_MEM1_PLL 190 348 #define CLK_SCLK_DSIM0_DISP 191 349 #define CLK_SCLK_DSD_DISP 192 350 #define CLK_SCLK_DECON_TV_ECLK_DISP 193 351 #define CLK_SCLK_DECON_VCLK_DISP 194 352 #define CLK_SCLK_DECON_ECLK_DISP 195 353 #define CLK_SCLK_HPM_MIF 196 354 #define CLK_SCLK_MFC_PLL 197 355 #define CLK_SCLK_BUS_PLL 198 356 #define CLK_SCLK_BUS_PLL_APOLLO 199 357 #define CLK_SCLK_BUS_PLL_ATLAS 200 358 #define CLK_SCLK_HDMI_SPDIF_DISP 201 359 360 #define MIF_NR_CLK 202 361 362 /* CMU_PERIC */ 363 #define CLK_PCLK_SPI2 1 364 #define CLK_PCLK_SPI1 2 365 #define CLK_PCLK_SPI0 3 366 #define CLK_PCLK_UART2 4 367 #define CLK_PCLK_UART1 5 368 #define CLK_PCLK_UART0 6 369 #define CLK_PCLK_HSI2C3 7 370 #define CLK_PCLK_HSI2C2 8 371 #define CLK_PCLK_HSI2C1 9 372 #define CLK_PCLK_HSI2C0 10 373 #define CLK_PCLK_I2C7 11 374 #define CLK_PCLK_I2C6 12 375 #define CLK_PCLK_I2C5 13 376 #define CLK_PCLK_I2C4 14 377 #define CLK_PCLK_I2C3 15 378 #define CLK_PCLK_I2C2 16 379 #define CLK_PCLK_I2C1 17 380 #define CLK_PCLK_I2C0 18 381 #define CLK_PCLK_SPI4 19 382 #define CLK_PCLK_SPI3 20 383 #define CLK_PCLK_HSI2C11 21 384 #define CLK_PCLK_HSI2C10 22 385 #define CLK_PCLK_HSI2C9 23 386 #define CLK_PCLK_HSI2C8 24 387 #define CLK_PCLK_HSI2C7 25 388 #define CLK_PCLK_HSI2C6 26 389 #define CLK_PCLK_HSI2C5 27 390 #define CLK_PCLK_HSI2C4 28 391 #define CLK_SCLK_SPI4 29 392 #define CLK_SCLK_SPI3 30 393 #define CLK_SCLK_SPI2 31 394 #define CLK_SCLK_SPI1 32 395 #define CLK_SCLK_SPI0 33 396 #define CLK_SCLK_UART2 34 397 #define CLK_SCLK_UART1 35 398 #define CLK_SCLK_UART0 36 399 #define CLK_ACLK_AHB2APB_PERIC2P 37 400 #define CLK_ACLK_AHB2APB_PERIC1P 38 401 #define CLK_ACLK_AHB2APB_PERIC0P 39 402 #define CLK_ACLK_PERICNP_66 40 403 #define CLK_PCLK_SCI 41 404 #define CLK_PCLK_GPIO_FINGER 42 405 #define CLK_PCLK_GPIO_ESE 43 406 #define CLK_PCLK_PWM 44 407 #define CLK_PCLK_SPDIF 45 408 #define CLK_PCLK_PCM1 46 409 #define CLK_PCLK_I2S1 47 410 #define CLK_PCLK_ADCIF 48 411 #define CLK_PCLK_GPIO_TOUCH 49 412 #define CLK_PCLK_GPIO_NFC 50 413 #define CLK_PCLK_GPIO_PERIC 51 414 #define CLK_PCLK_PMU_PERIC 52 415 #define CLK_PCLK_SYSREG_PERIC 53 416 #define CLK_SCLK_IOCLK_SPI4 54 417 #define CLK_SCLK_IOCLK_SPI3 55 418 #define CLK_SCLK_SCI 56 419 #define CLK_SCLK_SC_IN 57 420 #define CLK_SCLK_PWM 58 421 #define CLK_SCLK_IOCLK_SPI2 59 422 #define CLK_SCLK_IOCLK_SPI1 60 423 #define CLK_SCLK_IOCLK_SPI0 61 424 #define CLK_SCLK_IOCLK_I2S1_BCLK 62 425 #define CLK_SCLK_SPDIF 63 426 #define CLK_SCLK_PCM1 64 427 #define CLK_SCLK_I2S1 65 428 429 #define CLK_DIV_SCLK_SCI 70 430 #define CLK_DIV_SCLK_SC_IN 71 431 432 #define PERIC_NR_CLK 72 433 434 /* CMU_PERIS */ 435 #define CLK_PCLK_HPM_APBIF 1 436 #define CLK_PCLK_TMU1_APBIF 2 437 #define CLK_PCLK_TMU0_APBIF 3 438 #define CLK_PCLK_PMU_PERIS 4 439 #define CLK_PCLK_SYSREG_PERIS 5 440 #define CLK_PCLK_CMU_TOP_APBIF 6 441 #define CLK_PCLK_WDT_APOLLO 7 442 #define CLK_PCLK_WDT_ATLAS 8 443 #define CLK_PCLK_MCT 9 444 #define CLK_PCLK_HDMI_CEC 10 445 #define CLK_ACLK_AHB2APB_PERIS1P 11 446 #define CLK_ACLK_AHB2APB_PERIS0P 12 447 #define CLK_ACLK_PERISNP_66 13 448 #define CLK_PCLK_TZPC12 14 449 #define CLK_PCLK_TZPC11 15 450 #define CLK_PCLK_TZPC10 16 451 #define CLK_PCLK_TZPC9 17 452 #define CLK_PCLK_TZPC8 18 453 #define CLK_PCLK_TZPC7 19 454 #define CLK_PCLK_TZPC6 20 455 #define CLK_PCLK_TZPC5 21 456 #define CLK_PCLK_TZPC4 22 457 #define CLK_PCLK_TZPC3 23 458 #define CLK_PCLK_TZPC2 24 459 #define CLK_PCLK_TZPC1 25 460 #define CLK_PCLK_TZPC0 26 461 #define CLK_PCLK_SECKEY_APBIF 27 462 #define CLK_PCLK_CHIPID_APBIF 28 463 #define CLK_PCLK_TOPRTC 29 464 #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 465 #define CLK_PCLK_ANTIRBK_CNT_APBIF 31 466 #define CLK_PCLK_OTP_CON_APBIF 32 467 #define CLK_SCLK_ASV_TB 33 468 #define CLK_SCLK_TMU1 34 469 #define CLK_SCLK_TMU0 35 470 #define CLK_SCLK_SECKEY 36 471 #define CLK_SCLK_CHIPID 37 472 #define CLK_SCLK_TOPRTC 38 473 #define CLK_SCLK_CUSTOM_EFUSE 39 474 #define CLK_SCLK_ANTIRBK_CNT 40 475 #define CLK_SCLK_OTP_CON 41 476 477 #define PERIS_NR_CLK 42 478 479 /* CMU_FSYS */ 480 #define CLK_MOUT_ACLK_FSYS_200_USER 1 481 #define CLK_MOUT_SCLK_MMC2_USER 2 482 #define CLK_MOUT_SCLK_MMC1_USER 3 483 #define CLK_MOUT_SCLK_MMC0_USER 4 484 #define CLK_MOUT_SCLK_UFS_MPHY_USER 5 485 #define CLK_MOUT_SCLK_PCIE_100_USER 6 486 #define CLK_MOUT_SCLK_UFSUNIPRO_USER 7 487 #define CLK_MOUT_SCLK_USBHOST30_USER 8 488 #define CLK_MOUT_SCLK_USBDRD30_USER 9 489 #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10 490 #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11 491 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12 492 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13 493 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14 494 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15 495 #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16 496 #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17 497 #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18 498 #define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19 499 #define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20 500 #define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21 501 #define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22 502 #define CLK_MOUT_SCLK_MPHY 23 503 504 #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25 505 #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26 506 #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27 507 #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28 508 #define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29 509 #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30 510 #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31 511 #define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32 512 #define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33 513 #define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34 514 #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35 515 #define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36 516 #define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37 517 518 #define CLK_ACLK_PCIE 50 519 #define CLK_ACLK_PDMA1 51 520 #define CLK_ACLK_TSI 52 521 #define CLK_ACLK_MMC2 53 522 #define CLK_ACLK_MMC1 54 523 #define CLK_ACLK_MMC0 55 524 #define CLK_ACLK_UFS 56 525 #define CLK_ACLK_USBHOST20 57 526 #define CLK_ACLK_USBHOST30 58 527 #define CLK_ACLK_USBDRD30 59 528 #define CLK_ACLK_PDMA0 60 529 #define CLK_SCLK_MMC2 61 530 #define CLK_SCLK_MMC1 62 531 #define CLK_SCLK_MMC0 63 532 #define CLK_PDMA1 64 533 #define CLK_PDMA0 65 534 #define CLK_ACLK_XIU_FSYSPX 66 535 #define CLK_ACLK_AHB_USBLINKH1 67 536 #define CLK_ACLK_SMMU_PDMA1 68 537 #define CLK_ACLK_BTS_PCIE 69 538 #define CLK_ACLK_AXIUS_PDMA1 70 539 #define CLK_ACLK_SMMU_PDMA0 71 540 #define CLK_ACLK_BTS_UFS 72 541 #define CLK_ACLK_BTS_USBHOST30 73 542 #define CLK_ACLK_BTS_USBDRD30 74 543 #define CLK_ACLK_AXIUS_PDMA0 75 544 #define CLK_ACLK_AXIUS_USBHS 76 545 #define CLK_ACLK_AXIUS_FSYSSX 77 546 #define CLK_ACLK_AHB2APB_FSYSP 78 547 #define CLK_ACLK_AHB2AXI_USBHS 79 548 #define CLK_ACLK_AHB_USBLINKH0 80 549 #define CLK_ACLK_AHB_USBHS 81 550 #define CLK_ACLK_AHB_FSYSH 82 551 #define CLK_ACLK_XIU_FSYSX 83 552 #define CLK_ACLK_XIU_FSYSSX 84 553 #define CLK_ACLK_FSYSNP_200 85 554 #define CLK_ACLK_FSYSND_200 86 555 #define CLK_PCLK_PCIE_CTRL 87 556 #define CLK_PCLK_SMMU_PDMA1 88 557 #define CLK_PCLK_PCIE_PHY 89 558 #define CLK_PCLK_BTS_PCIE 90 559 #define CLK_PCLK_SMMU_PDMA0 91 560 #define CLK_PCLK_BTS_UFS 92 561 #define CLK_PCLK_BTS_USBHOST30 93 562 #define CLK_PCLK_BTS_USBDRD30 94 563 #define CLK_PCLK_GPIO_FSYS 95 564 #define CLK_PCLK_PMU_FSYS 96 565 #define CLK_PCLK_SYSREG_FSYS 97 566 #define CLK_SCLK_PCIE_100 98 567 #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99 568 #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100 569 #define CLK_PHYCLK_UFS_RX1_SYMBOL 101 570 #define CLK_PHYCLK_UFS_RX0_SYMBOL 102 571 #define CLK_PHYCLK_UFS_TX1_SYMBOL 103 572 #define CLK_PHYCLK_UFS_TX0_SYMBOL 104 573 #define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105 574 #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106 575 #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107 576 #define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108 577 #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109 578 #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110 579 #define CLK_SCLK_MPHY 111 580 #define CLK_SCLK_UFSUNIPRO 112 581 #define CLK_SCLK_USBHOST30 113 582 #define CLK_SCLK_USBDRD30 114 583 584 #define FSYS_NR_CLK 115 585 586 /* CMU_G2D */ 587 #define CLK_MUX_ACLK_G2D_266_USER 1 588 #define CLK_MUX_ACLK_G2D_400_USER 2 589 590 #define CLK_DIV_PCLK_G2D 3 591 592 #define CLK_ACLK_SMMU_MDMA1 4 593 #define CLK_ACLK_BTS_MDMA1 5 594 #define CLK_ACLK_BTS_G2D 6 595 #define CLK_ACLK_ALB_G2D 7 596 #define CLK_ACLK_AXIUS_G2DX 8 597 #define CLK_ACLK_ASYNCAXI_SYSX 9 598 #define CLK_ACLK_AHB2APB_G2D1P 10 599 #define CLK_ACLK_AHB2APB_G2D0P 11 600 #define CLK_ACLK_XIU_G2DX 12 601 #define CLK_ACLK_G2DNP_133 13 602 #define CLK_ACLK_G2DND_400 14 603 #define CLK_ACLK_MDMA1 15 604 #define CLK_ACLK_G2D 16 605 #define CLK_ACLK_SMMU_G2D 17 606 #define CLK_PCLK_SMMU_MDMA1 18 607 #define CLK_PCLK_BTS_MDMA1 19 608 #define CLK_PCLK_BTS_G2D 20 609 #define CLK_PCLK_ALB_G2D 21 610 #define CLK_PCLK_ASYNCAXI_SYSX 22 611 #define CLK_PCLK_PMU_G2D 23 612 #define CLK_PCLK_SYSREG_G2D 24 613 #define CLK_PCLK_G2D 25 614 #define CLK_PCLK_SMMU_G2D 26 615 616 #define G2D_NR_CLK 27 617 618 /* CMU_DISP */ 619 #define CLK_FOUT_DISP_PLL 1 620 621 #define CLK_MOUT_DISP_PLL 2 622 #define CLK_MOUT_SCLK_DSIM1_USER 3 623 #define CLK_MOUT_SCLK_DSIM0_USER 4 624 #define CLK_MOUT_SCLK_DSD_USER 5 625 #define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6 626 #define CLK_MOUT_SCLK_DECON_VCLK_USER 7 627 #define CLK_MOUT_SCLK_DECON_ECLK_USER 8 628 #define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9 629 #define CLK_MOUT_ACLK_DISP_333_USER 10 630 #define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11 631 #define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12 632 #define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13 633 #define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14 634 #define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15 635 #define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16 636 #define CLK_MOUT_SCLK_DSIM0 17 637 #define CLK_MOUT_SCLK_DECON_TV_ECLK 18 638 #define CLK_MOUT_SCLK_DECON_VCLK 19 639 #define CLK_MOUT_SCLK_DECON_ECLK 20 640 #define CLK_MOUT_SCLK_DSIM1_B_DISP 21 641 #define CLK_MOUT_SCLK_DSIM1_A_DISP 22 642 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23 643 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24 644 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25 645 646 #define CLK_DIV_SCLK_DSIM1_DISP 30 647 #define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31 648 #define CLK_DIV_SCLK_DSIM0_DISP 32 649 #define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33 650 #define CLK_DIV_SCLK_DECON_VCLK_DISP 34 651 #define CLK_DIV_SCLK_DECON_ECLK_DISP 35 652 #define CLK_DIV_PCLK_DISP 36 653 654 #define CLK_ACLK_DECON_TV 40 655 #define CLK_ACLK_DECON 41 656 #define CLK_ACLK_SMMU_TV1X 42 657 #define CLK_ACLK_SMMU_TV0X 43 658 #define CLK_ACLK_SMMU_DECON1X 44 659 #define CLK_ACLK_SMMU_DECON0X 45 660 #define CLK_ACLK_BTS_DECON_TV_M3 46 661 #define CLK_ACLK_BTS_DECON_TV_M2 47 662 #define CLK_ACLK_BTS_DECON_TV_M1 48 663 #define CLK_ACLK_BTS_DECON_TV_M0 49 664 #define CLK_ACLK_BTS_DECON_NM4 50 665 #define CLK_ACLK_BTS_DECON_NM3 51 666 #define CLK_ACLK_BTS_DECON_NM2 52 667 #define CLK_ACLK_BTS_DECON_NM1 53 668 #define CLK_ACLK_BTS_DECON_NM0 54 669 #define CLK_ACLK_AHB2APB_DISPSFR2P 55 670 #define CLK_ACLK_AHB2APB_DISPSFR1P 56 671 #define CLK_ACLK_AHB2APB_DISPSFR0P 57 672 #define CLK_ACLK_AHB_DISPH 58 673 #define CLK_ACLK_XIU_TV1X 59 674 #define CLK_ACLK_XIU_TV0X 60 675 #define CLK_ACLK_XIU_DECON1X 61 676 #define CLK_ACLK_XIU_DECON0X 62 677 #define CLK_ACLK_XIU_DISP1X 63 678 #define CLK_ACLK_XIU_DISPNP_100 64 679 #define CLK_ACLK_DISP1ND_333 65 680 #define CLK_ACLK_DISP0ND_333 66 681 #define CLK_PCLK_SMMU_TV1X 67 682 #define CLK_PCLK_SMMU_TV0X 68 683 #define CLK_PCLK_SMMU_DECON1X 69 684 #define CLK_PCLK_SMMU_DECON0X 70 685 #define CLK_PCLK_BTS_DECON_TV_M3 71 686 #define CLK_PCLK_BTS_DECON_TV_M2 72 687 #define CLK_PCLK_BTS_DECON_TV_M1 73 688 #define CLK_PCLK_BTS_DECON_TV_M0 74 689 #define CLK_PCLK_BTS_DECONM4 75 690 #define CLK_PCLK_BTS_DECONM3 76 691 #define CLK_PCLK_BTS_DECONM2 77 692 #define CLK_PCLK_BTS_DECONM1 78 693 #define CLK_PCLK_BTS_DECONM0 79 694 #define CLK_PCLK_MIC1 80 695 #define CLK_PCLK_PMU_DISP 81 696 #define CLK_PCLK_SYSREG_DISP 82 697 #define CLK_PCLK_HDMIPHY 83 698 #define CLK_PCLK_HDMI 84 699 #define CLK_PCLK_MIC0 85 700 #define CLK_PCLK_DSIM1 86 701 #define CLK_PCLK_DSIM0 87 702 #define CLK_PCLK_DECON_TV 88 703 #define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89 704 #define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90 705 #define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91 706 #define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92 707 #define CLK_SCLK_DSIM1 93 708 #define CLK_SCLK_DECON_TV_VCLK 94 709 #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95 710 #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96 711 #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97 712 #define CLK_PHYCLK_HDMI_PIXEL 98 713 #define CLK_SCLK_RGB_VCLK_TO_SMIES 99 714 #define CLK_SCLK_FREQ_DET_DISP_PLL 100 715 #define CLK_SCLK_RGB_VCLK_TO_DSIM0 101 716 #define CLK_SCLK_RGB_VCLK_TO_MIC0 102 717 #define CLK_SCLK_DSD 103 718 #define CLK_SCLK_HDMI_SPDIF 104 719 #define CLK_SCLK_DSIM0 105 720 #define CLK_SCLK_DECON_TV_ECLK 106 721 #define CLK_SCLK_DECON_VCLK 107 722 #define CLK_SCLK_DECON_ECLK 108 723 #define CLK_SCLK_RGB_VCLK 109 724 #define CLK_SCLK_RGB_TV_VCLK 110 725 726 #define DISP_NR_CLK 111 727 728 /* CMU_AUD */ 729 #define CLK_MOUT_AUD_PLL_USER 1 730 #define CLK_MOUT_SCLK_AUD_PCM 2 731 #define CLK_MOUT_SCLK_AUD_I2S 3 732 733 #define CLK_DIV_ATCLK_AUD 4 734 #define CLK_DIV_PCLK_DBG_AUD 5 735 #define CLK_DIV_ACLK_AUD 6 736 #define CLK_DIV_AUD_CA5 7 737 #define CLK_DIV_SCLK_AUD_SLIMBUS 8 738 #define CLK_DIV_SCLK_AUD_UART 9 739 #define CLK_DIV_SCLK_AUD_PCM 10 740 #define CLK_DIV_SCLK_AUD_I2S 11 741 742 #define CLK_ACLK_INTR_CTRL 12 743 #define CLK_ACLK_AXIDS2_LPASSP 13 744 #define CLK_ACLK_AXIDS1_LPASSP 14 745 #define CLK_ACLK_AXI2APB1_LPASSP 15 746 #define CLK_ACLK_AXI2APH_LPASSP 16 747 #define CLK_ACLK_SMMU_LPASSX 17 748 #define CLK_ACLK_AXIDS0_LPASSP 18 749 #define CLK_ACLK_AXI2APB0_LPASSP 19 750 #define CLK_ACLK_XIU_LPASSX 20 751 #define CLK_ACLK_AUDNP_133 21 752 #define CLK_ACLK_AUDND_133 22 753 #define CLK_ACLK_SRAMC 23 754 #define CLK_ACLK_DMAC 24 755 #define CLK_PCLK_WDT1 25 756 #define CLK_PCLK_WDT0 26 757 #define CLK_PCLK_SFR1 27 758 #define CLK_PCLK_SMMU_LPASSX 28 759 #define CLK_PCLK_GPIO_AUD 29 760 #define CLK_PCLK_PMU_AUD 30 761 #define CLK_PCLK_SYSREG_AUD 31 762 #define CLK_PCLK_AUD_SLIMBUS 32 763 #define CLK_PCLK_AUD_UART 33 764 #define CLK_PCLK_AUD_PCM 34 765 #define CLK_PCLK_AUD_I2S 35 766 #define CLK_PCLK_TIMER 36 767 #define CLK_PCLK_SFR0_CTRL 37 768 #define CLK_ATCLK_AUD 38 769 #define CLK_PCLK_DBG_AUD 39 770 #define CLK_SCLK_AUD_CA5 40 771 #define CLK_SCLK_JTAG_TCK 41 772 #define CLK_SCLK_SLIMBUS_CLKIN 42 773 #define CLK_SCLK_AUD_SLIMBUS 43 774 #define CLK_SCLK_AUD_UART 44 775 #define CLK_SCLK_AUD_PCM 45 776 #define CLK_SCLK_I2S_BCLK 46 777 #define CLK_SCLK_AUD_I2S 47 778 779 #define AUD_NR_CLK 48 780 781 /* CMU_BUS{0|1|2} */ 782 #define CLK_DIV_PCLK_BUS_133 1 783 784 #define CLK_ACLK_AHB2APB_BUSP 2 785 #define CLK_ACLK_BUSNP_133 3 786 #define CLK_ACLK_BUSND_400 4 787 #define CLK_PCLK_BUSSRVND_133 5 788 #define CLK_PCLK_PMU_BUS 6 789 #define CLK_PCLK_SYSREG_BUS 7 790 791 #define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */ 792 #define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ 793 #define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ 794 795 #define BUSx_NR_CLK 11 796 797 /* CMU_G3D */ 798 #define CLK_FOUT_G3D_PLL 1 799 800 #define CLK_MOUT_ACLK_G3D_400 2 801 #define CLK_MOUT_G3D_PLL 3 802 803 #define CLK_DIV_SCLK_HPM_G3D 4 804 #define CLK_DIV_PCLK_G3D 5 805 #define CLK_DIV_ACLK_G3D 6 806 #define CLK_ACLK_BTS_G3D1 7 807 #define CLK_ACLK_BTS_G3D0 8 808 #define CLK_ACLK_ASYNCAPBS_G3D 9 809 #define CLK_ACLK_ASYNCAPBM_G3D 10 810 #define CLK_ACLK_AHB2APB_G3DP 11 811 #define CLK_ACLK_G3DNP_150 12 812 #define CLK_ACLK_G3DND_600 13 813 #define CLK_ACLK_G3D 14 814 #define CLK_PCLK_BTS_G3D1 15 815 #define CLK_PCLK_BTS_G3D0 16 816 #define CLK_PCLK_PMU_G3D 17 817 #define CLK_PCLK_SYSREG_G3D 18 818 #define CLK_SCLK_HPM_G3D 19 819 820 #define G3D_NR_CLK 20 821 822 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 823