1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 4 * Author: Chanwoo Choi <cw00.choi@samsung.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 8 #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 9 10 /* CMU_TOP */ 11 #define CLK_FOUT_ISP_PLL 1 12 #define CLK_FOUT_AUD_PLL 2 13 14 #define CLK_MOUT_AUD_PLL 10 15 #define CLK_MOUT_ISP_PLL 11 16 #define CLK_MOUT_AUD_PLL_USER_T 12 17 #define CLK_MOUT_MPHY_PLL_USER 13 18 #define CLK_MOUT_MFC_PLL_USER 14 19 #define CLK_MOUT_BUS_PLL_USER 15 20 #define CLK_MOUT_ACLK_HEVC_400 16 21 #define CLK_MOUT_ACLK_CAM1_333 17 22 #define CLK_MOUT_ACLK_CAM1_552_B 18 23 #define CLK_MOUT_ACLK_CAM1_552_A 19 24 #define CLK_MOUT_ACLK_ISP_DIS_400 20 25 #define CLK_MOUT_ACLK_ISP_400 21 26 #define CLK_MOUT_ACLK_BUS0_400 22 27 #define CLK_MOUT_ACLK_MSCL_400_B 23 28 #define CLK_MOUT_ACLK_MSCL_400_A 24 29 #define CLK_MOUT_ACLK_GSCL_333 25 30 #define CLK_MOUT_ACLK_G2D_400_B 26 31 #define CLK_MOUT_ACLK_G2D_400_A 27 32 #define CLK_MOUT_SCLK_JPEG_C 28 33 #define CLK_MOUT_SCLK_JPEG_B 29 34 #define CLK_MOUT_SCLK_JPEG_A 30 35 #define CLK_MOUT_SCLK_MMC2_B 31 36 #define CLK_MOUT_SCLK_MMC2_A 32 37 #define CLK_MOUT_SCLK_MMC1_B 33 38 #define CLK_MOUT_SCLK_MMC1_A 34 39 #define CLK_MOUT_SCLK_MMC0_D 35 40 #define CLK_MOUT_SCLK_MMC0_C 36 41 #define CLK_MOUT_SCLK_MMC0_B 37 42 #define CLK_MOUT_SCLK_MMC0_A 38 43 #define CLK_MOUT_SCLK_SPI4 39 44 #define CLK_MOUT_SCLK_SPI3 40 45 #define CLK_MOUT_SCLK_UART2 41 46 #define CLK_MOUT_SCLK_UART1 42 47 #define CLK_MOUT_SCLK_UART0 43 48 #define CLK_MOUT_SCLK_SPI2 44 49 #define CLK_MOUT_SCLK_SPI1 45 50 #define CLK_MOUT_SCLK_SPI0 46 51 #define CLK_MOUT_ACLK_MFC_400_C 47 52 #define CLK_MOUT_ACLK_MFC_400_B 48 53 #define CLK_MOUT_ACLK_MFC_400_A 49 54 #define CLK_MOUT_SCLK_ISP_SENSOR2 50 55 #define CLK_MOUT_SCLK_ISP_SENSOR1 51 56 #define CLK_MOUT_SCLK_ISP_SENSOR0 52 57 #define CLK_MOUT_SCLK_ISP_UART 53 58 #define CLK_MOUT_SCLK_ISP_SPI1 54 59 #define CLK_MOUT_SCLK_ISP_SPI0 55 60 #define CLK_MOUT_SCLK_PCIE_100 56 61 #define CLK_MOUT_SCLK_UFSUNIPRO 57 62 #define CLK_MOUT_SCLK_USBHOST30 58 63 #define CLK_MOUT_SCLK_USBDRD30 59 64 #define CLK_MOUT_SCLK_SLIMBUS 60 65 #define CLK_MOUT_SCLK_SPDIF 61 66 #define CLK_MOUT_SCLK_AUDIO1 62 67 #define CLK_MOUT_SCLK_AUDIO0 63 68 #define CLK_MOUT_SCLK_HDMI_SPDIF 64 69 70 #define CLK_DIV_ACLK_FSYS_200 100 71 #define CLK_DIV_ACLK_IMEM_SSSX_266 101 72 #define CLK_DIV_ACLK_IMEM_200 102 73 #define CLK_DIV_ACLK_IMEM_266 103 74 #define CLK_DIV_ACLK_PERIC_66_B 104 75 #define CLK_DIV_ACLK_PERIC_66_A 105 76 #define CLK_DIV_ACLK_PERIS_66_B 106 77 #define CLK_DIV_ACLK_PERIS_66_A 107 78 #define CLK_DIV_SCLK_MMC1_B 108 79 #define CLK_DIV_SCLK_MMC1_A 109 80 #define CLK_DIV_SCLK_MMC0_B 110 81 #define CLK_DIV_SCLK_MMC0_A 111 82 #define CLK_DIV_SCLK_MMC2_B 112 83 #define CLK_DIV_SCLK_MMC2_A 113 84 #define CLK_DIV_SCLK_SPI1_B 114 85 #define CLK_DIV_SCLK_SPI1_A 115 86 #define CLK_DIV_SCLK_SPI0_B 116 87 #define CLK_DIV_SCLK_SPI0_A 117 88 #define CLK_DIV_SCLK_SPI2_B 118 89 #define CLK_DIV_SCLK_SPI2_A 119 90 #define CLK_DIV_SCLK_UART2 120 91 #define CLK_DIV_SCLK_UART1 121 92 #define CLK_DIV_SCLK_UART0 122 93 #define CLK_DIV_SCLK_SPI4_B 123 94 #define CLK_DIV_SCLK_SPI4_A 124 95 #define CLK_DIV_SCLK_SPI3_B 125 96 #define CLK_DIV_SCLK_SPI3_A 126 97 #define CLK_DIV_SCLK_I2S1 127 98 #define CLK_DIV_SCLK_PCM1 128 99 #define CLK_DIV_SCLK_AUDIO1 129 100 #define CLK_DIV_SCLK_AUDIO0 130 101 #define CLK_DIV_ACLK_GSCL_111 131 102 #define CLK_DIV_ACLK_GSCL_333 132 103 #define CLK_DIV_ACLK_HEVC_400 133 104 #define CLK_DIV_ACLK_MFC_400 134 105 #define CLK_DIV_ACLK_G2D_266 135 106 #define CLK_DIV_ACLK_G2D_400 136 107 #define CLK_DIV_ACLK_G3D_400 137 108 #define CLK_DIV_ACLK_BUS0_400 138 109 #define CLK_DIV_ACLK_BUS1_400 139 110 #define CLK_DIV_SCLK_PCIE_100 140 111 #define CLK_DIV_SCLK_USBHOST30 141 112 #define CLK_DIV_SCLK_UFSUNIPRO 142 113 #define CLK_DIV_SCLK_USBDRD30 143 114 #define CLK_DIV_SCLK_JPEG 144 115 #define CLK_DIV_ACLK_MSCL_400 145 116 #define CLK_DIV_ACLK_ISP_DIS_400 146 117 #define CLK_DIV_ACLK_ISP_400 147 118 #define CLK_DIV_ACLK_CAM0_333 148 119 #define CLK_DIV_ACLK_CAM0_400 149 120 #define CLK_DIV_ACLK_CAM0_552 150 121 #define CLK_DIV_ACLK_CAM1_333 151 122 #define CLK_DIV_ACLK_CAM1_400 152 123 #define CLK_DIV_ACLK_CAM1_552 153 124 #define CLK_DIV_SCLK_ISP_UART 154 125 #define CLK_DIV_SCLK_ISP_SPI1_B 155 126 #define CLK_DIV_SCLK_ISP_SPI1_A 156 127 #define CLK_DIV_SCLK_ISP_SPI0_B 157 128 #define CLK_DIV_SCLK_ISP_SPI0_A 158 129 #define CLK_DIV_SCLK_ISP_SENSOR2_B 159 130 #define CLK_DIV_SCLK_ISP_SENSOR2_A 160 131 #define CLK_DIV_SCLK_ISP_SENSOR1_B 161 132 #define CLK_DIV_SCLK_ISP_SENSOR1_A 162 133 #define CLK_DIV_SCLK_ISP_SENSOR0_B 163 134 #define CLK_DIV_SCLK_ISP_SENSOR0_A 164 135 136 #define CLK_ACLK_PERIC_66 200 137 #define CLK_ACLK_PERIS_66 201 138 #define CLK_ACLK_FSYS_200 202 139 #define CLK_SCLK_MMC2_FSYS 203 140 #define CLK_SCLK_MMC1_FSYS 204 141 #define CLK_SCLK_MMC0_FSYS 205 142 #define CLK_SCLK_SPI4_PERIC 206 143 #define CLK_SCLK_SPI3_PERIC 207 144 #define CLK_SCLK_UART2_PERIC 208 145 #define CLK_SCLK_UART1_PERIC 209 146 #define CLK_SCLK_UART0_PERIC 210 147 #define CLK_SCLK_SPI2_PERIC 211 148 #define CLK_SCLK_SPI1_PERIC 212 149 #define CLK_SCLK_SPI0_PERIC 213 150 #define CLK_SCLK_SPDIF_PERIC 214 151 #define CLK_SCLK_I2S1_PERIC 215 152 #define CLK_SCLK_PCM1_PERIC 216 153 #define CLK_SCLK_SLIMBUS 217 154 #define CLK_SCLK_AUDIO1 218 155 #define CLK_SCLK_AUDIO0 219 156 #define CLK_ACLK_G2D_266 220 157 #define CLK_ACLK_G2D_400 221 158 #define CLK_ACLK_G3D_400 222 159 #define CLK_ACLK_IMEM_SSSX_266 223 160 #define CLK_ACLK_BUS0_400 224 161 #define CLK_ACLK_BUS1_400 225 162 #define CLK_ACLK_IMEM_200 226 163 #define CLK_ACLK_IMEM_266 227 164 #define CLK_SCLK_PCIE_100_FSYS 228 165 #define CLK_SCLK_UFSUNIPRO_FSYS 229 166 #define CLK_SCLK_USBHOST30_FSYS 230 167 #define CLK_SCLK_USBDRD30_FSYS 231 168 #define CLK_ACLK_GSCL_111 232 169 #define CLK_ACLK_GSCL_333 233 170 #define CLK_SCLK_JPEG_MSCL 234 171 #define CLK_ACLK_MSCL_400 235 172 #define CLK_ACLK_MFC_400 236 173 #define CLK_ACLK_HEVC_400 237 174 #define CLK_ACLK_ISP_DIS_400 238 175 #define CLK_ACLK_ISP_400 239 176 #define CLK_ACLK_CAM0_333 240 177 #define CLK_ACLK_CAM0_400 241 178 #define CLK_ACLK_CAM0_552 242 179 #define CLK_ACLK_CAM1_333 243 180 #define CLK_ACLK_CAM1_400 244 181 #define CLK_ACLK_CAM1_552 245 182 #define CLK_SCLK_ISP_SENSOR2 246 183 #define CLK_SCLK_ISP_SENSOR1 247 184 #define CLK_SCLK_ISP_SENSOR0 248 185 #define CLK_SCLK_ISP_MCTADC_CAM1 249 186 #define CLK_SCLK_ISP_UART_CAM1 250 187 #define CLK_SCLK_ISP_SPI1_CAM1 251 188 #define CLK_SCLK_ISP_SPI0_CAM1 252 189 #define CLK_SCLK_HDMI_SPDIF_DISP 253 190 191 /* CMU_CPIF */ 192 #define CLK_FOUT_MPHY_PLL 1 193 194 #define CLK_MOUT_MPHY_PLL 2 195 196 #define CLK_DIV_SCLK_MPHY 10 197 198 #define CLK_SCLK_MPHY_PLL 11 199 #define CLK_SCLK_UFS_MPHY 11 200 201 /* CMU_MIF */ 202 #define CLK_FOUT_MEM0_PLL 1 203 #define CLK_FOUT_MEM1_PLL 2 204 #define CLK_FOUT_BUS_PLL 3 205 #define CLK_FOUT_MFC_PLL 4 206 #define CLK_DOUT_MFC_PLL 5 207 #define CLK_DOUT_BUS_PLL 6 208 #define CLK_DOUT_MEM1_PLL 7 209 #define CLK_DOUT_MEM0_PLL 8 210 211 #define CLK_MOUT_MFC_PLL_DIV2 10 212 #define CLK_MOUT_BUS_PLL_DIV2 11 213 #define CLK_MOUT_MEM1_PLL_DIV2 12 214 #define CLK_MOUT_MEM0_PLL_DIV2 13 215 #define CLK_MOUT_MFC_PLL 14 216 #define CLK_MOUT_BUS_PLL 15 217 #define CLK_MOUT_MEM1_PLL 16 218 #define CLK_MOUT_MEM0_PLL 17 219 #define CLK_MOUT_CLK2X_PHY_C 18 220 #define CLK_MOUT_CLK2X_PHY_B 19 221 #define CLK_MOUT_CLK2X_PHY_A 20 222 #define CLK_MOUT_CLKM_PHY_C 21 223 #define CLK_MOUT_CLKM_PHY_B 22 224 #define CLK_MOUT_CLKM_PHY_A 23 225 #define CLK_MOUT_ACLK_MIFNM_200 24 226 #define CLK_MOUT_ACLK_MIFNM_400 25 227 #define CLK_MOUT_ACLK_DISP_333_B 26 228 #define CLK_MOUT_ACLK_DISP_333_A 27 229 #define CLK_MOUT_SCLK_DECON_VCLK_C 28 230 #define CLK_MOUT_SCLK_DECON_VCLK_B 29 231 #define CLK_MOUT_SCLK_DECON_VCLK_A 30 232 #define CLK_MOUT_SCLK_DECON_ECLK_C 31 233 #define CLK_MOUT_SCLK_DECON_ECLK_B 32 234 #define CLK_MOUT_SCLK_DECON_ECLK_A 33 235 #define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34 236 #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35 237 #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36 238 #define CLK_MOUT_SCLK_DSD_C 37 239 #define CLK_MOUT_SCLK_DSD_B 38 240 #define CLK_MOUT_SCLK_DSD_A 39 241 #define CLK_MOUT_SCLK_DSIM0_C 40 242 #define CLK_MOUT_SCLK_DSIM0_B 41 243 #define CLK_MOUT_SCLK_DSIM0_A 42 244 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46 245 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47 246 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48 247 #define CLK_MOUT_SCLK_DSIM1_C 49 248 #define CLK_MOUT_SCLK_DSIM1_B 50 249 #define CLK_MOUT_SCLK_DSIM1_A 51 250 251 #define CLK_DIV_SCLK_HPM_MIF 55 252 #define CLK_DIV_ACLK_DREX1 56 253 #define CLK_DIV_ACLK_DREX0 57 254 #define CLK_DIV_CLK2XPHY 58 255 #define CLK_DIV_ACLK_MIF_266 59 256 #define CLK_DIV_ACLK_MIFND_133 60 257 #define CLK_DIV_ACLK_MIF_133 61 258 #define CLK_DIV_ACLK_MIFNM_200 62 259 #define CLK_DIV_ACLK_MIF_200 63 260 #define CLK_DIV_ACLK_MIF_400 64 261 #define CLK_DIV_ACLK_BUS2_400 65 262 #define CLK_DIV_ACLK_DISP_333 66 263 #define CLK_DIV_ACLK_CPIF_200 67 264 #define CLK_DIV_SCLK_DSIM1 68 265 #define CLK_DIV_SCLK_DECON_TV_VCLK 69 266 #define CLK_DIV_SCLK_DSIM0 70 267 #define CLK_DIV_SCLK_DSD 71 268 #define CLK_DIV_SCLK_DECON_TV_ECLK 72 269 #define CLK_DIV_SCLK_DECON_VCLK 73 270 #define CLK_DIV_SCLK_DECON_ECLK 74 271 #define CLK_DIV_MIF_PRE 75 272 273 #define CLK_CLK2X_PHY1 80 274 #define CLK_CLK2X_PHY0 81 275 #define CLK_CLKM_PHY1 82 276 #define CLK_CLKM_PHY0 83 277 #define CLK_RCLK_DREX1 84 278 #define CLK_RCLK_DREX0 85 279 #define CLK_ACLK_DREX1_TZ 86 280 #define CLK_ACLK_DREX0_TZ 87 281 #define CLK_ACLK_DREX1_PEREV 88 282 #define CLK_ACLK_DREX0_PEREV 89 283 #define CLK_ACLK_DREX1_MEMIF 90 284 #define CLK_ACLK_DREX0_MEMIF 91 285 #define CLK_ACLK_DREX1_SCH 92 286 #define CLK_ACLK_DREX0_SCH 93 287 #define CLK_ACLK_DREX1_BUSIF 94 288 #define CLK_ACLK_DREX0_BUSIF 95 289 #define CLK_ACLK_DREX1_BUSIF_RD 96 290 #define CLK_ACLK_DREX0_BUSIF_RD 97 291 #define CLK_ACLK_DREX1 98 292 #define CLK_ACLK_DREX0 99 293 #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100 294 #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101 295 #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102 296 #define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103 297 #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104 298 #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105 299 #define CLK_ACLK_ASYNCAXIS_CP1 106 300 #define CLK_ACLK_ASYNCAXIM_CP1 107 301 #define CLK_ACLK_ASYNCAXIS_CP0 108 302 #define CLK_ACLK_ASYNCAXIM_CP0 109 303 #define CLK_ACLK_ASYNCAXIS_DREX1_3 110 304 #define CLK_ACLK_ASYNCAXIM_DREX1_3 111 305 #define CLK_ACLK_ASYNCAXIS_DREX1_1 112 306 #define CLK_ACLK_ASYNCAXIM_DREX1_1 113 307 #define CLK_ACLK_ASYNCAXIS_DREX1_0 114 308 #define CLK_ACLK_ASYNCAXIM_DREX1_0 115 309 #define CLK_ACLK_ASYNCAXIS_DREX0_3 116 310 #define CLK_ACLK_ASYNCAXIM_DREX0_3 117 311 #define CLK_ACLK_ASYNCAXIS_DREX0_1 118 312 #define CLK_ACLK_ASYNCAXIM_DREX0_1 119 313 #define CLK_ACLK_ASYNCAXIS_DREX0_0 120 314 #define CLK_ACLK_ASYNCAXIM_DREX0_0 121 315 #define CLK_ACLK_AHB2APB_MIF2P 122 316 #define CLK_ACLK_AHB2APB_MIF1P 123 317 #define CLK_ACLK_AHB2APB_MIF0P 124 318 #define CLK_ACLK_IXIU_CCI 125 319 #define CLK_ACLK_XIU_MIFSFRX 126 320 #define CLK_ACLK_MIFNP_133 127 321 #define CLK_ACLK_MIFNM_200 128 322 #define CLK_ACLK_MIFND_133 129 323 #define CLK_ACLK_MIFND_400 130 324 #define CLK_ACLK_CCI 131 325 #define CLK_ACLK_MIFND_266 132 326 #define CLK_ACLK_PPMU_DREX1S3 133 327 #define CLK_ACLK_PPMU_DREX1S1 134 328 #define CLK_ACLK_PPMU_DREX1S0 135 329 #define CLK_ACLK_PPMU_DREX0S3 136 330 #define CLK_ACLK_PPMU_DREX0S1 137 331 #define CLK_ACLK_PPMU_DREX0S0 138 332 #define CLK_ACLK_BTS_APOLLO 139 333 #define CLK_ACLK_BTS_ATLAS 140 334 #define CLK_ACLK_ACE_SEL_APOLL 141 335 #define CLK_ACLK_ACE_SEL_ATLAS 142 336 #define CLK_ACLK_AXIDS_CCI_MIFSFRX 143 337 #define CLK_ACLK_AXIUS_ATLAS_CCI 144 338 #define CLK_ACLK_AXISYNCDNS_CCI 145 339 #define CLK_ACLK_AXISYNCDN_CCI 146 340 #define CLK_ACLK_AXISYNCDN_NOC_D 147 341 #define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148 342 #define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149 343 #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150 344 #define CLK_ACLK_BUS2_400 151 345 #define CLK_ACLK_DISP_333 152 346 #define CLK_ACLK_CPIF_200 153 347 #define CLK_PCLK_PPMU_DREX1S3 154 348 #define CLK_PCLK_PPMU_DREX1S1 155 349 #define CLK_PCLK_PPMU_DREX1S0 156 350 #define CLK_PCLK_PPMU_DREX0S3 157 351 #define CLK_PCLK_PPMU_DREX0S1 158 352 #define CLK_PCLK_PPMU_DREX0S0 159 353 #define CLK_PCLK_BTS_APOLLO 160 354 #define CLK_PCLK_BTS_ATLAS 161 355 #define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162 356 #define CLK_PCLK_ASYNCAXI_CP1 163 357 #define CLK_PCLK_ASYNCAXI_CP0 164 358 #define CLK_PCLK_ASYNCAXI_DREX1_3 165 359 #define CLK_PCLK_ASYNCAXI_DREX1_1 166 360 #define CLK_PCLK_ASYNCAXI_DREX1_0 167 361 #define CLK_PCLK_ASYNCAXI_DREX0_3 168 362 #define CLK_PCLK_ASYNCAXI_DREX0_1 169 363 #define CLK_PCLK_ASYNCAXI_DREX0_0 170 364 #define CLK_PCLK_MIFSRVND_133 171 365 #define CLK_PCLK_PMU_MIF 172 366 #define CLK_PCLK_SYSREG_MIF 173 367 #define CLK_PCLK_GPIO_ALIVE 174 368 #define CLK_PCLK_ABB 175 369 #define CLK_PCLK_PMU_APBIF 176 370 #define CLK_PCLK_DDR_PHY1 177 371 #define CLK_PCLK_DREX1 178 372 #define CLK_PCLK_DDR_PHY0 179 373 #define CLK_PCLK_DREX0 180 374 #define CLK_PCLK_DREX0_TZ 181 375 #define CLK_PCLK_DREX1_TZ 182 376 #define CLK_PCLK_MONOTONIC_CNT 183 377 #define CLK_PCLK_RTC 184 378 #define CLK_SCLK_DSIM1_DISP 185 379 #define CLK_SCLK_DECON_TV_VCLK_DISP 186 380 #define CLK_SCLK_FREQ_DET_BUS_PLL 187 381 #define CLK_SCLK_FREQ_DET_MFC_PLL 188 382 #define CLK_SCLK_FREQ_DET_MEM0_PLL 189 383 #define CLK_SCLK_FREQ_DET_MEM1_PLL 190 384 #define CLK_SCLK_DSIM0_DISP 191 385 #define CLK_SCLK_DSD_DISP 192 386 #define CLK_SCLK_DECON_TV_ECLK_DISP 193 387 #define CLK_SCLK_DECON_VCLK_DISP 194 388 #define CLK_SCLK_DECON_ECLK_DISP 195 389 #define CLK_SCLK_HPM_MIF 196 390 #define CLK_SCLK_MFC_PLL 197 391 #define CLK_SCLK_BUS_PLL 198 392 #define CLK_SCLK_BUS_PLL_APOLLO 199 393 #define CLK_SCLK_BUS_PLL_ATLAS 200 394 395 /* CMU_PERIC */ 396 #define CLK_PCLK_SPI2 1 397 #define CLK_PCLK_SPI1 2 398 #define CLK_PCLK_SPI0 3 399 #define CLK_PCLK_UART2 4 400 #define CLK_PCLK_UART1 5 401 #define CLK_PCLK_UART0 6 402 #define CLK_PCLK_HSI2C3 7 403 #define CLK_PCLK_HSI2C2 8 404 #define CLK_PCLK_HSI2C1 9 405 #define CLK_PCLK_HSI2C0 10 406 #define CLK_PCLK_I2C7 11 407 #define CLK_PCLK_I2C6 12 408 #define CLK_PCLK_I2C5 13 409 #define CLK_PCLK_I2C4 14 410 #define CLK_PCLK_I2C3 15 411 #define CLK_PCLK_I2C2 16 412 #define CLK_PCLK_I2C1 17 413 #define CLK_PCLK_I2C0 18 414 #define CLK_PCLK_SPI4 19 415 #define CLK_PCLK_SPI3 20 416 #define CLK_PCLK_HSI2C11 21 417 #define CLK_PCLK_HSI2C10 22 418 #define CLK_PCLK_HSI2C9 23 419 #define CLK_PCLK_HSI2C8 24 420 #define CLK_PCLK_HSI2C7 25 421 #define CLK_PCLK_HSI2C6 26 422 #define CLK_PCLK_HSI2C5 27 423 #define CLK_PCLK_HSI2C4 28 424 #define CLK_SCLK_SPI4 29 425 #define CLK_SCLK_SPI3 30 426 #define CLK_SCLK_SPI2 31 427 #define CLK_SCLK_SPI1 32 428 #define CLK_SCLK_SPI0 33 429 #define CLK_SCLK_UART2 34 430 #define CLK_SCLK_UART1 35 431 #define CLK_SCLK_UART0 36 432 #define CLK_ACLK_AHB2APB_PERIC2P 37 433 #define CLK_ACLK_AHB2APB_PERIC1P 38 434 #define CLK_ACLK_AHB2APB_PERIC0P 39 435 #define CLK_ACLK_PERICNP_66 40 436 #define CLK_PCLK_SCI 41 437 #define CLK_PCLK_GPIO_FINGER 42 438 #define CLK_PCLK_GPIO_ESE 43 439 #define CLK_PCLK_PWM 44 440 #define CLK_PCLK_SPDIF 45 441 #define CLK_PCLK_PCM1 46 442 #define CLK_PCLK_I2S1 47 443 #define CLK_PCLK_ADCIF 48 444 #define CLK_PCLK_GPIO_TOUCH 49 445 #define CLK_PCLK_GPIO_NFC 50 446 #define CLK_PCLK_GPIO_PERIC 51 447 #define CLK_PCLK_PMU_PERIC 52 448 #define CLK_PCLK_SYSREG_PERIC 53 449 #define CLK_SCLK_IOCLK_SPI4 54 450 #define CLK_SCLK_IOCLK_SPI3 55 451 #define CLK_SCLK_SCI 56 452 #define CLK_SCLK_SC_IN 57 453 #define CLK_SCLK_PWM 58 454 #define CLK_SCLK_IOCLK_SPI2 59 455 #define CLK_SCLK_IOCLK_SPI1 60 456 #define CLK_SCLK_IOCLK_SPI0 61 457 #define CLK_SCLK_IOCLK_I2S1_BCLK 62 458 #define CLK_SCLK_SPDIF 63 459 #define CLK_SCLK_PCM1 64 460 #define CLK_SCLK_I2S1 65 461 462 #define CLK_DIV_SCLK_SCI 70 463 #define CLK_DIV_SCLK_SC_IN 71 464 465 /* CMU_PERIS */ 466 #define CLK_PCLK_HPM_APBIF 1 467 #define CLK_PCLK_TMU1_APBIF 2 468 #define CLK_PCLK_TMU0_APBIF 3 469 #define CLK_PCLK_PMU_PERIS 4 470 #define CLK_PCLK_SYSREG_PERIS 5 471 #define CLK_PCLK_CMU_TOP_APBIF 6 472 #define CLK_PCLK_WDT_APOLLO 7 473 #define CLK_PCLK_WDT_ATLAS 8 474 #define CLK_PCLK_MCT 9 475 #define CLK_PCLK_HDMI_CEC 10 476 #define CLK_ACLK_AHB2APB_PERIS1P 11 477 #define CLK_ACLK_AHB2APB_PERIS0P 12 478 #define CLK_ACLK_PERISNP_66 13 479 #define CLK_PCLK_TZPC12 14 480 #define CLK_PCLK_TZPC11 15 481 #define CLK_PCLK_TZPC10 16 482 #define CLK_PCLK_TZPC9 17 483 #define CLK_PCLK_TZPC8 18 484 #define CLK_PCLK_TZPC7 19 485 #define CLK_PCLK_TZPC6 20 486 #define CLK_PCLK_TZPC5 21 487 #define CLK_PCLK_TZPC4 22 488 #define CLK_PCLK_TZPC3 23 489 #define CLK_PCLK_TZPC2 24 490 #define CLK_PCLK_TZPC1 25 491 #define CLK_PCLK_TZPC0 26 492 #define CLK_PCLK_SECKEY_APBIF 27 493 #define CLK_PCLK_CHIPID_APBIF 28 494 #define CLK_PCLK_TOPRTC 29 495 #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 496 #define CLK_PCLK_ANTIRBK_CNT_APBIF 31 497 #define CLK_PCLK_OTP_CON_APBIF 32 498 #define CLK_SCLK_ASV_TB 33 499 #define CLK_SCLK_TMU1 34 500 #define CLK_SCLK_TMU0 35 501 #define CLK_SCLK_SECKEY 36 502 #define CLK_SCLK_CHIPID 37 503 #define CLK_SCLK_TOPRTC 38 504 #define CLK_SCLK_CUSTOM_EFUSE 39 505 #define CLK_SCLK_ANTIRBK_CNT 40 506 #define CLK_SCLK_OTP_CON 41 507 508 /* CMU_FSYS */ 509 #define CLK_MOUT_ACLK_FSYS_200_USER 1 510 #define CLK_MOUT_SCLK_MMC2_USER 2 511 #define CLK_MOUT_SCLK_MMC1_USER 3 512 #define CLK_MOUT_SCLK_MMC0_USER 4 513 #define CLK_MOUT_SCLK_UFS_MPHY_USER 5 514 #define CLK_MOUT_SCLK_PCIE_100_USER 6 515 #define CLK_MOUT_SCLK_UFSUNIPRO_USER 7 516 #define CLK_MOUT_SCLK_USBHOST30_USER 8 517 #define CLK_MOUT_SCLK_USBDRD30_USER 9 518 #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10 519 #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11 520 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12 521 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13 522 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14 523 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15 524 #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16 525 #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17 526 #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18 527 #define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19 528 #define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20 529 #define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21 530 #define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22 531 #define CLK_MOUT_SCLK_MPHY 23 532 533 #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25 534 #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26 535 #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27 536 #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28 537 #define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29 538 #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30 539 #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31 540 #define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32 541 #define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33 542 #define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34 543 #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35 544 #define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36 545 #define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37 546 547 #define CLK_ACLK_PCIE 50 548 #define CLK_ACLK_PDMA1 51 549 #define CLK_ACLK_TSI 52 550 #define CLK_ACLK_MMC2 53 551 #define CLK_ACLK_MMC1 54 552 #define CLK_ACLK_MMC0 55 553 #define CLK_ACLK_UFS 56 554 #define CLK_ACLK_USBHOST20 57 555 #define CLK_ACLK_USBHOST30 58 556 #define CLK_ACLK_USBDRD30 59 557 #define CLK_ACLK_PDMA0 60 558 #define CLK_SCLK_MMC2 61 559 #define CLK_SCLK_MMC1 62 560 #define CLK_SCLK_MMC0 63 561 #define CLK_PDMA1 64 562 #define CLK_PDMA0 65 563 #define CLK_ACLK_XIU_FSYSPX 66 564 #define CLK_ACLK_AHB_USBLINKH1 67 565 #define CLK_ACLK_SMMU_PDMA1 68 566 #define CLK_ACLK_BTS_PCIE 69 567 #define CLK_ACLK_AXIUS_PDMA1 70 568 #define CLK_ACLK_SMMU_PDMA0 71 569 #define CLK_ACLK_BTS_UFS 72 570 #define CLK_ACLK_BTS_USBHOST30 73 571 #define CLK_ACLK_BTS_USBDRD30 74 572 #define CLK_ACLK_AXIUS_PDMA0 75 573 #define CLK_ACLK_AXIUS_USBHS 76 574 #define CLK_ACLK_AXIUS_FSYSSX 77 575 #define CLK_ACLK_AHB2APB_FSYSP 78 576 #define CLK_ACLK_AHB2AXI_USBHS 79 577 #define CLK_ACLK_AHB_USBLINKH0 80 578 #define CLK_ACLK_AHB_USBHS 81 579 #define CLK_ACLK_AHB_FSYSH 82 580 #define CLK_ACLK_XIU_FSYSX 83 581 #define CLK_ACLK_XIU_FSYSSX 84 582 #define CLK_ACLK_FSYSNP_200 85 583 #define CLK_ACLK_FSYSND_200 86 584 #define CLK_PCLK_PCIE_CTRL 87 585 #define CLK_PCLK_SMMU_PDMA1 88 586 #define CLK_PCLK_PCIE_PHY 89 587 #define CLK_PCLK_BTS_PCIE 90 588 #define CLK_PCLK_SMMU_PDMA0 91 589 #define CLK_PCLK_BTS_UFS 92 590 #define CLK_PCLK_BTS_USBHOST30 93 591 #define CLK_PCLK_BTS_USBDRD30 94 592 #define CLK_PCLK_GPIO_FSYS 95 593 #define CLK_PCLK_PMU_FSYS 96 594 #define CLK_PCLK_SYSREG_FSYS 97 595 #define CLK_SCLK_PCIE_100 98 596 #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99 597 #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100 598 #define CLK_PHYCLK_UFS_RX1_SYMBOL 101 599 #define CLK_PHYCLK_UFS_RX0_SYMBOL 102 600 #define CLK_PHYCLK_UFS_TX1_SYMBOL 103 601 #define CLK_PHYCLK_UFS_TX0_SYMBOL 104 602 #define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105 603 #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106 604 #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107 605 #define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108 606 #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109 607 #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110 608 #define CLK_SCLK_MPHY 111 609 #define CLK_SCLK_UFSUNIPRO 112 610 #define CLK_SCLK_USBHOST30 113 611 #define CLK_SCLK_USBDRD30 114 612 #define CLK_PCIE 115 613 614 /* CMU_G2D */ 615 #define CLK_MUX_ACLK_G2D_266_USER 1 616 #define CLK_MUX_ACLK_G2D_400_USER 2 617 618 #define CLK_DIV_PCLK_G2D 3 619 620 #define CLK_ACLK_SMMU_MDMA1 4 621 #define CLK_ACLK_BTS_MDMA1 5 622 #define CLK_ACLK_BTS_G2D 6 623 #define CLK_ACLK_ALB_G2D 7 624 #define CLK_ACLK_AXIUS_G2DX 8 625 #define CLK_ACLK_ASYNCAXI_SYSX 9 626 #define CLK_ACLK_AHB2APB_G2D1P 10 627 #define CLK_ACLK_AHB2APB_G2D0P 11 628 #define CLK_ACLK_XIU_G2DX 12 629 #define CLK_ACLK_G2DNP_133 13 630 #define CLK_ACLK_G2DND_400 14 631 #define CLK_ACLK_MDMA1 15 632 #define CLK_ACLK_G2D 16 633 #define CLK_ACLK_SMMU_G2D 17 634 #define CLK_PCLK_SMMU_MDMA1 18 635 #define CLK_PCLK_BTS_MDMA1 19 636 #define CLK_PCLK_BTS_G2D 20 637 #define CLK_PCLK_ALB_G2D 21 638 #define CLK_PCLK_ASYNCAXI_SYSX 22 639 #define CLK_PCLK_PMU_G2D 23 640 #define CLK_PCLK_SYSREG_G2D 24 641 #define CLK_PCLK_G2D 25 642 #define CLK_PCLK_SMMU_G2D 26 643 644 /* CMU_DISP */ 645 #define CLK_FOUT_DISP_PLL 1 646 647 #define CLK_MOUT_DISP_PLL 2 648 #define CLK_MOUT_SCLK_DSIM1_USER 3 649 #define CLK_MOUT_SCLK_DSIM0_USER 4 650 #define CLK_MOUT_SCLK_DSD_USER 5 651 #define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6 652 #define CLK_MOUT_SCLK_DECON_VCLK_USER 7 653 #define CLK_MOUT_SCLK_DECON_ECLK_USER 8 654 #define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9 655 #define CLK_MOUT_ACLK_DISP_333_USER 10 656 #define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11 657 #define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12 658 #define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13 659 #define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14 660 #define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15 661 #define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16 662 #define CLK_MOUT_SCLK_DSIM0 17 663 #define CLK_MOUT_SCLK_DECON_TV_ECLK 18 664 #define CLK_MOUT_SCLK_DECON_VCLK 19 665 #define CLK_MOUT_SCLK_DECON_ECLK 20 666 #define CLK_MOUT_SCLK_DSIM1_B_DISP 21 667 #define CLK_MOUT_SCLK_DSIM1_A_DISP 22 668 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23 669 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24 670 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25 671 672 #define CLK_DIV_SCLK_DSIM1_DISP 30 673 #define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31 674 #define CLK_DIV_SCLK_DSIM0_DISP 32 675 #define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33 676 #define CLK_DIV_SCLK_DECON_VCLK_DISP 34 677 #define CLK_DIV_SCLK_DECON_ECLK_DISP 35 678 #define CLK_DIV_PCLK_DISP 36 679 680 #define CLK_ACLK_DECON_TV 40 681 #define CLK_ACLK_DECON 41 682 #define CLK_ACLK_SMMU_TV1X 42 683 #define CLK_ACLK_SMMU_TV0X 43 684 #define CLK_ACLK_SMMU_DECON1X 44 685 #define CLK_ACLK_SMMU_DECON0X 45 686 #define CLK_ACLK_BTS_DECON_TV_M3 46 687 #define CLK_ACLK_BTS_DECON_TV_M2 47 688 #define CLK_ACLK_BTS_DECON_TV_M1 48 689 #define CLK_ACLK_BTS_DECON_TV_M0 49 690 #define CLK_ACLK_BTS_DECON_NM4 50 691 #define CLK_ACLK_BTS_DECON_NM3 51 692 #define CLK_ACLK_BTS_DECON_NM2 52 693 #define CLK_ACLK_BTS_DECON_NM1 53 694 #define CLK_ACLK_BTS_DECON_NM0 54 695 #define CLK_ACLK_AHB2APB_DISPSFR2P 55 696 #define CLK_ACLK_AHB2APB_DISPSFR1P 56 697 #define CLK_ACLK_AHB2APB_DISPSFR0P 57 698 #define CLK_ACLK_AHB_DISPH 58 699 #define CLK_ACLK_XIU_TV1X 59 700 #define CLK_ACLK_XIU_TV0X 60 701 #define CLK_ACLK_XIU_DECON1X 61 702 #define CLK_ACLK_XIU_DECON0X 62 703 #define CLK_ACLK_XIU_DISP1X 63 704 #define CLK_ACLK_XIU_DISPNP_100 64 705 #define CLK_ACLK_DISP1ND_333 65 706 #define CLK_ACLK_DISP0ND_333 66 707 #define CLK_PCLK_SMMU_TV1X 67 708 #define CLK_PCLK_SMMU_TV0X 68 709 #define CLK_PCLK_SMMU_DECON1X 69 710 #define CLK_PCLK_SMMU_DECON0X 70 711 #define CLK_PCLK_BTS_DECON_TV_M3 71 712 #define CLK_PCLK_BTS_DECON_TV_M2 72 713 #define CLK_PCLK_BTS_DECON_TV_M1 73 714 #define CLK_PCLK_BTS_DECON_TV_M0 74 715 #define CLK_PCLK_BTS_DECONM4 75 716 #define CLK_PCLK_BTS_DECONM3 76 717 #define CLK_PCLK_BTS_DECONM2 77 718 #define CLK_PCLK_BTS_DECONM1 78 719 #define CLK_PCLK_BTS_DECONM0 79 720 #define CLK_PCLK_MIC1 80 721 #define CLK_PCLK_PMU_DISP 81 722 #define CLK_PCLK_SYSREG_DISP 82 723 #define CLK_PCLK_HDMIPHY 83 724 #define CLK_PCLK_HDMI 84 725 #define CLK_PCLK_MIC0 85 726 #define CLK_PCLK_DSIM1 86 727 #define CLK_PCLK_DSIM0 87 728 #define CLK_PCLK_DECON_TV 88 729 #define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89 730 #define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90 731 #define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91 732 #define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92 733 #define CLK_SCLK_DSIM1 93 734 #define CLK_SCLK_DECON_TV_VCLK 94 735 #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95 736 #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96 737 #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97 738 #define CLK_PHYCLK_HDMI_PIXEL 98 739 #define CLK_SCLK_RGB_VCLK_TO_SMIES 99 740 #define CLK_SCLK_FREQ_DET_DISP_PLL 100 741 #define CLK_SCLK_RGB_VCLK_TO_DSIM0 101 742 #define CLK_SCLK_RGB_VCLK_TO_MIC0 102 743 #define CLK_SCLK_DSD 103 744 #define CLK_SCLK_HDMI_SPDIF 104 745 #define CLK_SCLK_DSIM0 105 746 #define CLK_SCLK_DECON_TV_ECLK 106 747 #define CLK_SCLK_DECON_VCLK 107 748 #define CLK_SCLK_DECON_ECLK 108 749 #define CLK_SCLK_RGB_VCLK 109 750 #define CLK_SCLK_RGB_TV_VCLK 110 751 752 #define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY 111 753 #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY 112 754 755 #define CLK_PCLK_DECON 113 756 757 #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114 758 #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115 759 760 /* CMU_AUD */ 761 #define CLK_MOUT_AUD_PLL_USER 1 762 #define CLK_MOUT_SCLK_AUD_PCM 2 763 #define CLK_MOUT_SCLK_AUD_I2S 3 764 765 #define CLK_DIV_ATCLK_AUD 4 766 #define CLK_DIV_PCLK_DBG_AUD 5 767 #define CLK_DIV_ACLK_AUD 6 768 #define CLK_DIV_AUD_CA5 7 769 #define CLK_DIV_SCLK_AUD_SLIMBUS 8 770 #define CLK_DIV_SCLK_AUD_UART 9 771 #define CLK_DIV_SCLK_AUD_PCM 10 772 #define CLK_DIV_SCLK_AUD_I2S 11 773 774 #define CLK_ACLK_INTR_CTRL 12 775 #define CLK_ACLK_AXIDS2_LPASSP 13 776 #define CLK_ACLK_AXIDS1_LPASSP 14 777 #define CLK_ACLK_AXI2APB1_LPASSP 15 778 #define CLK_ACLK_AXI2APH_LPASSP 16 779 #define CLK_ACLK_SMMU_LPASSX 17 780 #define CLK_ACLK_AXIDS0_LPASSP 18 781 #define CLK_ACLK_AXI2APB0_LPASSP 19 782 #define CLK_ACLK_XIU_LPASSX 20 783 #define CLK_ACLK_AUDNP_133 21 784 #define CLK_ACLK_AUDND_133 22 785 #define CLK_ACLK_SRAMC 23 786 #define CLK_ACLK_DMAC 24 787 #define CLK_PCLK_WDT1 25 788 #define CLK_PCLK_WDT0 26 789 #define CLK_PCLK_SFR1 27 790 #define CLK_PCLK_SMMU_LPASSX 28 791 #define CLK_PCLK_GPIO_AUD 29 792 #define CLK_PCLK_PMU_AUD 30 793 #define CLK_PCLK_SYSREG_AUD 31 794 #define CLK_PCLK_AUD_SLIMBUS 32 795 #define CLK_PCLK_AUD_UART 33 796 #define CLK_PCLK_AUD_PCM 34 797 #define CLK_PCLK_AUD_I2S 35 798 #define CLK_PCLK_TIMER 36 799 #define CLK_PCLK_SFR0_CTRL 37 800 #define CLK_ATCLK_AUD 38 801 #define CLK_PCLK_DBG_AUD 39 802 #define CLK_SCLK_AUD_CA5 40 803 #define CLK_SCLK_JTAG_TCK 41 804 #define CLK_SCLK_SLIMBUS_CLKIN 42 805 #define CLK_SCLK_AUD_SLIMBUS 43 806 #define CLK_SCLK_AUD_UART 44 807 #define CLK_SCLK_AUD_PCM 45 808 #define CLK_SCLK_I2S_BCLK 46 809 #define CLK_SCLK_AUD_I2S 47 810 811 /* CMU_BUS{0|1|2} */ 812 #define CLK_DIV_PCLK_BUS_133 1 813 814 #define CLK_ACLK_AHB2APB_BUSP 2 815 #define CLK_ACLK_BUSNP_133 3 816 #define CLK_ACLK_BUSND_400 4 817 #define CLK_PCLK_BUSSRVND_133 5 818 #define CLK_PCLK_PMU_BUS 6 819 #define CLK_PCLK_SYSREG_BUS 7 820 821 #define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */ 822 #define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ 823 #define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ 824 825 /* CMU_G3D */ 826 #define CLK_FOUT_G3D_PLL 1 827 828 #define CLK_MOUT_ACLK_G3D_400 2 829 #define CLK_MOUT_G3D_PLL 3 830 831 #define CLK_DIV_SCLK_HPM_G3D 4 832 #define CLK_DIV_PCLK_G3D 5 833 #define CLK_DIV_ACLK_G3D 6 834 #define CLK_ACLK_BTS_G3D1 7 835 #define CLK_ACLK_BTS_G3D0 8 836 #define CLK_ACLK_ASYNCAPBS_G3D 9 837 #define CLK_ACLK_ASYNCAPBM_G3D 10 838 #define CLK_ACLK_AHB2APB_G3DP 11 839 #define CLK_ACLK_G3DNP_150 12 840 #define CLK_ACLK_G3DND_600 13 841 #define CLK_ACLK_G3D 14 842 #define CLK_PCLK_BTS_G3D1 15 843 #define CLK_PCLK_BTS_G3D0 16 844 #define CLK_PCLK_PMU_G3D 17 845 #define CLK_PCLK_SYSREG_G3D 18 846 #define CLK_SCLK_HPM_G3D 19 847 848 /* CMU_GSCL */ 849 #define CLK_MOUT_ACLK_GSCL_111_USER 1 850 #define CLK_MOUT_ACLK_GSCL_333_USER 2 851 852 #define CLK_ACLK_BTS_GSCL2 3 853 #define CLK_ACLK_BTS_GSCL1 4 854 #define CLK_ACLK_BTS_GSCL0 5 855 #define CLK_ACLK_AHB2APB_GSCLP 6 856 #define CLK_ACLK_XIU_GSCLX 7 857 #define CLK_ACLK_GSCLNP_111 8 858 #define CLK_ACLK_GSCLRTND_333 9 859 #define CLK_ACLK_GSCLBEND_333 10 860 #define CLK_ACLK_GSD 11 861 #define CLK_ACLK_GSCL2 12 862 #define CLK_ACLK_GSCL1 13 863 #define CLK_ACLK_GSCL0 14 864 #define CLK_ACLK_SMMU_GSCL0 15 865 #define CLK_ACLK_SMMU_GSCL1 16 866 #define CLK_ACLK_SMMU_GSCL2 17 867 #define CLK_PCLK_BTS_GSCL2 18 868 #define CLK_PCLK_BTS_GSCL1 19 869 #define CLK_PCLK_BTS_GSCL0 20 870 #define CLK_PCLK_PMU_GSCL 21 871 #define CLK_PCLK_SYSREG_GSCL 22 872 #define CLK_PCLK_GSCL2 23 873 #define CLK_PCLK_GSCL1 24 874 #define CLK_PCLK_GSCL0 25 875 #define CLK_PCLK_SMMU_GSCL0 26 876 #define CLK_PCLK_SMMU_GSCL1 27 877 #define CLK_PCLK_SMMU_GSCL2 28 878 879 /* CMU_APOLLO */ 880 #define CLK_FOUT_APOLLO_PLL 1 881 882 #define CLK_MOUT_APOLLO_PLL 2 883 #define CLK_MOUT_BUS_PLL_APOLLO_USER 3 884 #define CLK_MOUT_APOLLO 4 885 886 #define CLK_DIV_CNTCLK_APOLLO 5 887 #define CLK_DIV_PCLK_DBG_APOLLO 6 888 #define CLK_DIV_ATCLK_APOLLO 7 889 #define CLK_DIV_PCLK_APOLLO 8 890 #define CLK_DIV_ACLK_APOLLO 9 891 #define CLK_DIV_APOLLO2 10 892 #define CLK_DIV_APOLLO1 11 893 #define CLK_DIV_SCLK_HPM_APOLLO 12 894 #define CLK_DIV_APOLLO_PLL 13 895 896 #define CLK_ACLK_ATBDS_APOLLO_3 14 897 #define CLK_ACLK_ATBDS_APOLLO_2 15 898 #define CLK_ACLK_ATBDS_APOLLO_1 16 899 #define CLK_ACLK_ATBDS_APOLLO_0 17 900 #define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18 901 #define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19 902 #define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20 903 #define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21 904 #define CLK_ACLK_ASYNCACES_APOLLO_CCI 22 905 #define CLK_ACLK_AHB2APB_APOLLOP 23 906 #define CLK_ACLK_APOLLONP_200 24 907 #define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25 908 #define CLK_PCLK_PMU_APOLLO 26 909 #define CLK_PCLK_SYSREG_APOLLO 27 910 #define CLK_CNTCLK_APOLLO 28 911 #define CLK_SCLK_HPM_APOLLO 29 912 #define CLK_SCLK_APOLLO 30 913 914 /* CMU_ATLAS */ 915 #define CLK_FOUT_ATLAS_PLL 1 916 917 #define CLK_MOUT_ATLAS_PLL 2 918 #define CLK_MOUT_BUS_PLL_ATLAS_USER 3 919 #define CLK_MOUT_ATLAS 4 920 921 #define CLK_DIV_CNTCLK_ATLAS 5 922 #define CLK_DIV_PCLK_DBG_ATLAS 6 923 #define CLK_DIV_ATCLK_ATLASO 7 924 #define CLK_DIV_PCLK_ATLAS 8 925 #define CLK_DIV_ACLK_ATLAS 9 926 #define CLK_DIV_ATLAS2 10 927 #define CLK_DIV_ATLAS1 11 928 #define CLK_DIV_SCLK_HPM_ATLAS 12 929 #define CLK_DIV_ATLAS_PLL 13 930 931 #define CLK_ACLK_ATB_AUD_CSSYS 14 932 #define CLK_ACLK_ATB_APOLLO3_CSSYS 15 933 #define CLK_ACLK_ATB_APOLLO2_CSSYS 16 934 #define CLK_ACLK_ATB_APOLLO1_CSSYS 17 935 #define CLK_ACLK_ATB_APOLLO0_CSSYS 18 936 #define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19 937 #define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20 938 #define CLK_ACLK_ASYNCACES_ATLAS_CCI 21 939 #define CLK_ACLK_AHB2APB_ATLASP 22 940 #define CLK_ACLK_ATLASNP_200 23 941 #define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24 942 #define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25 943 #define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26 944 #define CLK_PCLK_PMU_ATLAS 27 945 #define CLK_PCLK_SYSREG_ATLAS 28 946 #define CLK_PCLK_SECJTAG 29 947 #define CLK_CNTCLK_ATLAS 30 948 #define CLK_SCLK_FREQ_DET_ATLAS_PLL 31 949 #define CLK_SCLK_HPM_ATLAS 32 950 #define CLK_TRACECLK 33 951 #define CLK_CTMCLK 34 952 #define CLK_HCLK_CSSYS 35 953 #define CLK_PCLK_DBG_CSSYS 36 954 #define CLK_PCLK_DBG 37 955 #define CLK_ATCLK 38 956 #define CLK_SCLK_ATLAS 39 957 958 /* CMU_MSCL */ 959 #define CLK_MOUT_SCLK_JPEG_USER 1 960 #define CLK_MOUT_ACLK_MSCL_400_USER 2 961 #define CLK_MOUT_SCLK_JPEG 3 962 963 #define CLK_DIV_PCLK_MSCL 4 964 965 #define CLK_ACLK_BTS_JPEG 5 966 #define CLK_ACLK_BTS_M2MSCALER1 6 967 #define CLK_ACLK_BTS_M2MSCALER0 7 968 #define CLK_ACLK_AHB2APB_MSCL0P 8 969 #define CLK_ACLK_XIU_MSCLX 9 970 #define CLK_ACLK_MSCLNP_100 10 971 #define CLK_ACLK_MSCLND_400 11 972 #define CLK_ACLK_JPEG 12 973 #define CLK_ACLK_M2MSCALER1 13 974 #define CLK_ACLK_M2MSCALER0 14 975 #define CLK_ACLK_SMMU_M2MSCALER0 15 976 #define CLK_ACLK_SMMU_M2MSCALER1 16 977 #define CLK_ACLK_SMMU_JPEG 17 978 #define CLK_PCLK_BTS_JPEG 18 979 #define CLK_PCLK_BTS_M2MSCALER1 19 980 #define CLK_PCLK_BTS_M2MSCALER0 20 981 #define CLK_PCLK_PMU_MSCL 21 982 #define CLK_PCLK_SYSREG_MSCL 22 983 #define CLK_PCLK_JPEG 23 984 #define CLK_PCLK_M2MSCALER1 24 985 #define CLK_PCLK_M2MSCALER0 25 986 #define CLK_PCLK_SMMU_M2MSCALER0 26 987 #define CLK_PCLK_SMMU_M2MSCALER1 27 988 #define CLK_PCLK_SMMU_JPEG 28 989 #define CLK_SCLK_JPEG 29 990 991 /* CMU_MFC */ 992 #define CLK_MOUT_ACLK_MFC_400_USER 1 993 994 #define CLK_DIV_PCLK_MFC 2 995 996 #define CLK_ACLK_BTS_MFC_1 3 997 #define CLK_ACLK_BTS_MFC_0 4 998 #define CLK_ACLK_AHB2APB_MFCP 5 999 #define CLK_ACLK_XIU_MFCX 6 1000 #define CLK_ACLK_MFCNP_100 7 1001 #define CLK_ACLK_MFCND_400 8 1002 #define CLK_ACLK_MFC 9 1003 #define CLK_ACLK_SMMU_MFC_1 10 1004 #define CLK_ACLK_SMMU_MFC_0 11 1005 #define CLK_PCLK_BTS_MFC_1 12 1006 #define CLK_PCLK_BTS_MFC_0 13 1007 #define CLK_PCLK_PMU_MFC 14 1008 #define CLK_PCLK_SYSREG_MFC 15 1009 #define CLK_PCLK_MFC 16 1010 #define CLK_PCLK_SMMU_MFC_1 17 1011 #define CLK_PCLK_SMMU_MFC_0 18 1012 1013 /* CMU_HEVC */ 1014 #define CLK_MOUT_ACLK_HEVC_400_USER 1 1015 1016 #define CLK_DIV_PCLK_HEVC 2 1017 1018 #define CLK_ACLK_BTS_HEVC_1 3 1019 #define CLK_ACLK_BTS_HEVC_0 4 1020 #define CLK_ACLK_AHB2APB_HEVCP 5 1021 #define CLK_ACLK_XIU_HEVCX 6 1022 #define CLK_ACLK_HEVCNP_100 7 1023 #define CLK_ACLK_HEVCND_400 8 1024 #define CLK_ACLK_HEVC 9 1025 #define CLK_ACLK_SMMU_HEVC_1 10 1026 #define CLK_ACLK_SMMU_HEVC_0 11 1027 #define CLK_PCLK_BTS_HEVC_1 12 1028 #define CLK_PCLK_BTS_HEVC_0 13 1029 #define CLK_PCLK_PMU_HEVC 14 1030 #define CLK_PCLK_SYSREG_HEVC 15 1031 #define CLK_PCLK_HEVC 16 1032 #define CLK_PCLK_SMMU_HEVC_1 17 1033 #define CLK_PCLK_SMMU_HEVC_0 18 1034 1035 /* CMU_ISP */ 1036 #define CLK_MOUT_ACLK_ISP_DIS_400_USER 1 1037 #define CLK_MOUT_ACLK_ISP_400_USER 2 1038 1039 #define CLK_DIV_PCLK_ISP_DIS 3 1040 #define CLK_DIV_PCLK_ISP 4 1041 #define CLK_DIV_ACLK_ISP_D_200 5 1042 #define CLK_DIV_ACLK_ISP_C_200 6 1043 1044 #define CLK_ACLK_ISP_D_GLUE 7 1045 #define CLK_ACLK_SCALERP 8 1046 #define CLK_ACLK_3DNR 9 1047 #define CLK_ACLK_DIS 10 1048 #define CLK_ACLK_SCALERC 11 1049 #define CLK_ACLK_DRC 12 1050 #define CLK_ACLK_ISP 13 1051 #define CLK_ACLK_AXIUS_SCALERP 14 1052 #define CLK_ACLK_AXIUS_SCALERC 15 1053 #define CLK_ACLK_AXIUS_DRC 16 1054 #define CLK_ACLK_ASYNCAHBM_ISP2P 17 1055 #define CLK_ACLK_ASYNCAHBM_ISP1P 18 1056 #define CLK_ACLK_ASYNCAXIS_DIS1 19 1057 #define CLK_ACLK_ASYNCAXIS_DIS0 20 1058 #define CLK_ACLK_ASYNCAXIM_DIS1 21 1059 #define CLK_ACLK_ASYNCAXIM_DIS0 22 1060 #define CLK_ACLK_ASYNCAXIM_ISP2P 23 1061 #define CLK_ACLK_ASYNCAXIM_ISP1P 24 1062 #define CLK_ACLK_AHB2APB_ISP2P 25 1063 #define CLK_ACLK_AHB2APB_ISP1P 26 1064 #define CLK_ACLK_AXI2APB_ISP2P 27 1065 #define CLK_ACLK_AXI2APB_ISP1P 28 1066 #define CLK_ACLK_XIU_ISPEX1 29 1067 #define CLK_ACLK_XIU_ISPEX0 30 1068 #define CLK_ACLK_ISPND_400 31 1069 #define CLK_ACLK_SMMU_SCALERP 32 1070 #define CLK_ACLK_SMMU_3DNR 33 1071 #define CLK_ACLK_SMMU_DIS1 34 1072 #define CLK_ACLK_SMMU_DIS0 35 1073 #define CLK_ACLK_SMMU_SCALERC 36 1074 #define CLK_ACLK_SMMU_DRC 37 1075 #define CLK_ACLK_SMMU_ISP 38 1076 #define CLK_ACLK_BTS_SCALERP 39 1077 #define CLK_ACLK_BTS_3DR 40 1078 #define CLK_ACLK_BTS_DIS1 41 1079 #define CLK_ACLK_BTS_DIS0 42 1080 #define CLK_ACLK_BTS_SCALERC 43 1081 #define CLK_ACLK_BTS_DRC 44 1082 #define CLK_ACLK_BTS_ISP 45 1083 #define CLK_PCLK_SMMU_SCALERP 46 1084 #define CLK_PCLK_SMMU_3DNR 47 1085 #define CLK_PCLK_SMMU_DIS1 48 1086 #define CLK_PCLK_SMMU_DIS0 49 1087 #define CLK_PCLK_SMMU_SCALERC 50 1088 #define CLK_PCLK_SMMU_DRC 51 1089 #define CLK_PCLK_SMMU_ISP 52 1090 #define CLK_PCLK_BTS_SCALERP 53 1091 #define CLK_PCLK_BTS_3DNR 54 1092 #define CLK_PCLK_BTS_DIS1 55 1093 #define CLK_PCLK_BTS_DIS0 56 1094 #define CLK_PCLK_BTS_SCALERC 57 1095 #define CLK_PCLK_BTS_DRC 58 1096 #define CLK_PCLK_BTS_ISP 59 1097 #define CLK_PCLK_ASYNCAXI_DIS1 60 1098 #define CLK_PCLK_ASYNCAXI_DIS0 61 1099 #define CLK_PCLK_PMU_ISP 62 1100 #define CLK_PCLK_SYSREG_ISP 63 1101 #define CLK_PCLK_CMU_ISP_LOCAL 64 1102 #define CLK_PCLK_SCALERP 65 1103 #define CLK_PCLK_3DNR 66 1104 #define CLK_PCLK_DIS_CORE 67 1105 #define CLK_PCLK_DIS 68 1106 #define CLK_PCLK_SCALERC 69 1107 #define CLK_PCLK_DRC 70 1108 #define CLK_PCLK_ISP 71 1109 #define CLK_SCLK_PIXELASYNCS_DIS 72 1110 #define CLK_SCLK_PIXELASYNCM_DIS 73 1111 #define CLK_SCLK_PIXELASYNCS_SCALERP 74 1112 #define CLK_SCLK_PIXELASYNCM_ISPD 75 1113 #define CLK_SCLK_PIXELASYNCS_ISPC 76 1114 #define CLK_SCLK_PIXELASYNCM_ISPC 77 1115 1116 /* CMU_CAM0 */ 1117 #define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1 1118 #define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2 1119 1120 #define CLK_MOUT_ACLK_CAM0_333_USER 3 1121 #define CLK_MOUT_ACLK_CAM0_400_USER 4 1122 #define CLK_MOUT_ACLK_CAM0_552_USER 5 1123 #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER 6 1124 #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER 7 1125 #define CLK_MOUT_ACLK_LITE_D_B 8 1126 #define CLK_MOUT_ACLK_LITE_D_A 9 1127 #define CLK_MOUT_ACLK_LITE_B_B 10 1128 #define CLK_MOUT_ACLK_LITE_B_A 11 1129 #define CLK_MOUT_ACLK_LITE_A_B 12 1130 #define CLK_MOUT_ACLK_LITE_A_A 13 1131 #define CLK_MOUT_ACLK_CAM0_400 14 1132 #define CLK_MOUT_ACLK_CSIS1_B 15 1133 #define CLK_MOUT_ACLK_CSIS1_A 16 1134 #define CLK_MOUT_ACLK_CSIS0_B 17 1135 #define CLK_MOUT_ACLK_CSIS0_A 18 1136 #define CLK_MOUT_ACLK_3AA1_B 19 1137 #define CLK_MOUT_ACLK_3AA1_A 20 1138 #define CLK_MOUT_ACLK_3AA0_B 21 1139 #define CLK_MOUT_ACLK_3AA0_A 22 1140 #define CLK_MOUT_SCLK_LITE_FREECNT_C 23 1141 #define CLK_MOUT_SCLK_LITE_FREECNT_B 24 1142 #define CLK_MOUT_SCLK_LITE_FREECNT_A 25 1143 #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B 26 1144 #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A 27 1145 #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B 28 1146 #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A 29 1147 1148 #define CLK_DIV_PCLK_CAM0_50 30 1149 #define CLK_DIV_ACLK_CAM0_200 31 1150 #define CLK_DIV_ACLK_CAM0_BUS_400 32 1151 #define CLK_DIV_PCLK_LITE_D 33 1152 #define CLK_DIV_ACLK_LITE_D 34 1153 #define CLK_DIV_PCLK_LITE_B 35 1154 #define CLK_DIV_ACLK_LITE_B 36 1155 #define CLK_DIV_PCLK_LITE_A 37 1156 #define CLK_DIV_ACLK_LITE_A 38 1157 #define CLK_DIV_ACLK_CSIS1 39 1158 #define CLK_DIV_ACLK_CSIS0 40 1159 #define CLK_DIV_PCLK_3AA1 41 1160 #define CLK_DIV_ACLK_3AA1 42 1161 #define CLK_DIV_PCLK_3AA0 43 1162 #define CLK_DIV_ACLK_3AA0 44 1163 #define CLK_DIV_SCLK_PIXELASYNC_LITE_C 45 1164 #define CLK_DIV_PCLK_PIXELASYNC_LITE_C 46 1165 #define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT 47 1166 1167 #define CLK_ACLK_CSIS1 50 1168 #define CLK_ACLK_CSIS0 51 1169 #define CLK_ACLK_3AA1 52 1170 #define CLK_ACLK_3AA0 53 1171 #define CLK_ACLK_LITE_D 54 1172 #define CLK_ACLK_LITE_B 55 1173 #define CLK_ACLK_LITE_A 56 1174 #define CLK_ACLK_AHBSYNCDN 57 1175 #define CLK_ACLK_AXIUS_LITE_D 58 1176 #define CLK_ACLK_AXIUS_LITE_B 59 1177 #define CLK_ACLK_AXIUS_LITE_A 60 1178 #define CLK_ACLK_ASYNCAPBM_3AA1 61 1179 #define CLK_ACLK_ASYNCAPBS_3AA1 62 1180 #define CLK_ACLK_ASYNCAPBM_3AA0 63 1181 #define CLK_ACLK_ASYNCAPBS_3AA0 64 1182 #define CLK_ACLK_ASYNCAPBM_LITE_D 65 1183 #define CLK_ACLK_ASYNCAPBS_LITE_D 66 1184 #define CLK_ACLK_ASYNCAPBM_LITE_B 67 1185 #define CLK_ACLK_ASYNCAPBS_LITE_B 68 1186 #define CLK_ACLK_ASYNCAPBM_LITE_A 69 1187 #define CLK_ACLK_ASYNCAPBS_LITE_A 70 1188 #define CLK_ACLK_ASYNCAXIM_ISP0P 71 1189 #define CLK_ACLK_ASYNCAXIM_3AA1 72 1190 #define CLK_ACLK_ASYNCAXIS_3AA1 73 1191 #define CLK_ACLK_ASYNCAXIM_3AA0 74 1192 #define CLK_ACLK_ASYNCAXIS_3AA0 75 1193 #define CLK_ACLK_ASYNCAXIM_LITE_D 76 1194 #define CLK_ACLK_ASYNCAXIS_LITE_D 77 1195 #define CLK_ACLK_ASYNCAXIM_LITE_B 78 1196 #define CLK_ACLK_ASYNCAXIS_LITE_B 79 1197 #define CLK_ACLK_ASYNCAXIM_LITE_A 80 1198 #define CLK_ACLK_ASYNCAXIS_LITE_A 81 1199 #define CLK_ACLK_AHB2APB_ISPSFRP 82 1200 #define CLK_ACLK_AXI2APB_ISP0P 83 1201 #define CLK_ACLK_AXI2AHB_ISP0P 84 1202 #define CLK_ACLK_XIU_IS0X 85 1203 #define CLK_ACLK_XIU_ISP0EX 86 1204 #define CLK_ACLK_CAM0NP_276 87 1205 #define CLK_ACLK_CAM0ND_400 88 1206 #define CLK_ACLK_SMMU_3AA1 89 1207 #define CLK_ACLK_SMMU_3AA0 90 1208 #define CLK_ACLK_SMMU_LITE_D 91 1209 #define CLK_ACLK_SMMU_LITE_B 92 1210 #define CLK_ACLK_SMMU_LITE_A 93 1211 #define CLK_ACLK_BTS_3AA1 94 1212 #define CLK_ACLK_BTS_3AA0 95 1213 #define CLK_ACLK_BTS_LITE_D 96 1214 #define CLK_ACLK_BTS_LITE_B 97 1215 #define CLK_ACLK_BTS_LITE_A 98 1216 #define CLK_PCLK_SMMU_3AA1 99 1217 #define CLK_PCLK_SMMU_3AA0 100 1218 #define CLK_PCLK_SMMU_LITE_D 101 1219 #define CLK_PCLK_SMMU_LITE_B 102 1220 #define CLK_PCLK_SMMU_LITE_A 103 1221 #define CLK_PCLK_BTS_3AA1 104 1222 #define CLK_PCLK_BTS_3AA0 105 1223 #define CLK_PCLK_BTS_LITE_D 106 1224 #define CLK_PCLK_BTS_LITE_B 107 1225 #define CLK_PCLK_BTS_LITE_A 108 1226 #define CLK_PCLK_ASYNCAXI_CAM1 109 1227 #define CLK_PCLK_ASYNCAXI_3AA1 110 1228 #define CLK_PCLK_ASYNCAXI_3AA0 111 1229 #define CLK_PCLK_ASYNCAXI_LITE_D 112 1230 #define CLK_PCLK_ASYNCAXI_LITE_B 113 1231 #define CLK_PCLK_ASYNCAXI_LITE_A 114 1232 #define CLK_PCLK_PMU_CAM0 115 1233 #define CLK_PCLK_SYSREG_CAM0 116 1234 #define CLK_PCLK_CMU_CAM0_LOCAL 117 1235 #define CLK_PCLK_CSIS1 118 1236 #define CLK_PCLK_CSIS0 119 1237 #define CLK_PCLK_3AA1 120 1238 #define CLK_PCLK_3AA0 121 1239 #define CLK_PCLK_LITE_D 122 1240 #define CLK_PCLK_LITE_B 123 1241 #define CLK_PCLK_LITE_A 124 1242 #define CLK_PHYCLK_RXBYTECLKHS0_S4 125 1243 #define CLK_PHYCLK_RXBYTECLKHS0_S2A 126 1244 #define CLK_SCLK_LITE_FREECNT 127 1245 #define CLK_SCLK_PIXELASYNCM_3AA1 128 1246 #define CLK_SCLK_PIXELASYNCM_3AA0 129 1247 #define CLK_SCLK_PIXELASYNCS_3AA0 130 1248 #define CLK_SCLK_PIXELASYNCM_LITE_C 131 1249 #define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132 1250 #define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133 1251 1252 /* CMU_CAM1 */ 1253 #define CLK_PHYCLK_RXBYTEECLKHS0_S2B 1 1254 1255 #define CLK_MOUT_SCLK_ISP_UART_USER 2 1256 #define CLK_MOUT_SCLK_ISP_SPI1_USER 3 1257 #define CLK_MOUT_SCLK_ISP_SPI0_USER 4 1258 #define CLK_MOUT_ACLK_CAM1_333_USER 5 1259 #define CLK_MOUT_ACLK_CAM1_400_USER 6 1260 #define CLK_MOUT_ACLK_CAM1_552_USER 7 1261 #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER 8 1262 #define CLK_MOUT_ACLK_CSIS2_B 9 1263 #define CLK_MOUT_ACLK_CSIS2_A 10 1264 #define CLK_MOUT_ACLK_FD_B 11 1265 #define CLK_MOUT_ACLK_FD_A 12 1266 #define CLK_MOUT_ACLK_LITE_C_B 13 1267 #define CLK_MOUT_ACLK_LITE_C_A 14 1268 1269 #define CLK_DIV_SCLK_ISP_MPWM 15 1270 #define CLK_DIV_PCLK_CAM1_83 16 1271 #define CLK_DIV_PCLK_CAM1_166 17 1272 #define CLK_DIV_PCLK_DBG_CAM1 18 1273 #define CLK_DIV_ATCLK_CAM1 19 1274 #define CLK_DIV_ACLK_CSIS2 20 1275 #define CLK_DIV_PCLK_FD 21 1276 #define CLK_DIV_ACLK_FD 22 1277 #define CLK_DIV_PCLK_LITE_C 23 1278 #define CLK_DIV_ACLK_LITE_C 24 1279 1280 #define CLK_ACLK_ISP_GIC 25 1281 #define CLK_ACLK_FD 26 1282 #define CLK_ACLK_LITE_C 27 1283 #define CLK_ACLK_CSIS2 28 1284 #define CLK_ACLK_ASYNCAPBM_FD 29 1285 #define CLK_ACLK_ASYNCAPBS_FD 30 1286 #define CLK_ACLK_ASYNCAPBM_LITE_C 31 1287 #define CLK_ACLK_ASYNCAPBS_LITE_C 32 1288 #define CLK_ACLK_ASYNCAHBS_SFRISP2H2 33 1289 #define CLK_ACLK_ASYNCAHBS_SFRISP2H1 34 1290 #define CLK_ACLK_ASYNCAXIM_CA5 35 1291 #define CLK_ACLK_ASYNCAXIS_CA5 36 1292 #define CLK_ACLK_ASYNCAXIS_ISPX2 37 1293 #define CLK_ACLK_ASYNCAXIS_ISPX1 38 1294 #define CLK_ACLK_ASYNCAXIS_ISPX0 39 1295 #define CLK_ACLK_ASYNCAXIM_ISPEX 40 1296 #define CLK_ACLK_ASYNCAXIM_ISP3P 41 1297 #define CLK_ACLK_ASYNCAXIS_ISP3P 42 1298 #define CLK_ACLK_ASYNCAXIM_FD 43 1299 #define CLK_ACLK_ASYNCAXIS_FD 44 1300 #define CLK_ACLK_ASYNCAXIM_LITE_C 45 1301 #define CLK_ACLK_ASYNCAXIS_LITE_C 46 1302 #define CLK_ACLK_AHB2APB_ISP5P 47 1303 #define CLK_ACLK_AHB2APB_ISP3P 48 1304 #define CLK_ACLK_AXI2APB_ISP3P 49 1305 #define CLK_ACLK_AHB_SFRISP2H 50 1306 #define CLK_ACLK_AXI_ISP_HX_R 51 1307 #define CLK_ACLK_AXI_ISP_CX_R 52 1308 #define CLK_ACLK_AXI_ISP_HX 53 1309 #define CLK_ACLK_AXI_ISP_CX 54 1310 #define CLK_ACLK_XIU_ISPX 55 1311 #define CLK_ACLK_XIU_ISPEX 56 1312 #define CLK_ACLK_CAM1NP_333 57 1313 #define CLK_ACLK_CAM1ND_400 58 1314 #define CLK_ACLK_SMMU_ISPCPU 59 1315 #define CLK_ACLK_SMMU_FD 60 1316 #define CLK_ACLK_SMMU_LITE_C 61 1317 #define CLK_ACLK_BTS_ISP3P 62 1318 #define CLK_ACLK_BTS_FD 63 1319 #define CLK_ACLK_BTS_LITE_C 64 1320 #define CLK_ACLK_AHBDN_SFRISP2H 65 1321 #define CLK_ACLK_AHBDN_ISP5P 66 1322 #define CLK_ACLK_AXIUS_ISP3P 67 1323 #define CLK_ACLK_AXIUS_FD 68 1324 #define CLK_ACLK_AXIUS_LITE_C 69 1325 #define CLK_PCLK_SMMU_ISPCPU 70 1326 #define CLK_PCLK_SMMU_FD 71 1327 #define CLK_PCLK_SMMU_LITE_C 72 1328 #define CLK_PCLK_BTS_ISP3P 73 1329 #define CLK_PCLK_BTS_FD 74 1330 #define CLK_PCLK_BTS_LITE_C 75 1331 #define CLK_PCLK_ASYNCAXIM_CA5 76 1332 #define CLK_PCLK_ASYNCAXIM_ISPEX 77 1333 #define CLK_PCLK_ASYNCAXIM_ISP3P 78 1334 #define CLK_PCLK_ASYNCAXIM_FD 79 1335 #define CLK_PCLK_ASYNCAXIM_LITE_C 80 1336 #define CLK_PCLK_PMU_CAM1 81 1337 #define CLK_PCLK_SYSREG_CAM1 82 1338 #define CLK_PCLK_CMU_CAM1_LOCAL 83 1339 #define CLK_PCLK_ISP_MCTADC 84 1340 #define CLK_PCLK_ISP_WDT 85 1341 #define CLK_PCLK_ISP_PWM 86 1342 #define CLK_PCLK_ISP_UART 87 1343 #define CLK_PCLK_ISP_MCUCTL 88 1344 #define CLK_PCLK_ISP_SPI1 89 1345 #define CLK_PCLK_ISP_SPI0 90 1346 #define CLK_PCLK_ISP_I2C2 91 1347 #define CLK_PCLK_ISP_I2C1 92 1348 #define CLK_PCLK_ISP_I2C0 93 1349 #define CLK_PCLK_ISP_MPWM 94 1350 #define CLK_PCLK_FD 95 1351 #define CLK_PCLK_LITE_C 96 1352 #define CLK_PCLK_CSIS2 97 1353 #define CLK_SCLK_ISP_I2C2 98 1354 #define CLK_SCLK_ISP_I2C1 99 1355 #define CLK_SCLK_ISP_I2C0 100 1356 #define CLK_SCLK_ISP_PWM 101 1357 #define CLK_PHYCLK_RXBYTECLKHS0_S2B 102 1358 #define CLK_SCLK_LITE_C_FREECNT 103 1359 #define CLK_SCLK_PIXELASYNCM_FD 104 1360 #define CLK_SCLK_ISP_MCTADC 105 1361 #define CLK_SCLK_ISP_UART 106 1362 #define CLK_SCLK_ISP_SPI1 107 1363 #define CLK_SCLK_ISP_SPI0 108 1364 #define CLK_SCLK_ISP_MPWM 109 1365 #define CLK_PCLK_DBG_ISP 110 1366 #define CLK_ATCLK_ISP 111 1367 #define CLK_SCLK_ISP_CA5 112 1368 1369 /* CMU_IMEM */ 1370 #define CLK_ACLK_SLIMSSS 2 1371 #define CLK_PCLK_SLIMSSS 35 1372 1373 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 1374