196bd6224SChanwoo Choi /* 296bd6224SChanwoo Choi * Copyright (c) 2014 Samsung Electronics Co., Ltd. 396bd6224SChanwoo Choi * Author: Chanwoo Choi <cw00.choi@samsung.com> 496bd6224SChanwoo Choi * 596bd6224SChanwoo Choi * This program is free software; you can redistribute it and/or modify 696bd6224SChanwoo Choi * it under the terms of the GNU General Public License version 2 as 796bd6224SChanwoo Choi * published by the Free Software Foundation. 896bd6224SChanwoo Choi */ 996bd6224SChanwoo Choi 1096bd6224SChanwoo Choi #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 1196bd6224SChanwoo Choi #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 1296bd6224SChanwoo Choi 1396bd6224SChanwoo Choi /* CMU_TOP */ 1496bd6224SChanwoo Choi #define CLK_FOUT_ISP_PLL 1 1596bd6224SChanwoo Choi #define CLK_FOUT_AUD_PLL 2 1696bd6224SChanwoo Choi 1796bd6224SChanwoo Choi #define CLK_MOUT_AUD_PLL 10 1896bd6224SChanwoo Choi #define CLK_MOUT_ISP_PLL 11 1996bd6224SChanwoo Choi #define CLK_MOUT_AUD_PLL_USER_T 12 2096bd6224SChanwoo Choi #define CLK_MOUT_MPHY_PLL_USER 13 2196bd6224SChanwoo Choi #define CLK_MOUT_MFC_PLL_USER 14 2296bd6224SChanwoo Choi #define CLK_MOUT_BUS_PLL_USER 15 2396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_HEVC_400 16 2496bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_333 17 2596bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_B 18 2696bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_A 19 2796bd6224SChanwoo Choi #define CLK_MOUT_ACLK_ISP_DIS_400 20 2896bd6224SChanwoo Choi #define CLK_MOUT_ACLK_ISP_400 21 2996bd6224SChanwoo Choi #define CLK_MOUT_ACLK_BUS0_400 22 3096bd6224SChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_B 23 3196bd6224SChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_A 24 3296bd6224SChanwoo Choi #define CLK_MOUT_ACLK_GSCL_333 25 3396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_G2D_400_B 26 3496bd6224SChanwoo Choi #define CLK_MOUT_ACLK_G2D_400_A 27 3596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_C 28 3696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_B 29 3796bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_A 30 3896bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_B 31 3996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_A 32 4096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_B 33 4196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_A 34 4296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_D 35 4396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_C 36 4496bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_B 37 4596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_A 38 4696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI4 39 4796bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI3 40 4896bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART2 41 4996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART1 42 5096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART0 43 5196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI2 44 5296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI1 45 5396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI0 46 5423236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_C 47 5523236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_B 48 5623236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_A 49 5723236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR2 50 5823236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR1 51 5923236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR0 52 6023236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_UART 53 6123236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI1 54 6223236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI0 55 6323236496SChanwoo Choi #define CLK_MOUT_SCLK_PCIE_100 56 6423236496SChanwoo Choi #define CLK_MOUT_SCLK_UFSUNIPRO 57 6523236496SChanwoo Choi #define CLK_MOUT_SCLK_USBHOST30 58 6623236496SChanwoo Choi #define CLK_MOUT_SCLK_USBDRD30 59 6723236496SChanwoo Choi #define CLK_MOUT_SCLK_SLIMBUS 60 6823236496SChanwoo Choi #define CLK_MOUT_SCLK_SPDIF 61 6923236496SChanwoo Choi #define CLK_MOUT_SCLK_AUDIO1 62 7023236496SChanwoo Choi #define CLK_MOUT_SCLK_AUDIO0 63 712a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_HDMI_SPDIF 64 7296bd6224SChanwoo Choi 7396bd6224SChanwoo Choi #define CLK_DIV_ACLK_FSYS_200 100 7496bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_SSSX_266 101 7596bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_200 102 7696bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_266 103 7796bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIC_66_B 104 7896bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIC_66_A 105 7996bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIS_66_B 106 8096bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIS_66_A 107 8196bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC1_B 108 8296bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC1_A 109 8396bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC0_B 110 8496bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC0_A 111 8596bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC2_B 112 8696bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC2_A 113 8796bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI1_B 114 8896bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI1_A 115 8996bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI0_B 116 9096bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI0_A 117 9196bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI2_B 118 9296bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI2_A 119 9396bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART2 120 9496bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART1 121 9596bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART0 122 9696bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI4_B 123 9796bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI4_A 124 9896bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI3_B 125 9996bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI3_A 126 10023236496SChanwoo Choi #define CLK_DIV_SCLK_I2S1 127 10123236496SChanwoo Choi #define CLK_DIV_SCLK_PCM1 128 10223236496SChanwoo Choi #define CLK_DIV_SCLK_AUDIO1 129 10323236496SChanwoo Choi #define CLK_DIV_SCLK_AUDIO0 130 104a29308daSChanwoo Choi #define CLK_DIV_ACLK_GSCL_111 131 105a29308daSChanwoo Choi #define CLK_DIV_ACLK_GSCL_333 132 106a29308daSChanwoo Choi #define CLK_DIV_ACLK_HEVC_400 133 107a29308daSChanwoo Choi #define CLK_DIV_ACLK_MFC_400 134 108a29308daSChanwoo Choi #define CLK_DIV_ACLK_G2D_266 135 109a29308daSChanwoo Choi #define CLK_DIV_ACLK_G2D_400 136 1105785d6e6SChanwoo Choi #define CLK_DIV_ACLK_G3D_400 137 1115785d6e6SChanwoo Choi #define CLK_DIV_ACLK_BUS0_400 138 1125785d6e6SChanwoo Choi #define CLK_DIV_ACLK_BUS1_400 139 1134b801355SChanwoo Choi #define CLK_DIV_SCLK_PCIE_100 140 1144b801355SChanwoo Choi #define CLK_DIV_SCLK_USBHOST30 141 1154b801355SChanwoo Choi #define CLK_DIV_SCLK_UFSUNIPRO 142 1164b801355SChanwoo Choi #define CLK_DIV_SCLK_USBDRD30 143 117b274bbfdSChanwoo Choi #define CLK_DIV_SCLK_JPEG 144 118b274bbfdSChanwoo Choi #define CLK_DIV_ACLK_MSCL_400 145 1198e46c4b8SChanwoo Choi #define CLK_DIV_ACLK_ISP_DIS_400 146 1208e46c4b8SChanwoo Choi #define CLK_DIV_ACLK_ISP_400 147 1216958f22fSChanwoo Choi #define CLK_DIV_ACLK_CAM0_333 148 1226958f22fSChanwoo Choi #define CLK_DIV_ACLK_CAM0_400 149 1236958f22fSChanwoo Choi #define CLK_DIV_ACLK_CAM0_552 150 124a5958a93SChanwoo Choi #define CLK_DIV_ACLK_CAM1_333 151 125a5958a93SChanwoo Choi #define CLK_DIV_ACLK_CAM1_400 152 126a5958a93SChanwoo Choi #define CLK_DIV_ACLK_CAM1_552 153 127a5958a93SChanwoo Choi #define CLK_DIV_SCLK_ISP_UART 154 128a5958a93SChanwoo Choi #define CLK_DIV_SCLK_ISP_SPI1_B 155 129a5958a93SChanwoo Choi #define CLK_DIV_SCLK_ISP_SPI1_A 156 130a5958a93SChanwoo Choi #define CLK_DIV_SCLK_ISP_SPI0_B 157 131a5958a93SChanwoo Choi #define CLK_DIV_SCLK_ISP_SPI0_A 158 132a5958a93SChanwoo Choi #define CLK_DIV_SCLK_ISP_SENSOR2_B 159 133a5958a93SChanwoo Choi #define CLK_DIV_SCLK_ISP_SENSOR2_A 160 134a5958a93SChanwoo Choi #define CLK_DIV_SCLK_ISP_SENSOR1_B 161 135a5958a93SChanwoo Choi #define CLK_DIV_SCLK_ISP_SENSOR1_A 162 136a5958a93SChanwoo Choi #define CLK_DIV_SCLK_ISP_SENSOR0_B 163 137a5958a93SChanwoo Choi #define CLK_DIV_SCLK_ISP_SENSOR0_A 164 13896bd6224SChanwoo Choi 13996bd6224SChanwoo Choi #define CLK_ACLK_PERIC_66 200 14096bd6224SChanwoo Choi #define CLK_ACLK_PERIS_66 201 14196bd6224SChanwoo Choi #define CLK_ACLK_FSYS_200 202 14296bd6224SChanwoo Choi #define CLK_SCLK_MMC2_FSYS 203 14396bd6224SChanwoo Choi #define CLK_SCLK_MMC1_FSYS 204 14496bd6224SChanwoo Choi #define CLK_SCLK_MMC0_FSYS 205 14596bd6224SChanwoo Choi #define CLK_SCLK_SPI4_PERIC 206 14696bd6224SChanwoo Choi #define CLK_SCLK_SPI3_PERIC 207 14796bd6224SChanwoo Choi #define CLK_SCLK_UART2_PERIC 208 14896bd6224SChanwoo Choi #define CLK_SCLK_UART1_PERIC 209 14996bd6224SChanwoo Choi #define CLK_SCLK_UART0_PERIC 210 15096bd6224SChanwoo Choi #define CLK_SCLK_SPI2_PERIC 211 15196bd6224SChanwoo Choi #define CLK_SCLK_SPI1_PERIC 212 15296bd6224SChanwoo Choi #define CLK_SCLK_SPI0_PERIC 213 15323236496SChanwoo Choi #define CLK_SCLK_SPDIF_PERIC 214 15423236496SChanwoo Choi #define CLK_SCLK_I2S1_PERIC 215 15523236496SChanwoo Choi #define CLK_SCLK_PCM1_PERIC 216 15623236496SChanwoo Choi #define CLK_SCLK_SLIMBUS 217 15723236496SChanwoo Choi #define CLK_SCLK_AUDIO1 218 15823236496SChanwoo Choi #define CLK_SCLK_AUDIO0 219 159a29308daSChanwoo Choi #define CLK_ACLK_G2D_266 220 160a29308daSChanwoo Choi #define CLK_ACLK_G2D_400 221 1615785d6e6SChanwoo Choi #define CLK_ACLK_G3D_400 222 1625785d6e6SChanwoo Choi #define CLK_ACLK_IMEM_SSX_266 223 1635785d6e6SChanwoo Choi #define CLK_ACLK_BUS0_400 224 1645785d6e6SChanwoo Choi #define CLK_ACLK_BUS1_400 225 1655785d6e6SChanwoo Choi #define CLK_ACLK_IMEM_200 226 1665785d6e6SChanwoo Choi #define CLK_ACLK_IMEM_266 227 1674b801355SChanwoo Choi #define CLK_SCLK_PCIE_100_FSYS 228 1684b801355SChanwoo Choi #define CLK_SCLK_UFSUNIPRO_FSYS 229 1694b801355SChanwoo Choi #define CLK_SCLK_USBHOST30_FSYS 230 1704b801355SChanwoo Choi #define CLK_SCLK_USBDRD30_FSYS 231 1712a2f33e8SChanwoo Choi #define CLK_ACLK_GSCL_111 232 1722a2f33e8SChanwoo Choi #define CLK_ACLK_GSCL_333 233 173b274bbfdSChanwoo Choi #define CLK_SCLK_JPEG_MSCL 234 174b274bbfdSChanwoo Choi #define CLK_ACLK_MSCL_400 235 1759910b6bbSChanwoo Choi #define CLK_ACLK_MFC_400 236 17645e58aa5SChanwoo Choi #define CLK_ACLK_HEVC_400 237 1778e46c4b8SChanwoo Choi #define CLK_ACLK_ISP_DIS_400 238 1788e46c4b8SChanwoo Choi #define CLK_ACLK_ISP_400 239 1796958f22fSChanwoo Choi #define CLK_ACLK_CAM0_333 240 1806958f22fSChanwoo Choi #define CLK_ACLK_CAM0_400 241 1816958f22fSChanwoo Choi #define CLK_ACLK_CAM0_552 242 182a5958a93SChanwoo Choi #define CLK_ACLK_CAM1_333 243 183a5958a93SChanwoo Choi #define CLK_ACLK_CAM1_400 244 184a5958a93SChanwoo Choi #define CLK_ACLK_CAM1_552 245 185a5958a93SChanwoo Choi #define CLK_SCLK_ISP_SENSOR2 246 186a5958a93SChanwoo Choi #define CLK_SCLK_ISP_SENSOR1 247 187a5958a93SChanwoo Choi #define CLK_SCLK_ISP_SENSOR0 248 188a5958a93SChanwoo Choi #define CLK_SCLK_ISP_MCTADC_CAM1 249 189a5958a93SChanwoo Choi #define CLK_SCLK_ISP_UART_CAM1 250 190a5958a93SChanwoo Choi #define CLK_SCLK_ISP_SPI1_CAM1 251 191a5958a93SChanwoo Choi #define CLK_SCLK_ISP_SPI0_CAM1 252 192b2f0e5f2SChanwoo Choi #define CLK_SCLK_HDMI_SPDIF_DISP 253 19396bd6224SChanwoo Choi 194b2f0e5f2SChanwoo Choi #define TOP_NR_CLK 254 19596bd6224SChanwoo Choi 19696bd6224SChanwoo Choi /* CMU_CPIF */ 19796bd6224SChanwoo Choi #define CLK_FOUT_MPHY_PLL 1 19896bd6224SChanwoo Choi 19996bd6224SChanwoo Choi #define CLK_MOUT_MPHY_PLL 2 20096bd6224SChanwoo Choi 20196bd6224SChanwoo Choi #define CLK_DIV_SCLK_MPHY 10 20296bd6224SChanwoo Choi 20396bd6224SChanwoo Choi #define CLK_SCLK_MPHY_PLL 11 20496bd6224SChanwoo Choi #define CLK_SCLK_UFS_MPHY 11 20596bd6224SChanwoo Choi 20696bd6224SChanwoo Choi #define CPIF_NR_CLK 12 20796bd6224SChanwoo Choi 20896bd6224SChanwoo Choi /* CMU_MIF */ 20996bd6224SChanwoo Choi #define CLK_FOUT_MEM0_PLL 1 21096bd6224SChanwoo Choi #define CLK_FOUT_MEM1_PLL 2 21196bd6224SChanwoo Choi #define CLK_FOUT_BUS_PLL 3 21296bd6224SChanwoo Choi #define CLK_FOUT_MFC_PLL 4 21306d2f9dfSChanwoo Choi #define CLK_DOUT_MFC_PLL 5 21406d2f9dfSChanwoo Choi #define CLK_DOUT_BUS_PLL 6 21506d2f9dfSChanwoo Choi #define CLK_DOUT_MEM1_PLL 7 21606d2f9dfSChanwoo Choi #define CLK_DOUT_MEM0_PLL 8 21796bd6224SChanwoo Choi 21806d2f9dfSChanwoo Choi #define CLK_MOUT_MFC_PLL_DIV2 10 21906d2f9dfSChanwoo Choi #define CLK_MOUT_BUS_PLL_DIV2 11 22006d2f9dfSChanwoo Choi #define CLK_MOUT_MEM1_PLL_DIV2 12 22106d2f9dfSChanwoo Choi #define CLK_MOUT_MEM0_PLL_DIV2 13 22206d2f9dfSChanwoo Choi #define CLK_MOUT_MFC_PLL 14 22306d2f9dfSChanwoo Choi #define CLK_MOUT_BUS_PLL 15 22406d2f9dfSChanwoo Choi #define CLK_MOUT_MEM1_PLL 16 22506d2f9dfSChanwoo Choi #define CLK_MOUT_MEM0_PLL 17 22606d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_C 18 22706d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_B 19 22806d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_A 20 22906d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_C 21 23006d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_B 22 23106d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_A 23 23206d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_MIFNM_200 24 23306d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_MIFNM_400 25 23406d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_B 26 23506d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_A 27 23606d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_C 28 23706d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_B 29 23806d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_A 30 23906d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_C 31 24006d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_B 32 24106d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_A 33 24206d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34 24306d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35 24406d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36 24506d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_C 37 24606d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_B 38 24706d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_A 39 24806d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_C 40 24906d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_B 41 25006d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_A 42 25106d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46 25206d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47 25306d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48 25406d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_C 49 25506d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_B 50 25606d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_A 51 25706d2f9dfSChanwoo Choi 25806d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_HPM_MIF 55 25906d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DREX1 56 26006d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DREX0 57 26106d2f9dfSChanwoo Choi #define CLK_DIV_CLK2XPHY 58 26206d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_266 59 26306d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIFND_133 60 26406d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_133 61 26506d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIFNM_200 62 26606d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_200 63 26706d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_400 64 26806d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_BUS2_400 65 26906d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DISP_333 66 27006d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_CPIF_200 67 27106d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSIM1 68 27206d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_VCLK 69 27306d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSIM0 70 27406d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSD 71 27506d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_ECLK 72 27606d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_VCLK 73 27706d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_ECLK 74 27806d2f9dfSChanwoo Choi #define CLK_DIV_MIF_PRE 75 27906d2f9dfSChanwoo Choi 28006d2f9dfSChanwoo Choi #define CLK_CLK2X_PHY1 80 28106d2f9dfSChanwoo Choi #define CLK_CLK2X_PHY0 81 28206d2f9dfSChanwoo Choi #define CLK_CLKM_PHY1 82 28306d2f9dfSChanwoo Choi #define CLK_CLKM_PHY0 83 28406d2f9dfSChanwoo Choi #define CLK_RCLK_DREX1 84 28506d2f9dfSChanwoo Choi #define CLK_RCLK_DREX0 85 28606d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_TZ 86 28706d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_TZ 87 28806d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_PEREV 88 28906d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_PEREV 89 29006d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_MEMIF 90 29106d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_MEMIF 91 29206d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_SCH 92 29306d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_SCH 93 29406d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_BUSIF 94 29506d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_BUSIF 95 29606d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_BUSIF_RD 96 29706d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_BUSIF_RD 97 29806d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1 98 29906d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0 99 30006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100 30106d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101 30206d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102 30306d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103 30406d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104 30506d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105 30606d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_CP1 106 30706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_CP1 107 30806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_CP0 108 30906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_CP0 109 31006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_3 110 31106d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_3 111 31206d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_1 112 31306d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_1 113 31406d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_0 114 31506d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_0 115 31606d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_3 116 31706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_3 117 31806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_1 118 31906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_1 119 32006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_0 120 32106d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_0 121 32206d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF2P 122 32306d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF1P 123 32406d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF0P 124 32506d2f9dfSChanwoo Choi #define CLK_ACLK_IXIU_CCI 125 32606d2f9dfSChanwoo Choi #define CLK_ACLK_XIU_MIFSFRX 126 32706d2f9dfSChanwoo Choi #define CLK_ACLK_MIFNP_133 127 32806d2f9dfSChanwoo Choi #define CLK_ACLK_MIFNM_200 128 32906d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_133 129 33006d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_400 130 33106d2f9dfSChanwoo Choi #define CLK_ACLK_CCI 131 33206d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_266 132 33306d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S3 133 33406d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S1 134 33506d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S0 135 33606d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S3 136 33706d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S1 137 33806d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S0 138 33906d2f9dfSChanwoo Choi #define CLK_ACLK_BTS_APOLLO 139 34006d2f9dfSChanwoo Choi #define CLK_ACLK_BTS_ATLAS 140 34106d2f9dfSChanwoo Choi #define CLK_ACLK_ACE_SEL_APOLL 141 34206d2f9dfSChanwoo Choi #define CLK_ACLK_ACE_SEL_ATLAS 142 34306d2f9dfSChanwoo Choi #define CLK_ACLK_AXIDS_CCI_MIFSFRX 143 34406d2f9dfSChanwoo Choi #define CLK_ACLK_AXIUS_ATLAS_CCI 144 34506d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDNS_CCI 145 34606d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDN_CCI 146 34706d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDN_NOC_D 147 34806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148 34906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149 35006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150 35106d2f9dfSChanwoo Choi #define CLK_ACLK_BUS2_400 151 35206d2f9dfSChanwoo Choi #define CLK_ACLK_DISP_333 152 35306d2f9dfSChanwoo Choi #define CLK_ACLK_CPIF_200 153 35406d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S3 154 35506d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S1 155 35606d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S0 156 35706d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S3 157 35806d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S1 158 35906d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S0 159 36006d2f9dfSChanwoo Choi #define CLK_PCLK_BTS_APOLLO 160 36106d2f9dfSChanwoo Choi #define CLK_PCLK_BTS_ATLAS 161 36206d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162 36306d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_CP1 163 36406d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_CP0 164 36506d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_3 165 36606d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_1 166 36706d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_0 167 36806d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_3 168 36906d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_1 169 37006d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_0 170 37106d2f9dfSChanwoo Choi #define CLK_PCLK_MIFSRVND_133 171 37206d2f9dfSChanwoo Choi #define CLK_PCLK_PMU_MIF 172 37306d2f9dfSChanwoo Choi #define CLK_PCLK_SYSREG_MIF 173 37406d2f9dfSChanwoo Choi #define CLK_PCLK_GPIO_ALIVE 174 37506d2f9dfSChanwoo Choi #define CLK_PCLK_ABB 175 37606d2f9dfSChanwoo Choi #define CLK_PCLK_PMU_APBIF 176 37706d2f9dfSChanwoo Choi #define CLK_PCLK_DDR_PHY1 177 37806d2f9dfSChanwoo Choi #define CLK_PCLK_DREX1 178 37906d2f9dfSChanwoo Choi #define CLK_PCLK_DDR_PHY0 179 38006d2f9dfSChanwoo Choi #define CLK_PCLK_DREX0 180 38106d2f9dfSChanwoo Choi #define CLK_PCLK_DREX0_TZ 181 38206d2f9dfSChanwoo Choi #define CLK_PCLK_DREX1_TZ 182 38306d2f9dfSChanwoo Choi #define CLK_PCLK_MONOTONIC_CNT 183 38406d2f9dfSChanwoo Choi #define CLK_PCLK_RTC 184 38506d2f9dfSChanwoo Choi #define CLK_SCLK_DSIM1_DISP 185 38606d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_TV_VCLK_DISP 186 38706d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_BUS_PLL 187 38806d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MFC_PLL 188 38906d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MEM0_PLL 189 39006d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MEM1_PLL 190 39106d2f9dfSChanwoo Choi #define CLK_SCLK_DSIM0_DISP 191 39206d2f9dfSChanwoo Choi #define CLK_SCLK_DSD_DISP 192 39306d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_TV_ECLK_DISP 193 39406d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_VCLK_DISP 194 39506d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_ECLK_DISP 195 39606d2f9dfSChanwoo Choi #define CLK_SCLK_HPM_MIF 196 39706d2f9dfSChanwoo Choi #define CLK_SCLK_MFC_PLL 197 39806d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL 198 39906d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL_APOLLO 199 40006d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL_ATLAS 200 40106d2f9dfSChanwoo Choi 402b2f0e5f2SChanwoo Choi #define MIF_NR_CLK 201 40396bd6224SChanwoo Choi 40496bd6224SChanwoo Choi /* CMU_PERIC */ 40596bd6224SChanwoo Choi #define CLK_PCLK_SPI2 1 40696bd6224SChanwoo Choi #define CLK_PCLK_SPI1 2 40796bd6224SChanwoo Choi #define CLK_PCLK_SPI0 3 40896bd6224SChanwoo Choi #define CLK_PCLK_UART2 4 40996bd6224SChanwoo Choi #define CLK_PCLK_UART1 5 41096bd6224SChanwoo Choi #define CLK_PCLK_UART0 6 41196bd6224SChanwoo Choi #define CLK_PCLK_HSI2C3 7 41296bd6224SChanwoo Choi #define CLK_PCLK_HSI2C2 8 41396bd6224SChanwoo Choi #define CLK_PCLK_HSI2C1 9 41496bd6224SChanwoo Choi #define CLK_PCLK_HSI2C0 10 41596bd6224SChanwoo Choi #define CLK_PCLK_I2C7 11 41696bd6224SChanwoo Choi #define CLK_PCLK_I2C6 12 41796bd6224SChanwoo Choi #define CLK_PCLK_I2C5 13 41896bd6224SChanwoo Choi #define CLK_PCLK_I2C4 14 41996bd6224SChanwoo Choi #define CLK_PCLK_I2C3 15 42096bd6224SChanwoo Choi #define CLK_PCLK_I2C2 16 42196bd6224SChanwoo Choi #define CLK_PCLK_I2C1 17 42296bd6224SChanwoo Choi #define CLK_PCLK_I2C0 18 42396bd6224SChanwoo Choi #define CLK_PCLK_SPI4 19 42496bd6224SChanwoo Choi #define CLK_PCLK_SPI3 20 42596bd6224SChanwoo Choi #define CLK_PCLK_HSI2C11 21 42696bd6224SChanwoo Choi #define CLK_PCLK_HSI2C10 22 42796bd6224SChanwoo Choi #define CLK_PCLK_HSI2C9 23 42896bd6224SChanwoo Choi #define CLK_PCLK_HSI2C8 24 42996bd6224SChanwoo Choi #define CLK_PCLK_HSI2C7 25 43096bd6224SChanwoo Choi #define CLK_PCLK_HSI2C6 26 43196bd6224SChanwoo Choi #define CLK_PCLK_HSI2C5 27 43296bd6224SChanwoo Choi #define CLK_PCLK_HSI2C4 28 43396bd6224SChanwoo Choi #define CLK_SCLK_SPI4 29 43496bd6224SChanwoo Choi #define CLK_SCLK_SPI3 30 43596bd6224SChanwoo Choi #define CLK_SCLK_SPI2 31 43696bd6224SChanwoo Choi #define CLK_SCLK_SPI1 32 43796bd6224SChanwoo Choi #define CLK_SCLK_SPI0 33 43896bd6224SChanwoo Choi #define CLK_SCLK_UART2 34 43996bd6224SChanwoo Choi #define CLK_SCLK_UART1 35 44096bd6224SChanwoo Choi #define CLK_SCLK_UART0 36 441d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC2P 37 442d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC1P 38 443d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC0P 39 444d0f5de66SChanwoo Choi #define CLK_ACLK_PERICNP_66 40 445d0f5de66SChanwoo Choi #define CLK_PCLK_SCI 41 446d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_FINGER 42 447d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_ESE 43 448d0f5de66SChanwoo Choi #define CLK_PCLK_PWM 44 449d0f5de66SChanwoo Choi #define CLK_PCLK_SPDIF 45 450d0f5de66SChanwoo Choi #define CLK_PCLK_PCM1 46 451d0f5de66SChanwoo Choi #define CLK_PCLK_I2S1 47 452d0f5de66SChanwoo Choi #define CLK_PCLK_ADCIF 48 453d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_TOUCH 49 454d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_NFC 50 455d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_PERIC 51 456d0f5de66SChanwoo Choi #define CLK_PCLK_PMU_PERIC 52 457d0f5de66SChanwoo Choi #define CLK_PCLK_SYSREG_PERIC 53 458d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI4 54 459d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI3 55 460d0f5de66SChanwoo Choi #define CLK_SCLK_SCI 56 461d0f5de66SChanwoo Choi #define CLK_SCLK_SC_IN 57 462d0f5de66SChanwoo Choi #define CLK_SCLK_PWM 58 463d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI2 59 464d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI1 60 465d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI0 61 466d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_I2S1_BCLK 62 467d0f5de66SChanwoo Choi #define CLK_SCLK_SPDIF 63 468d0f5de66SChanwoo Choi #define CLK_SCLK_PCM1 64 469d0f5de66SChanwoo Choi #define CLK_SCLK_I2S1 65 47096bd6224SChanwoo Choi 471d0f5de66SChanwoo Choi #define CLK_DIV_SCLK_SCI 70 472d0f5de66SChanwoo Choi #define CLK_DIV_SCLK_SC_IN 71 473d0f5de66SChanwoo Choi 474d0f5de66SChanwoo Choi #define PERIC_NR_CLK 72 47596bd6224SChanwoo Choi 47696bd6224SChanwoo Choi /* CMU_PERIS */ 47796bd6224SChanwoo Choi #define CLK_PCLK_HPM_APBIF 1 47896bd6224SChanwoo Choi #define CLK_PCLK_TMU1_APBIF 2 47996bd6224SChanwoo Choi #define CLK_PCLK_TMU0_APBIF 3 48096bd6224SChanwoo Choi #define CLK_PCLK_PMU_PERIS 4 48196bd6224SChanwoo Choi #define CLK_PCLK_SYSREG_PERIS 5 48296bd6224SChanwoo Choi #define CLK_PCLK_CMU_TOP_APBIF 6 48396bd6224SChanwoo Choi #define CLK_PCLK_WDT_APOLLO 7 48496bd6224SChanwoo Choi #define CLK_PCLK_WDT_ATLAS 8 48596bd6224SChanwoo Choi #define CLK_PCLK_MCT 9 48696bd6224SChanwoo Choi #define CLK_PCLK_HDMI_CEC 10 48756bcf3f3SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIS1P 11 48856bcf3f3SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIS0P 12 48956bcf3f3SChanwoo Choi #define CLK_ACLK_PERISNP_66 13 49056bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC12 14 49156bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC11 15 49256bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC10 16 49356bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC9 17 49456bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC8 18 49556bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC7 19 49656bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC6 20 49756bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC5 21 49856bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC4 22 49956bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC3 23 50056bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC2 24 50156bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC1 25 50256bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC0 26 50356bcf3f3SChanwoo Choi #define CLK_PCLK_SECKEY_APBIF 27 50456bcf3f3SChanwoo Choi #define CLK_PCLK_CHIPID_APBIF 28 50556bcf3f3SChanwoo Choi #define CLK_PCLK_TOPRTC 29 50656bcf3f3SChanwoo Choi #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 50756bcf3f3SChanwoo Choi #define CLK_PCLK_ANTIRBK_CNT_APBIF 31 50856bcf3f3SChanwoo Choi #define CLK_PCLK_OTP_CON_APBIF 32 50956bcf3f3SChanwoo Choi #define CLK_SCLK_ASV_TB 33 51056bcf3f3SChanwoo Choi #define CLK_SCLK_TMU1 34 51156bcf3f3SChanwoo Choi #define CLK_SCLK_TMU0 35 51256bcf3f3SChanwoo Choi #define CLK_SCLK_SECKEY 36 51356bcf3f3SChanwoo Choi #define CLK_SCLK_CHIPID 37 51456bcf3f3SChanwoo Choi #define CLK_SCLK_TOPRTC 38 51556bcf3f3SChanwoo Choi #define CLK_SCLK_CUSTOM_EFUSE 39 51656bcf3f3SChanwoo Choi #define CLK_SCLK_ANTIRBK_CNT 40 51756bcf3f3SChanwoo Choi #define CLK_SCLK_OTP_CON 41 51896bd6224SChanwoo Choi 51956bcf3f3SChanwoo Choi #define PERIS_NR_CLK 42 52096bd6224SChanwoo Choi 52196bd6224SChanwoo Choi /* CMU_FSYS */ 52296bd6224SChanwoo Choi #define CLK_MOUT_ACLK_FSYS_200_USER 1 52396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_USER 2 52496bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_USER 3 52596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_USER 4 5264b801355SChanwoo Choi #define CLK_MOUT_SCLK_UFS_MPHY_USER 5 5274b801355SChanwoo Choi #define CLK_MOUT_SCLK_PCIE_100_USER 6 5284b801355SChanwoo Choi #define CLK_MOUT_SCLK_UFSUNIPRO_USER 7 5294b801355SChanwoo Choi #define CLK_MOUT_SCLK_USBHOST30_USER 8 5304b801355SChanwoo Choi #define CLK_MOUT_SCLK_USBDRD30_USER 9 5314b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10 5324b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11 5334b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12 5344b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13 5354b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14 5364b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15 5374b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16 5384b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17 5394b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18 5404b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19 5414b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20 5424b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21 5434b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22 5444b801355SChanwoo Choi #define CLK_MOUT_SCLK_MPHY 23 5454b801355SChanwoo Choi 5464b801355SChanwoo Choi #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25 5474b801355SChanwoo Choi #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26 5484b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27 5494b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28 5504b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29 5514b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30 5524b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31 5534b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32 5544b801355SChanwoo Choi #define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33 5554b801355SChanwoo Choi #define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34 5564b801355SChanwoo Choi #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35 5574b801355SChanwoo Choi #define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36 5584b801355SChanwoo Choi #define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37 55996bd6224SChanwoo Choi 56096bd6224SChanwoo Choi #define CLK_ACLK_PCIE 50 56196bd6224SChanwoo Choi #define CLK_ACLK_PDMA1 51 56296bd6224SChanwoo Choi #define CLK_ACLK_TSI 52 56396bd6224SChanwoo Choi #define CLK_ACLK_MMC2 53 56496bd6224SChanwoo Choi #define CLK_ACLK_MMC1 54 56596bd6224SChanwoo Choi #define CLK_ACLK_MMC0 55 56696bd6224SChanwoo Choi #define CLK_ACLK_UFS 56 56796bd6224SChanwoo Choi #define CLK_ACLK_USBHOST20 57 56896bd6224SChanwoo Choi #define CLK_ACLK_USBHOST30 58 56996bd6224SChanwoo Choi #define CLK_ACLK_USBDRD30 59 57096bd6224SChanwoo Choi #define CLK_ACLK_PDMA0 60 57196bd6224SChanwoo Choi #define CLK_SCLK_MMC2 61 57296bd6224SChanwoo Choi #define CLK_SCLK_MMC1 62 57396bd6224SChanwoo Choi #define CLK_SCLK_MMC0 63 57496bd6224SChanwoo Choi #define CLK_PDMA1 64 57596bd6224SChanwoo Choi #define CLK_PDMA0 65 5764b801355SChanwoo Choi #define CLK_ACLK_XIU_FSYSPX 66 5774b801355SChanwoo Choi #define CLK_ACLK_AHB_USBLINKH1 67 5784b801355SChanwoo Choi #define CLK_ACLK_SMMU_PDMA1 68 5794b801355SChanwoo Choi #define CLK_ACLK_BTS_PCIE 69 5804b801355SChanwoo Choi #define CLK_ACLK_AXIUS_PDMA1 70 5814b801355SChanwoo Choi #define CLK_ACLK_SMMU_PDMA0 71 5824b801355SChanwoo Choi #define CLK_ACLK_BTS_UFS 72 5834b801355SChanwoo Choi #define CLK_ACLK_BTS_USBHOST30 73 5844b801355SChanwoo Choi #define CLK_ACLK_BTS_USBDRD30 74 5854b801355SChanwoo Choi #define CLK_ACLK_AXIUS_PDMA0 75 5864b801355SChanwoo Choi #define CLK_ACLK_AXIUS_USBHS 76 5874b801355SChanwoo Choi #define CLK_ACLK_AXIUS_FSYSSX 77 5884b801355SChanwoo Choi #define CLK_ACLK_AHB2APB_FSYSP 78 5894b801355SChanwoo Choi #define CLK_ACLK_AHB2AXI_USBHS 79 5904b801355SChanwoo Choi #define CLK_ACLK_AHB_USBLINKH0 80 5914b801355SChanwoo Choi #define CLK_ACLK_AHB_USBHS 81 5924b801355SChanwoo Choi #define CLK_ACLK_AHB_FSYSH 82 5934b801355SChanwoo Choi #define CLK_ACLK_XIU_FSYSX 83 5944b801355SChanwoo Choi #define CLK_ACLK_XIU_FSYSSX 84 5954b801355SChanwoo Choi #define CLK_ACLK_FSYSNP_200 85 5964b801355SChanwoo Choi #define CLK_ACLK_FSYSND_200 86 5974b801355SChanwoo Choi #define CLK_PCLK_PCIE_CTRL 87 5984b801355SChanwoo Choi #define CLK_PCLK_SMMU_PDMA1 88 5994b801355SChanwoo Choi #define CLK_PCLK_PCIE_PHY 89 6004b801355SChanwoo Choi #define CLK_PCLK_BTS_PCIE 90 6014b801355SChanwoo Choi #define CLK_PCLK_SMMU_PDMA0 91 6024b801355SChanwoo Choi #define CLK_PCLK_BTS_UFS 92 6034b801355SChanwoo Choi #define CLK_PCLK_BTS_USBHOST30 93 6044b801355SChanwoo Choi #define CLK_PCLK_BTS_USBDRD30 94 6054b801355SChanwoo Choi #define CLK_PCLK_GPIO_FSYS 95 6064b801355SChanwoo Choi #define CLK_PCLK_PMU_FSYS 96 6074b801355SChanwoo Choi #define CLK_PCLK_SYSREG_FSYS 97 6084b801355SChanwoo Choi #define CLK_SCLK_PCIE_100 98 6094b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99 6104b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100 6114b801355SChanwoo Choi #define CLK_PHYCLK_UFS_RX1_SYMBOL 101 6124b801355SChanwoo Choi #define CLK_PHYCLK_UFS_RX0_SYMBOL 102 6134b801355SChanwoo Choi #define CLK_PHYCLK_UFS_TX1_SYMBOL 103 6144b801355SChanwoo Choi #define CLK_PHYCLK_UFS_TX0_SYMBOL 104 6154b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105 6164b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106 6174b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107 6184b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108 6194b801355SChanwoo Choi #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109 6204b801355SChanwoo Choi #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110 6214b801355SChanwoo Choi #define CLK_SCLK_MPHY 111 6224b801355SChanwoo Choi #define CLK_SCLK_UFSUNIPRO 112 6234b801355SChanwoo Choi #define CLK_SCLK_USBHOST30 113 6244b801355SChanwoo Choi #define CLK_SCLK_USBDRD30 114 62596bd6224SChanwoo Choi 6264b801355SChanwoo Choi #define FSYS_NR_CLK 115 62796bd6224SChanwoo Choi 628a29308daSChanwoo Choi /* CMU_G2D */ 629a29308daSChanwoo Choi #define CLK_MUX_ACLK_G2D_266_USER 1 630a29308daSChanwoo Choi #define CLK_MUX_ACLK_G2D_400_USER 2 631a29308daSChanwoo Choi 632a29308daSChanwoo Choi #define CLK_DIV_PCLK_G2D 3 633a29308daSChanwoo Choi 634a29308daSChanwoo Choi #define CLK_ACLK_SMMU_MDMA1 4 635a29308daSChanwoo Choi #define CLK_ACLK_BTS_MDMA1 5 636a29308daSChanwoo Choi #define CLK_ACLK_BTS_G2D 6 637a29308daSChanwoo Choi #define CLK_ACLK_ALB_G2D 7 638a29308daSChanwoo Choi #define CLK_ACLK_AXIUS_G2DX 8 639a29308daSChanwoo Choi #define CLK_ACLK_ASYNCAXI_SYSX 9 640a29308daSChanwoo Choi #define CLK_ACLK_AHB2APB_G2D1P 10 641a29308daSChanwoo Choi #define CLK_ACLK_AHB2APB_G2D0P 11 642a29308daSChanwoo Choi #define CLK_ACLK_XIU_G2DX 12 643a29308daSChanwoo Choi #define CLK_ACLK_G2DNP_133 13 644a29308daSChanwoo Choi #define CLK_ACLK_G2DND_400 14 645a29308daSChanwoo Choi #define CLK_ACLK_MDMA1 15 646a29308daSChanwoo Choi #define CLK_ACLK_G2D 16 647a29308daSChanwoo Choi #define CLK_ACLK_SMMU_G2D 17 648a29308daSChanwoo Choi #define CLK_PCLK_SMMU_MDMA1 18 649a29308daSChanwoo Choi #define CLK_PCLK_BTS_MDMA1 19 650a29308daSChanwoo Choi #define CLK_PCLK_BTS_G2D 20 651a29308daSChanwoo Choi #define CLK_PCLK_ALB_G2D 21 652a29308daSChanwoo Choi #define CLK_PCLK_ASYNCAXI_SYSX 22 653a29308daSChanwoo Choi #define CLK_PCLK_PMU_G2D 23 654a29308daSChanwoo Choi #define CLK_PCLK_SYSREG_G2D 24 655a29308daSChanwoo Choi #define CLK_PCLK_G2D 25 656a29308daSChanwoo Choi #define CLK_PCLK_SMMU_G2D 26 657a29308daSChanwoo Choi 658a29308daSChanwoo Choi #define G2D_NR_CLK 27 659a29308daSChanwoo Choi 6602a1808a6SChanwoo Choi /* CMU_DISP */ 6612a1808a6SChanwoo Choi #define CLK_FOUT_DISP_PLL 1 6622a1808a6SChanwoo Choi 6632a1808a6SChanwoo Choi #define CLK_MOUT_DISP_PLL 2 6642a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_USER 3 6652a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_USER 4 6662a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSD_USER 5 6672a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6 6682a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_USER 7 6692a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_USER 8 6702a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9 6712a1808a6SChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_USER 10 6722a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11 6732a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12 6742a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13 6752a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14 6762a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15 6772a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16 6782a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM0 17 6792a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK 18 6802a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK 19 6812a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK 20 6822a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_B_DISP 21 6832a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_A_DISP 22 6842a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23 6852a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24 6862a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25 6872a1808a6SChanwoo Choi 6882a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DSIM1_DISP 30 6892a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31 6902a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DSIM0_DISP 32 6912a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33 6922a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_VCLK_DISP 34 6932a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_ECLK_DISP 35 6942a1808a6SChanwoo Choi #define CLK_DIV_PCLK_DISP 36 6952a1808a6SChanwoo Choi 6962a1808a6SChanwoo Choi #define CLK_ACLK_DECON_TV 40 6972a1808a6SChanwoo Choi #define CLK_ACLK_DECON 41 6982a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_TV1X 42 6992a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_TV0X 43 7002a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_DECON1X 44 7012a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_DECON0X 45 7022a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M3 46 7032a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M2 47 7042a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M1 48 7052a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M0 49 7062a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM4 50 7072a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM3 51 7082a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM2 52 7092a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM1 53 7102a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM0 54 7112a1808a6SChanwoo Choi #define CLK_ACLK_AHB2APB_DISPSFR2P 55 7122a1808a6SChanwoo Choi #define CLK_ACLK_AHB2APB_DISPSFR1P 56 7132a1808a6SChanwoo Choi #define CLK_ACLK_AHB2APB_DISPSFR0P 57 7142a1808a6SChanwoo Choi #define CLK_ACLK_AHB_DISPH 58 7152a1808a6SChanwoo Choi #define CLK_ACLK_XIU_TV1X 59 7162a1808a6SChanwoo Choi #define CLK_ACLK_XIU_TV0X 60 7172a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DECON1X 61 7182a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DECON0X 62 7192a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DISP1X 63 7202a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DISPNP_100 64 7212a1808a6SChanwoo Choi #define CLK_ACLK_DISP1ND_333 65 7222a1808a6SChanwoo Choi #define CLK_ACLK_DISP0ND_333 66 7232a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_TV1X 67 7242a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_TV0X 68 7252a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_DECON1X 69 7262a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_DECON0X 70 7272a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M3 71 7282a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M2 72 7292a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M1 73 7302a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M0 74 7312a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM4 75 7322a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM3 76 7332a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM2 77 7342a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM1 78 7352a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM0 79 7362a1808a6SChanwoo Choi #define CLK_PCLK_MIC1 80 7372a1808a6SChanwoo Choi #define CLK_PCLK_PMU_DISP 81 7382a1808a6SChanwoo Choi #define CLK_PCLK_SYSREG_DISP 82 7392a1808a6SChanwoo Choi #define CLK_PCLK_HDMIPHY 83 7402a1808a6SChanwoo Choi #define CLK_PCLK_HDMI 84 7412a1808a6SChanwoo Choi #define CLK_PCLK_MIC0 85 7422a1808a6SChanwoo Choi #define CLK_PCLK_DSIM1 86 7432a1808a6SChanwoo Choi #define CLK_PCLK_DSIM0 87 7442a1808a6SChanwoo Choi #define CLK_PCLK_DECON_TV 88 7452a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89 7462a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90 7472a1808a6SChanwoo Choi #define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91 7482a1808a6SChanwoo Choi #define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92 7492a1808a6SChanwoo Choi #define CLK_SCLK_DSIM1 93 7502a1808a6SChanwoo Choi #define CLK_SCLK_DECON_TV_VCLK 94 7512a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95 7522a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96 7532a1808a6SChanwoo Choi #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97 7542a1808a6SChanwoo Choi #define CLK_PHYCLK_HDMI_PIXEL 98 7552a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK_TO_SMIES 99 7562a1808a6SChanwoo Choi #define CLK_SCLK_FREQ_DET_DISP_PLL 100 7572a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK_TO_DSIM0 101 7582a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK_TO_MIC0 102 7592a1808a6SChanwoo Choi #define CLK_SCLK_DSD 103 7602a1808a6SChanwoo Choi #define CLK_SCLK_HDMI_SPDIF 104 7612a1808a6SChanwoo Choi #define CLK_SCLK_DSIM0 105 7622a1808a6SChanwoo Choi #define CLK_SCLK_DECON_TV_ECLK 106 7632a1808a6SChanwoo Choi #define CLK_SCLK_DECON_VCLK 107 7642a1808a6SChanwoo Choi #define CLK_SCLK_DECON_ECLK 108 7652a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK 109 7662a1808a6SChanwoo Choi #define CLK_SCLK_RGB_TV_VCLK 110 7672a1808a6SChanwoo Choi 7682a1808a6SChanwoo Choi #define DISP_NR_CLK 111 7692a1808a6SChanwoo Choi 7702e997c03SChanwoo Choi /* CMU_AUD */ 7712e997c03SChanwoo Choi #define CLK_MOUT_AUD_PLL_USER 1 7722e997c03SChanwoo Choi #define CLK_MOUT_SCLK_AUD_PCM 2 7732e997c03SChanwoo Choi #define CLK_MOUT_SCLK_AUD_I2S 3 7742e997c03SChanwoo Choi 7752e997c03SChanwoo Choi #define CLK_DIV_ATCLK_AUD 4 7762e997c03SChanwoo Choi #define CLK_DIV_PCLK_DBG_AUD 5 7772e997c03SChanwoo Choi #define CLK_DIV_ACLK_AUD 6 7782e997c03SChanwoo Choi #define CLK_DIV_AUD_CA5 7 7792e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_SLIMBUS 8 7802e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_UART 9 7812e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_PCM 10 7822e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_I2S 11 7832e997c03SChanwoo Choi 7842e997c03SChanwoo Choi #define CLK_ACLK_INTR_CTRL 12 7852e997c03SChanwoo Choi #define CLK_ACLK_AXIDS2_LPASSP 13 7862e997c03SChanwoo Choi #define CLK_ACLK_AXIDS1_LPASSP 14 7872e997c03SChanwoo Choi #define CLK_ACLK_AXI2APB1_LPASSP 15 7882e997c03SChanwoo Choi #define CLK_ACLK_AXI2APH_LPASSP 16 7892e997c03SChanwoo Choi #define CLK_ACLK_SMMU_LPASSX 17 7902e997c03SChanwoo Choi #define CLK_ACLK_AXIDS0_LPASSP 18 7912e997c03SChanwoo Choi #define CLK_ACLK_AXI2APB0_LPASSP 19 7922e997c03SChanwoo Choi #define CLK_ACLK_XIU_LPASSX 20 7932e997c03SChanwoo Choi #define CLK_ACLK_AUDNP_133 21 7942e997c03SChanwoo Choi #define CLK_ACLK_AUDND_133 22 7952e997c03SChanwoo Choi #define CLK_ACLK_SRAMC 23 7962e997c03SChanwoo Choi #define CLK_ACLK_DMAC 24 7972e997c03SChanwoo Choi #define CLK_PCLK_WDT1 25 7982e997c03SChanwoo Choi #define CLK_PCLK_WDT0 26 7992e997c03SChanwoo Choi #define CLK_PCLK_SFR1 27 8002e997c03SChanwoo Choi #define CLK_PCLK_SMMU_LPASSX 28 8012e997c03SChanwoo Choi #define CLK_PCLK_GPIO_AUD 29 8022e997c03SChanwoo Choi #define CLK_PCLK_PMU_AUD 30 8032e997c03SChanwoo Choi #define CLK_PCLK_SYSREG_AUD 31 8042e997c03SChanwoo Choi #define CLK_PCLK_AUD_SLIMBUS 32 8052e997c03SChanwoo Choi #define CLK_PCLK_AUD_UART 33 8062e997c03SChanwoo Choi #define CLK_PCLK_AUD_PCM 34 8072e997c03SChanwoo Choi #define CLK_PCLK_AUD_I2S 35 8082e997c03SChanwoo Choi #define CLK_PCLK_TIMER 36 8092e997c03SChanwoo Choi #define CLK_PCLK_SFR0_CTRL 37 8102e997c03SChanwoo Choi #define CLK_ATCLK_AUD 38 8112e997c03SChanwoo Choi #define CLK_PCLK_DBG_AUD 39 8122e997c03SChanwoo Choi #define CLK_SCLK_AUD_CA5 40 8132e997c03SChanwoo Choi #define CLK_SCLK_JTAG_TCK 41 8142e997c03SChanwoo Choi #define CLK_SCLK_SLIMBUS_CLKIN 42 8152e997c03SChanwoo Choi #define CLK_SCLK_AUD_SLIMBUS 43 8162e997c03SChanwoo Choi #define CLK_SCLK_AUD_UART 44 8172e997c03SChanwoo Choi #define CLK_SCLK_AUD_PCM 45 8182e997c03SChanwoo Choi #define CLK_SCLK_I2S_BCLK 46 8192e997c03SChanwoo Choi #define CLK_SCLK_AUD_I2S 47 8202e997c03SChanwoo Choi 8212e997c03SChanwoo Choi #define AUD_NR_CLK 48 8222e997c03SChanwoo Choi 8235785d6e6SChanwoo Choi /* CMU_BUS{0|1|2} */ 8245785d6e6SChanwoo Choi #define CLK_DIV_PCLK_BUS_133 1 8255785d6e6SChanwoo Choi 8265785d6e6SChanwoo Choi #define CLK_ACLK_AHB2APB_BUSP 2 8275785d6e6SChanwoo Choi #define CLK_ACLK_BUSNP_133 3 8285785d6e6SChanwoo Choi #define CLK_ACLK_BUSND_400 4 8295785d6e6SChanwoo Choi #define CLK_PCLK_BUSSRVND_133 5 8305785d6e6SChanwoo Choi #define CLK_PCLK_PMU_BUS 6 8315785d6e6SChanwoo Choi #define CLK_PCLK_SYSREG_BUS 7 8325785d6e6SChanwoo Choi 8335785d6e6SChanwoo Choi #define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */ 8345785d6e6SChanwoo Choi #define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ 8355785d6e6SChanwoo Choi #define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ 8365785d6e6SChanwoo Choi 8375785d6e6SChanwoo Choi #define BUSx_NR_CLK 11 8385785d6e6SChanwoo Choi 839453e519eSChanwoo Choi /* CMU_G3D */ 840453e519eSChanwoo Choi #define CLK_FOUT_G3D_PLL 1 841453e519eSChanwoo Choi 842453e519eSChanwoo Choi #define CLK_MOUT_ACLK_G3D_400 2 843453e519eSChanwoo Choi #define CLK_MOUT_G3D_PLL 3 844453e519eSChanwoo Choi 845453e519eSChanwoo Choi #define CLK_DIV_SCLK_HPM_G3D 4 846453e519eSChanwoo Choi #define CLK_DIV_PCLK_G3D 5 847453e519eSChanwoo Choi #define CLK_DIV_ACLK_G3D 6 848453e519eSChanwoo Choi #define CLK_ACLK_BTS_G3D1 7 849453e519eSChanwoo Choi #define CLK_ACLK_BTS_G3D0 8 850453e519eSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_G3D 9 851453e519eSChanwoo Choi #define CLK_ACLK_ASYNCAPBM_G3D 10 852453e519eSChanwoo Choi #define CLK_ACLK_AHB2APB_G3DP 11 853453e519eSChanwoo Choi #define CLK_ACLK_G3DNP_150 12 854453e519eSChanwoo Choi #define CLK_ACLK_G3DND_600 13 855453e519eSChanwoo Choi #define CLK_ACLK_G3D 14 856453e519eSChanwoo Choi #define CLK_PCLK_BTS_G3D1 15 857453e519eSChanwoo Choi #define CLK_PCLK_BTS_G3D0 16 858453e519eSChanwoo Choi #define CLK_PCLK_PMU_G3D 17 859453e519eSChanwoo Choi #define CLK_PCLK_SYSREG_G3D 18 860453e519eSChanwoo Choi #define CLK_SCLK_HPM_G3D 19 861453e519eSChanwoo Choi 862453e519eSChanwoo Choi #define G3D_NR_CLK 20 863453e519eSChanwoo Choi 8642a2f33e8SChanwoo Choi /* CMU_GSCL */ 8652a2f33e8SChanwoo Choi #define CLK_MOUT_ACLK_GSCL_111_USER 1 8662a2f33e8SChanwoo Choi #define CLK_MOUT_ACLK_GSCL_333_USER 2 8672a2f33e8SChanwoo Choi 8682a2f33e8SChanwoo Choi #define CLK_ACLK_BTS_GSCL2 3 8692a2f33e8SChanwoo Choi #define CLK_ACLK_BTS_GSCL1 4 8702a2f33e8SChanwoo Choi #define CLK_ACLK_BTS_GSCL0 5 8712a2f33e8SChanwoo Choi #define CLK_ACLK_AHB2APB_GSCLP 6 8722a2f33e8SChanwoo Choi #define CLK_ACLK_XIU_GSCLX 7 8732a2f33e8SChanwoo Choi #define CLK_ACLK_GSCLNP_111 8 8742a2f33e8SChanwoo Choi #define CLK_ACLK_GSCLRTND_333 9 8752a2f33e8SChanwoo Choi #define CLK_ACLK_GSCLBEND_333 10 8762a2f33e8SChanwoo Choi #define CLK_ACLK_GSD 11 8772a2f33e8SChanwoo Choi #define CLK_ACLK_GSCL2 12 8782a2f33e8SChanwoo Choi #define CLK_ACLK_GSCL1 13 8792a2f33e8SChanwoo Choi #define CLK_ACLK_GSCL0 14 8802a2f33e8SChanwoo Choi #define CLK_ACLK_SMMU_GSCL0 15 8812a2f33e8SChanwoo Choi #define CLK_ACLK_SMMU_GSCL1 16 8822a2f33e8SChanwoo Choi #define CLK_ACLK_SMMU_GSCL2 17 8832a2f33e8SChanwoo Choi #define CLK_PCLK_BTS_GSCL2 18 8842a2f33e8SChanwoo Choi #define CLK_PCLK_BTS_GSCL1 19 8852a2f33e8SChanwoo Choi #define CLK_PCLK_BTS_GSCL0 20 8862a2f33e8SChanwoo Choi #define CLK_PCLK_PMU_GSCL 21 8872a2f33e8SChanwoo Choi #define CLK_PCLK_SYSREG_GSCL 22 8882a2f33e8SChanwoo Choi #define CLK_PCLK_GSCL2 23 8892a2f33e8SChanwoo Choi #define CLK_PCLK_GSCL1 24 8902a2f33e8SChanwoo Choi #define CLK_PCLK_GSCL0 25 8912a2f33e8SChanwoo Choi #define CLK_PCLK_SMMU_GSCL0 26 8922a2f33e8SChanwoo Choi #define CLK_PCLK_SMMU_GSCL1 27 8932a2f33e8SChanwoo Choi #define CLK_PCLK_SMMU_GSCL2 28 8942a2f33e8SChanwoo Choi 8952a2f33e8SChanwoo Choi #define GSCL_NR_CLK 29 8962a2f33e8SChanwoo Choi 897df40a13cSChanwoo Choi /* CMU_APOLLO */ 898df40a13cSChanwoo Choi #define CLK_FOUT_APOLLO_PLL 1 899df40a13cSChanwoo Choi 900df40a13cSChanwoo Choi #define CLK_MOUT_APOLLO_PLL 2 901df40a13cSChanwoo Choi #define CLK_MOUT_BUS_PLL_APOLLO_USER 3 902df40a13cSChanwoo Choi #define CLK_MOUT_APOLLO 4 903df40a13cSChanwoo Choi 904df40a13cSChanwoo Choi #define CLK_DIV_CNTCLK_APOLLO 5 905df40a13cSChanwoo Choi #define CLK_DIV_PCLK_DBG_APOLLO 6 906df40a13cSChanwoo Choi #define CLK_DIV_ATCLK_APOLLO 7 907df40a13cSChanwoo Choi #define CLK_DIV_PCLK_APOLLO 8 908df40a13cSChanwoo Choi #define CLK_DIV_ACLK_APOLLO 9 909df40a13cSChanwoo Choi #define CLK_DIV_APOLLO2 10 910df40a13cSChanwoo Choi #define CLK_DIV_APOLLO1 11 911df40a13cSChanwoo Choi #define CLK_DIV_SCLK_HPM_APOLLO 12 912df40a13cSChanwoo Choi #define CLK_DIV_APOLLO_PLL 13 913df40a13cSChanwoo Choi 914df40a13cSChanwoo Choi #define CLK_ACLK_ATBDS_APOLLO_3 14 915df40a13cSChanwoo Choi #define CLK_ACLK_ATBDS_APOLLO_2 15 916df40a13cSChanwoo Choi #define CLK_ACLK_ATBDS_APOLLO_1 16 917df40a13cSChanwoo Choi #define CLK_ACLK_ATBDS_APOLLO_0 17 918df40a13cSChanwoo Choi #define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18 919df40a13cSChanwoo Choi #define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19 920df40a13cSChanwoo Choi #define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20 921df40a13cSChanwoo Choi #define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21 922df40a13cSChanwoo Choi #define CLK_ACLK_ASYNCACES_APOLLO_CCI 22 923df40a13cSChanwoo Choi #define CLK_ACLK_AHB2APB_APOLLOP 23 924df40a13cSChanwoo Choi #define CLK_ACLK_APOLLONP_200 24 925df40a13cSChanwoo Choi #define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25 926df40a13cSChanwoo Choi #define CLK_PCLK_PMU_APOLLO 26 927df40a13cSChanwoo Choi #define CLK_PCLK_SYSREG_APOLLO 27 928df40a13cSChanwoo Choi #define CLK_CNTCLK_APOLLO 28 929df40a13cSChanwoo Choi #define CLK_SCLK_HPM_APOLLO 29 930df40a13cSChanwoo Choi #define CLK_SCLK_APOLLO 30 931df40a13cSChanwoo Choi 932df40a13cSChanwoo Choi #define APOLLO_NR_CLK 31 933df40a13cSChanwoo Choi 9346c5d76d1SChanwoo Choi /* CMU_ATLAS */ 9356c5d76d1SChanwoo Choi #define CLK_FOUT_ATLAS_PLL 1 9366c5d76d1SChanwoo Choi 9376c5d76d1SChanwoo Choi #define CLK_MOUT_ATLAS_PLL 2 9386c5d76d1SChanwoo Choi #define CLK_MOUT_BUS_PLL_ATLAS_USER 3 9396c5d76d1SChanwoo Choi #define CLK_MOUT_ATLAS 4 9406c5d76d1SChanwoo Choi 9416c5d76d1SChanwoo Choi #define CLK_DIV_CNTCLK_ATLAS 5 9426c5d76d1SChanwoo Choi #define CLK_DIV_PCLK_DBG_ATLAS 6 9436c5d76d1SChanwoo Choi #define CLK_DIV_ATCLK_ATLASO 7 9446c5d76d1SChanwoo Choi #define CLK_DIV_PCLK_ATLAS 8 9456c5d76d1SChanwoo Choi #define CLK_DIV_ACLK_ATLAS 9 9466c5d76d1SChanwoo Choi #define CLK_DIV_ATLAS2 10 9476c5d76d1SChanwoo Choi #define CLK_DIV_ATLAS1 11 9486c5d76d1SChanwoo Choi #define CLK_DIV_SCLK_HPM_ATLAS 12 9496c5d76d1SChanwoo Choi #define CLK_DIV_ATLAS_PLL 13 9506c5d76d1SChanwoo Choi 9516c5d76d1SChanwoo Choi #define CLK_ACLK_ATB_AUD_CSSYS 14 9526c5d76d1SChanwoo Choi #define CLK_ACLK_ATB_APOLLO3_CSSYS 15 9536c5d76d1SChanwoo Choi #define CLK_ACLK_ATB_APOLLO2_CSSYS 16 9546c5d76d1SChanwoo Choi #define CLK_ACLK_ATB_APOLLO1_CSSYS 17 9556c5d76d1SChanwoo Choi #define CLK_ACLK_ATB_APOLLO0_CSSYS 18 9566c5d76d1SChanwoo Choi #define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19 9576c5d76d1SChanwoo Choi #define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20 9586c5d76d1SChanwoo Choi #define CLK_ACLK_ASYNCACES_ATLAS_CCI 21 9596c5d76d1SChanwoo Choi #define CLK_ACLK_AHB2APB_ATLASP 22 9606c5d76d1SChanwoo Choi #define CLK_ACLK_ATLASNP_200 23 9616c5d76d1SChanwoo Choi #define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24 9626c5d76d1SChanwoo Choi #define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25 9636c5d76d1SChanwoo Choi #define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26 9646c5d76d1SChanwoo Choi #define CLK_PCLK_PMU_ATLAS 27 9656c5d76d1SChanwoo Choi #define CLK_PCLK_SYSREG_ATLAS 28 9666c5d76d1SChanwoo Choi #define CLK_PCLK_SECJTAG 29 9676c5d76d1SChanwoo Choi #define CLK_CNTCLK_ATLAS 30 9686c5d76d1SChanwoo Choi #define CLK_SCLK_FREQ_DET_ATLAS_PLL 31 9696c5d76d1SChanwoo Choi #define CLK_SCLK_HPM_ATLAS 32 9706c5d76d1SChanwoo Choi #define CLK_TRACECLK 33 9716c5d76d1SChanwoo Choi #define CLK_CTMCLK 34 9726c5d76d1SChanwoo Choi #define CLK_HCLK_CSSYS 35 9736c5d76d1SChanwoo Choi #define CLK_PCLK_DBG_CSSYS 36 9746c5d76d1SChanwoo Choi #define CLK_PCLK_DBG 37 9756c5d76d1SChanwoo Choi #define CLK_ATCLK 38 9766c5d76d1SChanwoo Choi #define CLK_SCLK_ATLAS 39 9776c5d76d1SChanwoo Choi 9786c5d76d1SChanwoo Choi #define ATLAS_NR_CLK 40 9796c5d76d1SChanwoo Choi 980b274bbfdSChanwoo Choi /* CMU_MSCL */ 981b274bbfdSChanwoo Choi #define CLK_MOUT_SCLK_JPEG_USER 1 982b274bbfdSChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_USER 2 983b274bbfdSChanwoo Choi #define CLK_MOUT_SCLK_JPEG 3 984b274bbfdSChanwoo Choi 985b274bbfdSChanwoo Choi #define CLK_DIV_PCLK_MSCL 4 986b274bbfdSChanwoo Choi 987b274bbfdSChanwoo Choi #define CLK_ACLK_BTS_JPEG 5 988b274bbfdSChanwoo Choi #define CLK_ACLK_BTS_M2MSCALER1 6 989b274bbfdSChanwoo Choi #define CLK_ACLK_BTS_M2MSCALER0 7 990b274bbfdSChanwoo Choi #define CLK_ACLK_AHB2APB_MSCL0P 8 991b274bbfdSChanwoo Choi #define CLK_ACLK_XIU_MSCLX 9 992b274bbfdSChanwoo Choi #define CLK_ACLK_MSCLNP_100 10 993b274bbfdSChanwoo Choi #define CLK_ACLK_MSCLND_400 11 994b274bbfdSChanwoo Choi #define CLK_ACLK_JPEG 12 995b274bbfdSChanwoo Choi #define CLK_ACLK_M2MSCALER1 13 996b274bbfdSChanwoo Choi #define CLK_ACLK_M2MSCALER0 14 997b274bbfdSChanwoo Choi #define CLK_ACLK_SMMU_M2MSCALER0 15 998b274bbfdSChanwoo Choi #define CLK_ACLK_SMMU_M2MSCALER1 16 999b274bbfdSChanwoo Choi #define CLK_ACLK_SMMU_JPEG 17 1000b274bbfdSChanwoo Choi #define CLK_PCLK_BTS_JPEG 18 1001b274bbfdSChanwoo Choi #define CLK_PCLK_BTS_M2MSCALER1 19 1002b274bbfdSChanwoo Choi #define CLK_PCLK_BTS_M2MSCALER0 20 1003b274bbfdSChanwoo Choi #define CLK_PCLK_PMU_MSCL 21 1004b274bbfdSChanwoo Choi #define CLK_PCLK_SYSREG_MSCL 22 1005b274bbfdSChanwoo Choi #define CLK_PCLK_JPEG 23 1006b274bbfdSChanwoo Choi #define CLK_PCLK_M2MSCALER1 24 1007b274bbfdSChanwoo Choi #define CLK_PCLK_M2MSCALER0 25 1008b274bbfdSChanwoo Choi #define CLK_PCLK_SMMU_M2MSCALER0 26 1009b274bbfdSChanwoo Choi #define CLK_PCLK_SMMU_M2MSCALER1 27 1010b274bbfdSChanwoo Choi #define CLK_PCLK_SMMU_JPEG 28 1011b274bbfdSChanwoo Choi #define CLK_SCLK_JPEG 29 1012b274bbfdSChanwoo Choi 1013b274bbfdSChanwoo Choi #define MSCL_NR_CLK 30 1014b274bbfdSChanwoo Choi 10159910b6bbSChanwoo Choi /* CMU_MFC */ 10169910b6bbSChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_USER 1 10179910b6bbSChanwoo Choi 10189910b6bbSChanwoo Choi #define CLK_DIV_PCLK_MFC 2 10199910b6bbSChanwoo Choi 10209910b6bbSChanwoo Choi #define CLK_ACLK_BTS_MFC_1 3 10219910b6bbSChanwoo Choi #define CLK_ACLK_BTS_MFC_0 4 10229910b6bbSChanwoo Choi #define CLK_ACLK_AHB2APB_MFCP 5 10239910b6bbSChanwoo Choi #define CLK_ACLK_XIU_MFCX 6 10249910b6bbSChanwoo Choi #define CLK_ACLK_MFCNP_100 7 10259910b6bbSChanwoo Choi #define CLK_ACLK_MFCND_400 8 10269910b6bbSChanwoo Choi #define CLK_ACLK_MFC 9 10279910b6bbSChanwoo Choi #define CLK_ACLK_SMMU_MFC_1 10 10289910b6bbSChanwoo Choi #define CLK_ACLK_SMMU_MFC_0 11 10299910b6bbSChanwoo Choi #define CLK_PCLK_BTS_MFC_1 12 10309910b6bbSChanwoo Choi #define CLK_PCLK_BTS_MFC_0 13 10319910b6bbSChanwoo Choi #define CLK_PCLK_PMU_MFC 14 10329910b6bbSChanwoo Choi #define CLK_PCLK_SYSREG_MFC 15 10339910b6bbSChanwoo Choi #define CLK_PCLK_MFC 16 10349910b6bbSChanwoo Choi #define CLK_PCLK_SMMU_MFC_1 17 10359910b6bbSChanwoo Choi #define CLK_PCLK_SMMU_MFC_0 18 10369910b6bbSChanwoo Choi 10379910b6bbSChanwoo Choi #define MFC_NR_CLK 19 10389910b6bbSChanwoo Choi 103945e58aa5SChanwoo Choi /* CMU_HEVC */ 104045e58aa5SChanwoo Choi #define CLK_MOUT_ACLK_HEVC_400_USER 1 104145e58aa5SChanwoo Choi 104245e58aa5SChanwoo Choi #define CLK_DIV_PCLK_HEVC 2 104345e58aa5SChanwoo Choi 104445e58aa5SChanwoo Choi #define CLK_ACLK_BTS_HEVC_1 3 104545e58aa5SChanwoo Choi #define CLK_ACLK_BTS_HEVC_0 4 104645e58aa5SChanwoo Choi #define CLK_ACLK_AHB2APB_HEVCP 5 104745e58aa5SChanwoo Choi #define CLK_ACLK_XIU_HEVCX 6 104845e58aa5SChanwoo Choi #define CLK_ACLK_HEVCNP_100 7 104945e58aa5SChanwoo Choi #define CLK_ACLK_HEVCND_400 8 105045e58aa5SChanwoo Choi #define CLK_ACLK_HEVC 9 105145e58aa5SChanwoo Choi #define CLK_ACLK_SMMU_HEVC_1 10 105245e58aa5SChanwoo Choi #define CLK_ACLK_SMMU_HEVC_0 11 105345e58aa5SChanwoo Choi #define CLK_PCLK_BTS_HEVC_1 12 105445e58aa5SChanwoo Choi #define CLK_PCLK_BTS_HEVC_0 13 105545e58aa5SChanwoo Choi #define CLK_PCLK_PMU_HEVC 14 105645e58aa5SChanwoo Choi #define CLK_PCLK_SYSREG_HEVC 15 105745e58aa5SChanwoo Choi #define CLK_PCLK_HEVC 16 105845e58aa5SChanwoo Choi #define CLK_PCLK_SMMU_HEVC_1 17 105945e58aa5SChanwoo Choi #define CLK_PCLK_SMMU_HEVC_0 18 106045e58aa5SChanwoo Choi 106145e58aa5SChanwoo Choi #define HEVC_NR_CLK 19 106245e58aa5SChanwoo Choi 10638e46c4b8SChanwoo Choi /* CMU_ISP */ 10648e46c4b8SChanwoo Choi #define CLK_MOUT_ACLK_ISP_DIS_400_USER 1 10658e46c4b8SChanwoo Choi #define CLK_MOUT_ACLK_ISP_400_USER 2 10668e46c4b8SChanwoo Choi 10678e46c4b8SChanwoo Choi #define CLK_DIV_PCLK_ISP_DIS 3 10688e46c4b8SChanwoo Choi #define CLK_DIV_PCLK_ISP 4 10698e46c4b8SChanwoo Choi #define CLK_DIV_ACLK_ISP_D_200 5 10708e46c4b8SChanwoo Choi #define CLK_DIV_ACLK_ISP_C_200 6 10718e46c4b8SChanwoo Choi 10728e46c4b8SChanwoo Choi #define CLK_ACLK_ISP_D_GLUE 7 10738e46c4b8SChanwoo Choi #define CLK_ACLK_SCALERP 8 10748e46c4b8SChanwoo Choi #define CLK_ACLK_3DNR 9 10758e46c4b8SChanwoo Choi #define CLK_ACLK_DIS 10 10768e46c4b8SChanwoo Choi #define CLK_ACLK_SCALERC 11 10778e46c4b8SChanwoo Choi #define CLK_ACLK_DRC 12 10788e46c4b8SChanwoo Choi #define CLK_ACLK_ISP 13 10798e46c4b8SChanwoo Choi #define CLK_ACLK_AXIUS_SCALERP 14 10808e46c4b8SChanwoo Choi #define CLK_ACLK_AXIUS_SCALERC 15 10818e46c4b8SChanwoo Choi #define CLK_ACLK_AXIUS_DRC 16 10828e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAHBM_ISP2P 17 10838e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAHBM_ISP1P 18 10848e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DIS1 19 10858e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DIS0 20 10868e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DIS1 21 10878e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DIS0 22 10888e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ISP2P 23 10898e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ISP1P 24 10908e46c4b8SChanwoo Choi #define CLK_ACLK_AHB2APB_ISP2P 25 10918e46c4b8SChanwoo Choi #define CLK_ACLK_AHB2APB_ISP1P 26 10928e46c4b8SChanwoo Choi #define CLK_ACLK_AXI2APB_ISP2P 27 10938e46c4b8SChanwoo Choi #define CLK_ACLK_AXI2APB_ISP1P 28 10948e46c4b8SChanwoo Choi #define CLK_ACLK_XIU_ISPEX1 29 10958e46c4b8SChanwoo Choi #define CLK_ACLK_XIU_ISPEX0 30 10968e46c4b8SChanwoo Choi #define CLK_ACLK_ISPND_400 31 10978e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_SCALERP 32 10988e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_3DNR 33 10998e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_DIS1 34 11008e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_DIS0 35 11018e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_SCALERC 36 11028e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_DRC 37 11038e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_ISP 38 11048e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_SCALERP 39 11058e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_3DR 40 11068e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_DIS1 41 11078e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_DIS0 42 11088e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_SCALERC 43 11098e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_DRC 44 11108e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_ISP 45 11118e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_SCALERP 46 11128e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_3DNR 47 11138e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_DIS1 48 11148e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_DIS0 49 11158e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_SCALERC 50 11168e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_DRC 51 11178e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_ISP 52 11188e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_SCALERP 53 11198e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_3DNR 54 11208e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_DIS1 55 11218e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_DIS0 56 11228e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_SCALERC 57 11238e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_DRC 58 11248e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_ISP 59 11258e46c4b8SChanwoo Choi #define CLK_PCLK_ASYNCAXI_DIS1 60 11268e46c4b8SChanwoo Choi #define CLK_PCLK_ASYNCAXI_DIS0 61 11278e46c4b8SChanwoo Choi #define CLK_PCLK_PMU_ISP 62 11288e46c4b8SChanwoo Choi #define CLK_PCLK_SYSREG_ISP 63 11298e46c4b8SChanwoo Choi #define CLK_PCLK_CMU_ISP_LOCAL 64 11308e46c4b8SChanwoo Choi #define CLK_PCLK_SCALERP 65 11318e46c4b8SChanwoo Choi #define CLK_PCLK_3DNR 66 11328e46c4b8SChanwoo Choi #define CLK_PCLK_DIS_CORE 67 11338e46c4b8SChanwoo Choi #define CLK_PCLK_DIS 68 11348e46c4b8SChanwoo Choi #define CLK_PCLK_SCALERC 69 11358e46c4b8SChanwoo Choi #define CLK_PCLK_DRC 70 11368e46c4b8SChanwoo Choi #define CLK_PCLK_ISP 71 11378e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCS_DIS 72 11388e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCM_DIS 73 11398e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCS_SCALERP 74 11408e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCM_ISPD 75 11418e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCS_ISPC 76 11428e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCM_ISPC 77 11438e46c4b8SChanwoo Choi 11448e46c4b8SChanwoo Choi #define ISP_NR_CLK 78 11458e46c4b8SChanwoo Choi 11466958f22fSChanwoo Choi /* CMU_CAM0 */ 11476958f22fSChanwoo Choi #define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1 11486958f22fSChanwoo Choi #define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2 11496958f22fSChanwoo Choi 11506958f22fSChanwoo Choi #define CLK_MOUT_ACLK_CAM0_333_USER 3 11516958f22fSChanwoo Choi #define CLK_MOUT_ACLK_CAM0_400_USER 4 11526958f22fSChanwoo Choi #define CLK_MOUT_ACLK_CAM0_552_USER 5 11536958f22fSChanwoo Choi #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER 6 11546958f22fSChanwoo Choi #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER 7 11556958f22fSChanwoo Choi #define CLK_MOUT_ACLK_LITE_D_B 8 11566958f22fSChanwoo Choi #define CLK_MOUT_ACLK_LITE_D_A 9 11576958f22fSChanwoo Choi #define CLK_MOUT_ACLK_LITE_B_B 10 11586958f22fSChanwoo Choi #define CLK_MOUT_ACLK_LITE_B_A 11 11596958f22fSChanwoo Choi #define CLK_MOUT_ACLK_LITE_A_B 12 11606958f22fSChanwoo Choi #define CLK_MOUT_ACLK_LITE_A_A 13 11616958f22fSChanwoo Choi #define CLK_MOUT_ACLK_CAM0_400 14 11626958f22fSChanwoo Choi #define CLK_MOUT_ACLK_CSIS1_B 15 11636958f22fSChanwoo Choi #define CLK_MOUT_ACLK_CSIS1_A 16 11646958f22fSChanwoo Choi #define CLK_MOUT_ACLK_CSIS0_B 17 11656958f22fSChanwoo Choi #define CLK_MOUT_ACLK_CSIS0_A 18 11666958f22fSChanwoo Choi #define CLK_MOUT_ACLK_3AA1_B 19 11676958f22fSChanwoo Choi #define CLK_MOUT_ACLK_3AA1_A 20 11686958f22fSChanwoo Choi #define CLK_MOUT_ACLK_3AA0_B 21 11696958f22fSChanwoo Choi #define CLK_MOUT_ACLK_3AA0_A 22 11706958f22fSChanwoo Choi #define CLK_MOUT_SCLK_LITE_FREECNT_C 23 11716958f22fSChanwoo Choi #define CLK_MOUT_SCLK_LITE_FREECNT_B 24 11726958f22fSChanwoo Choi #define CLK_MOUT_SCLK_LITE_FREECNT_A 25 11736958f22fSChanwoo Choi #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B 26 11746958f22fSChanwoo Choi #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A 27 11756958f22fSChanwoo Choi #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B 28 11766958f22fSChanwoo Choi #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A 29 11776958f22fSChanwoo Choi 11786958f22fSChanwoo Choi #define CLK_DIV_PCLK_CAM0_50 30 11796958f22fSChanwoo Choi #define CLK_DIV_ACLK_CAM0_200 31 11806958f22fSChanwoo Choi #define CLK_DIV_ACLK_CAM0_BUS_400 32 11816958f22fSChanwoo Choi #define CLK_DIV_PCLK_LITE_D 33 11826958f22fSChanwoo Choi #define CLK_DIV_ACLK_LITE_D 34 11836958f22fSChanwoo Choi #define CLK_DIV_PCLK_LITE_B 35 11846958f22fSChanwoo Choi #define CLK_DIV_ACLK_LITE_B 36 11856958f22fSChanwoo Choi #define CLK_DIV_PCLK_LITE_A 37 11866958f22fSChanwoo Choi #define CLK_DIV_ACLK_LITE_A 38 11876958f22fSChanwoo Choi #define CLK_DIV_ACLK_CSIS1 39 11886958f22fSChanwoo Choi #define CLK_DIV_ACLK_CSIS0 40 11896958f22fSChanwoo Choi #define CLK_DIV_PCLK_3AA1 41 11906958f22fSChanwoo Choi #define CLK_DIV_ACLK_3AA1 42 11916958f22fSChanwoo Choi #define CLK_DIV_PCLK_3AA0 43 11926958f22fSChanwoo Choi #define CLK_DIV_ACLK_3AA0 44 11936958f22fSChanwoo Choi #define CLK_DIV_SCLK_PIXELASYNC_LITE_C 45 11946958f22fSChanwoo Choi #define CLK_DIV_PCLK_PIXELASYNC_LITE_C 46 11956958f22fSChanwoo Choi #define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT 47 11966958f22fSChanwoo Choi 11976958f22fSChanwoo Choi #define CLK_ACLK_CSIS1 50 11986958f22fSChanwoo Choi #define CLK_ACLK_CSIS0 51 11996958f22fSChanwoo Choi #define CLK_ACLK_3AA1 52 12006958f22fSChanwoo Choi #define CLK_ACLK_3AA0 53 12016958f22fSChanwoo Choi #define CLK_ACLK_LITE_D 54 12026958f22fSChanwoo Choi #define CLK_ACLK_LITE_B 55 12036958f22fSChanwoo Choi #define CLK_ACLK_LITE_A 56 12046958f22fSChanwoo Choi #define CLK_ACLK_AHBSYNCDN 57 12056958f22fSChanwoo Choi #define CLK_ACLK_AXIUS_LITE_D 58 12066958f22fSChanwoo Choi #define CLK_ACLK_AXIUS_LITE_B 59 12076958f22fSChanwoo Choi #define CLK_ACLK_AXIUS_LITE_A 60 12086958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBM_3AA1 61 12096958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_3AA1 62 12106958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBM_3AA0 63 12116958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_3AA0 64 12126958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBM_LITE_D 65 12136958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_LITE_D 66 12146958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBM_LITE_B 67 12156958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_LITE_B 68 12166958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBM_LITE_A 69 12176958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_LITE_A 70 12186958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ISP0P 71 12196958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_3AA1 72 12206958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_3AA1 73 12216958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_3AA0 74 12226958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_3AA0 75 12236958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_LITE_D 76 12246958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_LITE_D 77 12256958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_LITE_B 78 12266958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_LITE_B 79 12276958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_LITE_A 80 12286958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_LITE_A 81 12296958f22fSChanwoo Choi #define CLK_ACLK_AHB2APB_ISPSFRP 82 12306958f22fSChanwoo Choi #define CLK_ACLK_AXI2APB_ISP0P 83 12316958f22fSChanwoo Choi #define CLK_ACLK_AXI2AHB_ISP0P 84 12326958f22fSChanwoo Choi #define CLK_ACLK_XIU_IS0X 85 12336958f22fSChanwoo Choi #define CLK_ACLK_XIU_ISP0EX 86 12346958f22fSChanwoo Choi #define CLK_ACLK_CAM0NP_276 87 12356958f22fSChanwoo Choi #define CLK_ACLK_CAM0ND_400 88 12366958f22fSChanwoo Choi #define CLK_ACLK_SMMU_3AA1 89 12376958f22fSChanwoo Choi #define CLK_ACLK_SMMU_3AA0 90 12386958f22fSChanwoo Choi #define CLK_ACLK_SMMU_LITE_D 91 12396958f22fSChanwoo Choi #define CLK_ACLK_SMMU_LITE_B 92 12406958f22fSChanwoo Choi #define CLK_ACLK_SMMU_LITE_A 93 12416958f22fSChanwoo Choi #define CLK_ACLK_BTS_3AA1 94 12426958f22fSChanwoo Choi #define CLK_ACLK_BTS_3AA0 95 12436958f22fSChanwoo Choi #define CLK_ACLK_BTS_LITE_D 96 12446958f22fSChanwoo Choi #define CLK_ACLK_BTS_LITE_B 97 12456958f22fSChanwoo Choi #define CLK_ACLK_BTS_LITE_A 98 12466958f22fSChanwoo Choi #define CLK_PCLK_SMMU_3AA1 99 12476958f22fSChanwoo Choi #define CLK_PCLK_SMMU_3AA0 100 12486958f22fSChanwoo Choi #define CLK_PCLK_SMMU_LITE_D 101 12496958f22fSChanwoo Choi #define CLK_PCLK_SMMU_LITE_B 102 12506958f22fSChanwoo Choi #define CLK_PCLK_SMMU_LITE_A 103 12516958f22fSChanwoo Choi #define CLK_PCLK_BTS_3AA1 104 12526958f22fSChanwoo Choi #define CLK_PCLK_BTS_3AA0 105 12536958f22fSChanwoo Choi #define CLK_PCLK_BTS_LITE_D 106 12546958f22fSChanwoo Choi #define CLK_PCLK_BTS_LITE_B 107 12556958f22fSChanwoo Choi #define CLK_PCLK_BTS_LITE_A 108 12566958f22fSChanwoo Choi #define CLK_PCLK_ASYNCAXI_CAM1 109 12576958f22fSChanwoo Choi #define CLK_PCLK_ASYNCAXI_3AA1 110 12586958f22fSChanwoo Choi #define CLK_PCLK_ASYNCAXI_3AA0 111 12596958f22fSChanwoo Choi #define CLK_PCLK_ASYNCAXI_LITE_D 112 12606958f22fSChanwoo Choi #define CLK_PCLK_ASYNCAXI_LITE_B 113 12616958f22fSChanwoo Choi #define CLK_PCLK_ASYNCAXI_LITE_A 114 12626958f22fSChanwoo Choi #define CLK_PCLK_PMU_CAM0 115 12636958f22fSChanwoo Choi #define CLK_PCLK_SYSREG_CAM0 116 12646958f22fSChanwoo Choi #define CLK_PCLK_CMU_CAM0_LOCAL 117 12656958f22fSChanwoo Choi #define CLK_PCLK_CSIS1 118 12666958f22fSChanwoo Choi #define CLK_PCLK_CSIS0 119 12676958f22fSChanwoo Choi #define CLK_PCLK_3AA1 120 12686958f22fSChanwoo Choi #define CLK_PCLK_3AA0 121 12696958f22fSChanwoo Choi #define CLK_PCLK_LITE_D 122 12706958f22fSChanwoo Choi #define CLK_PCLK_LITE_B 123 12716958f22fSChanwoo Choi #define CLK_PCLK_LITE_A 124 12726958f22fSChanwoo Choi #define CLK_PHYCLK_RXBYTECLKHS0_S4 125 12736958f22fSChanwoo Choi #define CLK_PHYCLK_RXBYTECLKHS0_S2A 126 12746958f22fSChanwoo Choi #define CLK_SCLK_LITE_FREECNT 127 12756958f22fSChanwoo Choi #define CLK_SCLK_PIXELASYNCM_3AA1 128 12766958f22fSChanwoo Choi #define CLK_SCLK_PIXELASYNCM_3AA0 129 12776958f22fSChanwoo Choi #define CLK_SCLK_PIXELASYNCS_3AA0 130 12786958f22fSChanwoo Choi #define CLK_SCLK_PIXELASYNCM_LITE_C 131 12796958f22fSChanwoo Choi #define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132 12806958f22fSChanwoo Choi #define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133 12816958f22fSChanwoo Choi 12826958f22fSChanwoo Choi #define CAM0_NR_CLK 134 12836958f22fSChanwoo Choi 1284a5958a93SChanwoo Choi /* CMU_CAM1 */ 1285a5958a93SChanwoo Choi #define CLK_PHYCLK_RXBYTEECLKHS0_S2B 1 1286a5958a93SChanwoo Choi 1287a5958a93SChanwoo Choi #define CLK_MOUT_SCLK_ISP_UART_USER 2 1288a5958a93SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI1_USER 3 1289a5958a93SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI0_USER 4 1290a5958a93SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_333_USER 5 1291a5958a93SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_400_USER 6 1292a5958a93SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_USER 7 1293a5958a93SChanwoo Choi #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER 8 1294a5958a93SChanwoo Choi #define CLK_MOUT_ACLK_CSIS2_B 9 1295a5958a93SChanwoo Choi #define CLK_MOUT_ACLK_CSIS2_A 10 1296a5958a93SChanwoo Choi #define CLK_MOUT_ACLK_FD_B 11 1297a5958a93SChanwoo Choi #define CLK_MOUT_ACLK_FD_A 12 1298a5958a93SChanwoo Choi #define CLK_MOUT_ACLK_LITE_C_B 13 1299a5958a93SChanwoo Choi #define CLK_MOUT_ACLK_LITE_C_A 14 1300a5958a93SChanwoo Choi 1301a5958a93SChanwoo Choi #define CLK_DIV_SCLK_ISP_WPWM 15 1302a5958a93SChanwoo Choi #define CLK_DIV_PCLK_CAM1_83 16 1303a5958a93SChanwoo Choi #define CLK_DIV_PCLK_CAM1_166 17 1304a5958a93SChanwoo Choi #define CLK_DIV_PCLK_DBG_CAM1 18 1305a5958a93SChanwoo Choi #define CLK_DIV_ATCLK_CAM1 19 1306a5958a93SChanwoo Choi #define CLK_DIV_ACLK_CSIS2 20 1307a5958a93SChanwoo Choi #define CLK_DIV_PCLK_FD 21 1308a5958a93SChanwoo Choi #define CLK_DIV_ACLK_FD 22 1309a5958a93SChanwoo Choi #define CLK_DIV_PCLK_LITE_C 23 1310a5958a93SChanwoo Choi #define CLK_DIV_ACLK_LITE_C 24 1311a5958a93SChanwoo Choi 1312a5958a93SChanwoo Choi #define CLK_ACLK_ISP_GIC 25 1313a5958a93SChanwoo Choi #define CLK_ACLK_FD 26 1314a5958a93SChanwoo Choi #define CLK_ACLK_LITE_C 27 1315a5958a93SChanwoo Choi #define CLK_ACLK_CSIS2 28 1316a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAPBM_FD 29 1317a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAPBS_FD 30 1318a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAPBM_LITE_C 31 1319a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAPBS_LITE_C 32 1320a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAHBS_SFRISP2H2 33 1321a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAHBS_SFRISP2H1 34 1322a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_CA5 35 1323a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAXIS_CA5 36 1324a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAXIS_ISPX2 37 1325a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAXIS_ISPX1 38 1326a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAXIS_ISPX0 39 1327a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ISPEX 40 1328a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ISP3P 41 1329a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAXIS_ISP3P 42 1330a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_FD 43 1331a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAXIS_FD 44 1332a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_LITE_C 45 1333a5958a93SChanwoo Choi #define CLK_ACLK_ASYNCAXIS_LITE_C 46 1334a5958a93SChanwoo Choi #define CLK_ACLK_AHB2APB_ISP5P 47 1335a5958a93SChanwoo Choi #define CLK_ACLK_AHB2APB_ISP3P 48 1336a5958a93SChanwoo Choi #define CLK_ACLK_AXI2APB_ISP3P 49 1337a5958a93SChanwoo Choi #define CLK_ACLK_AHB_SFRISP2H 50 1338a5958a93SChanwoo Choi #define CLK_ACLK_AXI_ISP_HX_R 51 1339a5958a93SChanwoo Choi #define CLK_ACLK_AXI_ISP_CX_R 52 1340a5958a93SChanwoo Choi #define CLK_ACLK_AXI_ISP_HX 53 1341a5958a93SChanwoo Choi #define CLK_ACLK_AXI_ISP_CX 54 1342a5958a93SChanwoo Choi #define CLK_ACLK_XIU_ISPX 55 1343a5958a93SChanwoo Choi #define CLK_ACLK_XIU_ISPEX 56 1344a5958a93SChanwoo Choi #define CLK_ACLK_CAM1NP_333 57 1345a5958a93SChanwoo Choi #define CLK_ACLK_CAM1ND_400 58 1346a5958a93SChanwoo Choi #define CLK_ACLK_SMMU_ISPCPU 59 1347a5958a93SChanwoo Choi #define CLK_ACLK_SMMU_FD 60 1348a5958a93SChanwoo Choi #define CLK_ACLK_SMMU_LITE_C 61 1349a5958a93SChanwoo Choi #define CLK_ACLK_BTS_ISP3P 62 1350a5958a93SChanwoo Choi #define CLK_ACLK_BTS_FD 63 1351a5958a93SChanwoo Choi #define CLK_ACLK_BTS_LITE_C 64 1352a5958a93SChanwoo Choi #define CLK_ACLK_AHBDN_SFRISP2H 65 1353a5958a93SChanwoo Choi #define CLK_ACLK_AHBDN_ISP5P 66 1354a5958a93SChanwoo Choi #define CLK_ACLK_AXIUS_ISP3P 67 1355a5958a93SChanwoo Choi #define CLK_ACLK_AXIUS_FD 68 1356a5958a93SChanwoo Choi #define CLK_ACLK_AXIUS_LITE_C 69 1357a5958a93SChanwoo Choi #define CLK_PCLK_SMMU_ISPCPU 70 1358a5958a93SChanwoo Choi #define CLK_PCLK_SMMU_FD 71 1359a5958a93SChanwoo Choi #define CLK_PCLK_SMMU_LITE_C 72 1360a5958a93SChanwoo Choi #define CLK_PCLK_BTS_ISP3P 73 1361a5958a93SChanwoo Choi #define CLK_PCLK_BTS_FD 74 1362a5958a93SChanwoo Choi #define CLK_PCLK_BTS_LITE_C 75 1363a5958a93SChanwoo Choi #define CLK_PCLK_ASYNCAXIM_CA5 76 1364a5958a93SChanwoo Choi #define CLK_PCLK_ASYNCAXIM_ISPEX 77 1365a5958a93SChanwoo Choi #define CLK_PCLK_ASYNCAXIM_ISP3P 78 1366a5958a93SChanwoo Choi #define CLK_PCLK_ASYNCAXIM_FD 79 1367a5958a93SChanwoo Choi #define CLK_PCLK_ASYNCAXIM_LITE_C 80 1368a5958a93SChanwoo Choi #define CLK_PCLK_PMU_CAM1 81 1369a5958a93SChanwoo Choi #define CLK_PCLK_SYSREG_CAM1 82 1370a5958a93SChanwoo Choi #define CLK_PCLK_CMU_CAM1_LOCAL 83 1371a5958a93SChanwoo Choi #define CLK_PCLK_ISP_MCTADC 84 1372a5958a93SChanwoo Choi #define CLK_PCLK_ISP_WDT 85 1373a5958a93SChanwoo Choi #define CLK_PCLK_ISP_PWM 86 1374a5958a93SChanwoo Choi #define CLK_PCLK_ISP_UART 87 1375a5958a93SChanwoo Choi #define CLK_PCLK_ISP_MCUCTL 88 1376a5958a93SChanwoo Choi #define CLK_PCLK_ISP_SPI1 89 1377a5958a93SChanwoo Choi #define CLK_PCLK_ISP_SPI0 90 1378a5958a93SChanwoo Choi #define CLK_PCLK_ISP_I2C2 91 1379a5958a93SChanwoo Choi #define CLK_PCLK_ISP_I2C1 92 1380a5958a93SChanwoo Choi #define CLK_PCLK_ISP_I2C0 93 1381a5958a93SChanwoo Choi #define CLK_PCLK_ISP_MPWM 94 1382a5958a93SChanwoo Choi #define CLK_PCLK_FD 95 1383a5958a93SChanwoo Choi #define CLK_PCLK_LITE_C 96 1384a5958a93SChanwoo Choi #define CLK_PCLK_CSIS2 97 1385a5958a93SChanwoo Choi #define CLK_SCLK_ISP_I2C2 98 1386a5958a93SChanwoo Choi #define CLK_SCLK_ISP_I2C1 99 1387a5958a93SChanwoo Choi #define CLK_SCLK_ISP_I2C0 100 1388a5958a93SChanwoo Choi #define CLK_SCLK_ISP_PWM 101 1389a5958a93SChanwoo Choi #define CLK_PHYCLK_RXBYTECLKHS0_S2B 102 1390a5958a93SChanwoo Choi #define CLK_SCLK_LITE_C_FREECNT 103 1391a5958a93SChanwoo Choi #define CLK_SCLK_PIXELASYNCM_FD 104 1392a5958a93SChanwoo Choi #define CLK_SCLK_ISP_MCTADC 105 1393a5958a93SChanwoo Choi #define CLK_SCLK_ISP_UART 106 1394a5958a93SChanwoo Choi #define CLK_SCLK_ISP_SPI1 107 1395a5958a93SChanwoo Choi #define CLK_SCLK_ISP_SPI0 108 1396a5958a93SChanwoo Choi #define CLK_SCLK_ISP_MPWM 109 1397a5958a93SChanwoo Choi #define CLK_PCLK_DBG_ISP 110 1398a5958a93SChanwoo Choi #define CLK_ATCLK_ISP 111 1399a5958a93SChanwoo Choi #define CLK_SCLK_ISP_CA5 112 1400a5958a93SChanwoo Choi 1401a5958a93SChanwoo Choi #define CAM1_NR_CLK 113 1402a5958a93SChanwoo Choi 140396bd6224SChanwoo Choi #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 1404