196bd6224SChanwoo Choi /* 296bd6224SChanwoo Choi * Copyright (c) 2014 Samsung Electronics Co., Ltd. 396bd6224SChanwoo Choi * Author: Chanwoo Choi <cw00.choi@samsung.com> 496bd6224SChanwoo Choi * 596bd6224SChanwoo Choi * This program is free software; you can redistribute it and/or modify 696bd6224SChanwoo Choi * it under the terms of the GNU General Public License version 2 as 796bd6224SChanwoo Choi * published by the Free Software Foundation. 896bd6224SChanwoo Choi */ 996bd6224SChanwoo Choi 1096bd6224SChanwoo Choi #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 1196bd6224SChanwoo Choi #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 1296bd6224SChanwoo Choi 1396bd6224SChanwoo Choi /* CMU_TOP */ 1496bd6224SChanwoo Choi #define CLK_FOUT_ISP_PLL 1 1596bd6224SChanwoo Choi #define CLK_FOUT_AUD_PLL 2 1696bd6224SChanwoo Choi 1796bd6224SChanwoo Choi #define CLK_MOUT_AUD_PLL 10 1896bd6224SChanwoo Choi #define CLK_MOUT_ISP_PLL 11 1996bd6224SChanwoo Choi #define CLK_MOUT_AUD_PLL_USER_T 12 2096bd6224SChanwoo Choi #define CLK_MOUT_MPHY_PLL_USER 13 2196bd6224SChanwoo Choi #define CLK_MOUT_MFC_PLL_USER 14 2296bd6224SChanwoo Choi #define CLK_MOUT_BUS_PLL_USER 15 2396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_HEVC_400 16 2496bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_333 17 2596bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_B 18 2696bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_A 19 2796bd6224SChanwoo Choi #define CLK_MOUT_ACLK_ISP_DIS_400 20 2896bd6224SChanwoo Choi #define CLK_MOUT_ACLK_ISP_400 21 2996bd6224SChanwoo Choi #define CLK_MOUT_ACLK_BUS0_400 22 3096bd6224SChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_B 23 3196bd6224SChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_A 24 3296bd6224SChanwoo Choi #define CLK_MOUT_ACLK_GSCL_333 25 3396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_G2D_400_B 26 3496bd6224SChanwoo Choi #define CLK_MOUT_ACLK_G2D_400_A 27 3596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_C 28 3696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_B 29 3796bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_A 30 3896bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_B 31 3996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_A 32 4096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_B 33 4196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_A 34 4296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_D 35 4396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_C 36 4496bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_B 37 4596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_A 38 4696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI4 39 4796bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI3 40 4896bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART2 41 4996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART1 42 5096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART0 43 5196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI2 44 5296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI1 45 5396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI0 46 5423236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_C 47 5523236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_B 48 5623236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_A 49 5723236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR2 50 5823236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR1 51 5923236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR0 52 6023236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_UART 53 6123236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI1 54 6223236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI0 55 6323236496SChanwoo Choi #define CLK_MOUT_SCLK_PCIE_100 56 6423236496SChanwoo Choi #define CLK_MOUT_SCLK_UFSUNIPRO 57 6523236496SChanwoo Choi #define CLK_MOUT_SCLK_USBHOST30 58 6623236496SChanwoo Choi #define CLK_MOUT_SCLK_USBDRD30 59 6723236496SChanwoo Choi #define CLK_MOUT_SCLK_SLIMBUS 60 6823236496SChanwoo Choi #define CLK_MOUT_SCLK_SPDIF 61 6923236496SChanwoo Choi #define CLK_MOUT_SCLK_AUDIO1 62 7023236496SChanwoo Choi #define CLK_MOUT_SCLK_AUDIO0 63 7196bd6224SChanwoo Choi 7296bd6224SChanwoo Choi #define CLK_DIV_ACLK_FSYS_200 100 7396bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_SSSX_266 101 7496bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_200 102 7596bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_266 103 7696bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIC_66_B 104 7796bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIC_66_A 105 7896bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIS_66_B 106 7996bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIS_66_A 107 8096bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC1_B 108 8196bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC1_A 109 8296bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC0_B 110 8396bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC0_A 111 8496bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC2_B 112 8596bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC2_A 113 8696bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI1_B 114 8796bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI1_A 115 8896bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI0_B 116 8996bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI0_A 117 9096bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI2_B 118 9196bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI2_A 119 9296bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART2 120 9396bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART1 121 9496bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART0 122 9596bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI4_B 123 9696bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI4_A 124 9796bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI3_B 125 9896bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI3_A 126 9923236496SChanwoo Choi #define CLK_DIV_SCLK_I2S1 127 10023236496SChanwoo Choi #define CLK_DIV_SCLK_PCM1 128 10123236496SChanwoo Choi #define CLK_DIV_SCLK_AUDIO1 129 10223236496SChanwoo Choi #define CLK_DIV_SCLK_AUDIO0 130 103a29308daSChanwoo Choi #define CLK_DIV_ACLK_GSCL_111 131 104a29308daSChanwoo Choi #define CLK_DIV_ACLK_GSCL_333 132 105a29308daSChanwoo Choi #define CLK_DIV_ACLK_HEVC_400 133 106a29308daSChanwoo Choi #define CLK_DIV_ACLK_MFC_400 134 107a29308daSChanwoo Choi #define CLK_DIV_ACLK_G2D_266 135 108a29308daSChanwoo Choi #define CLK_DIV_ACLK_G2D_400 136 10996bd6224SChanwoo Choi 11096bd6224SChanwoo Choi #define CLK_ACLK_PERIC_66 200 11196bd6224SChanwoo Choi #define CLK_ACLK_PERIS_66 201 11296bd6224SChanwoo Choi #define CLK_ACLK_FSYS_200 202 11396bd6224SChanwoo Choi #define CLK_SCLK_MMC2_FSYS 203 11496bd6224SChanwoo Choi #define CLK_SCLK_MMC1_FSYS 204 11596bd6224SChanwoo Choi #define CLK_SCLK_MMC0_FSYS 205 11696bd6224SChanwoo Choi #define CLK_SCLK_SPI4_PERIC 206 11796bd6224SChanwoo Choi #define CLK_SCLK_SPI3_PERIC 207 11896bd6224SChanwoo Choi #define CLK_SCLK_UART2_PERIC 208 11996bd6224SChanwoo Choi #define CLK_SCLK_UART1_PERIC 209 12096bd6224SChanwoo Choi #define CLK_SCLK_UART0_PERIC 210 12196bd6224SChanwoo Choi #define CLK_SCLK_SPI2_PERIC 211 12296bd6224SChanwoo Choi #define CLK_SCLK_SPI1_PERIC 212 12396bd6224SChanwoo Choi #define CLK_SCLK_SPI0_PERIC 213 12423236496SChanwoo Choi #define CLK_SCLK_SPDIF_PERIC 214 12523236496SChanwoo Choi #define CLK_SCLK_I2S1_PERIC 215 12623236496SChanwoo Choi #define CLK_SCLK_PCM1_PERIC 216 12723236496SChanwoo Choi #define CLK_SCLK_SLIMBUS 217 12823236496SChanwoo Choi #define CLK_SCLK_AUDIO1 218 12923236496SChanwoo Choi #define CLK_SCLK_AUDIO0 219 130a29308daSChanwoo Choi #define CLK_ACLK_G2D_266 220 131a29308daSChanwoo Choi #define CLK_ACLK_G2D_400 221 13296bd6224SChanwoo Choi 133a29308daSChanwoo Choi #define TOP_NR_CLK 222 13496bd6224SChanwoo Choi 13596bd6224SChanwoo Choi /* CMU_CPIF */ 13696bd6224SChanwoo Choi #define CLK_FOUT_MPHY_PLL 1 13796bd6224SChanwoo Choi 13896bd6224SChanwoo Choi #define CLK_MOUT_MPHY_PLL 2 13996bd6224SChanwoo Choi 14096bd6224SChanwoo Choi #define CLK_DIV_SCLK_MPHY 10 14196bd6224SChanwoo Choi 14296bd6224SChanwoo Choi #define CLK_SCLK_MPHY_PLL 11 14396bd6224SChanwoo Choi #define CLK_SCLK_UFS_MPHY 11 14496bd6224SChanwoo Choi 14596bd6224SChanwoo Choi #define CPIF_NR_CLK 12 14696bd6224SChanwoo Choi 14796bd6224SChanwoo Choi /* CMU_MIF */ 14896bd6224SChanwoo Choi #define CLK_FOUT_MEM0_PLL 1 14996bd6224SChanwoo Choi #define CLK_FOUT_MEM1_PLL 2 15096bd6224SChanwoo Choi #define CLK_FOUT_BUS_PLL 3 15196bd6224SChanwoo Choi #define CLK_FOUT_MFC_PLL 4 15296bd6224SChanwoo Choi 15396bd6224SChanwoo Choi #define MIF_NR_CLK 5 15496bd6224SChanwoo Choi 15596bd6224SChanwoo Choi /* CMU_PERIC */ 15696bd6224SChanwoo Choi #define CLK_PCLK_SPI2 1 15796bd6224SChanwoo Choi #define CLK_PCLK_SPI1 2 15896bd6224SChanwoo Choi #define CLK_PCLK_SPI0 3 15996bd6224SChanwoo Choi #define CLK_PCLK_UART2 4 16096bd6224SChanwoo Choi #define CLK_PCLK_UART1 5 16196bd6224SChanwoo Choi #define CLK_PCLK_UART0 6 16296bd6224SChanwoo Choi #define CLK_PCLK_HSI2C3 7 16396bd6224SChanwoo Choi #define CLK_PCLK_HSI2C2 8 16496bd6224SChanwoo Choi #define CLK_PCLK_HSI2C1 9 16596bd6224SChanwoo Choi #define CLK_PCLK_HSI2C0 10 16696bd6224SChanwoo Choi #define CLK_PCLK_I2C7 11 16796bd6224SChanwoo Choi #define CLK_PCLK_I2C6 12 16896bd6224SChanwoo Choi #define CLK_PCLK_I2C5 13 16996bd6224SChanwoo Choi #define CLK_PCLK_I2C4 14 17096bd6224SChanwoo Choi #define CLK_PCLK_I2C3 15 17196bd6224SChanwoo Choi #define CLK_PCLK_I2C2 16 17296bd6224SChanwoo Choi #define CLK_PCLK_I2C1 17 17396bd6224SChanwoo Choi #define CLK_PCLK_I2C0 18 17496bd6224SChanwoo Choi #define CLK_PCLK_SPI4 19 17596bd6224SChanwoo Choi #define CLK_PCLK_SPI3 20 17696bd6224SChanwoo Choi #define CLK_PCLK_HSI2C11 21 17796bd6224SChanwoo Choi #define CLK_PCLK_HSI2C10 22 17896bd6224SChanwoo Choi #define CLK_PCLK_HSI2C9 23 17996bd6224SChanwoo Choi #define CLK_PCLK_HSI2C8 24 18096bd6224SChanwoo Choi #define CLK_PCLK_HSI2C7 25 18196bd6224SChanwoo Choi #define CLK_PCLK_HSI2C6 26 18296bd6224SChanwoo Choi #define CLK_PCLK_HSI2C5 27 18396bd6224SChanwoo Choi #define CLK_PCLK_HSI2C4 28 18496bd6224SChanwoo Choi #define CLK_SCLK_SPI4 29 18596bd6224SChanwoo Choi #define CLK_SCLK_SPI3 30 18696bd6224SChanwoo Choi #define CLK_SCLK_SPI2 31 18796bd6224SChanwoo Choi #define CLK_SCLK_SPI1 32 18896bd6224SChanwoo Choi #define CLK_SCLK_SPI0 33 18996bd6224SChanwoo Choi #define CLK_SCLK_UART2 34 19096bd6224SChanwoo Choi #define CLK_SCLK_UART1 35 19196bd6224SChanwoo Choi #define CLK_SCLK_UART0 36 192d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC2P 37 193d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC1P 38 194d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC0P 39 195d0f5de66SChanwoo Choi #define CLK_ACLK_PERICNP_66 40 196d0f5de66SChanwoo Choi #define CLK_PCLK_SCI 41 197d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_FINGER 42 198d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_ESE 43 199d0f5de66SChanwoo Choi #define CLK_PCLK_PWM 44 200d0f5de66SChanwoo Choi #define CLK_PCLK_SPDIF 45 201d0f5de66SChanwoo Choi #define CLK_PCLK_PCM1 46 202d0f5de66SChanwoo Choi #define CLK_PCLK_I2S1 47 203d0f5de66SChanwoo Choi #define CLK_PCLK_ADCIF 48 204d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_TOUCH 49 205d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_NFC 50 206d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_PERIC 51 207d0f5de66SChanwoo Choi #define CLK_PCLK_PMU_PERIC 52 208d0f5de66SChanwoo Choi #define CLK_PCLK_SYSREG_PERIC 53 209d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI4 54 210d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI3 55 211d0f5de66SChanwoo Choi #define CLK_SCLK_SCI 56 212d0f5de66SChanwoo Choi #define CLK_SCLK_SC_IN 57 213d0f5de66SChanwoo Choi #define CLK_SCLK_PWM 58 214d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI2 59 215d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI1 60 216d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI0 61 217d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_I2S1_BCLK 62 218d0f5de66SChanwoo Choi #define CLK_SCLK_SPDIF 63 219d0f5de66SChanwoo Choi #define CLK_SCLK_PCM1 64 220d0f5de66SChanwoo Choi #define CLK_SCLK_I2S1 65 22196bd6224SChanwoo Choi 222d0f5de66SChanwoo Choi #define CLK_DIV_SCLK_SCI 70 223d0f5de66SChanwoo Choi #define CLK_DIV_SCLK_SC_IN 71 224d0f5de66SChanwoo Choi 225d0f5de66SChanwoo Choi #define PERIC_NR_CLK 72 22696bd6224SChanwoo Choi 22796bd6224SChanwoo Choi /* CMU_PERIS */ 22896bd6224SChanwoo Choi #define CLK_PCLK_HPM_APBIF 1 22996bd6224SChanwoo Choi #define CLK_PCLK_TMU1_APBIF 2 23096bd6224SChanwoo Choi #define CLK_PCLK_TMU0_APBIF 3 23196bd6224SChanwoo Choi #define CLK_PCLK_PMU_PERIS 4 23296bd6224SChanwoo Choi #define CLK_PCLK_SYSREG_PERIS 5 23396bd6224SChanwoo Choi #define CLK_PCLK_CMU_TOP_APBIF 6 23496bd6224SChanwoo Choi #define CLK_PCLK_WDT_APOLLO 7 23596bd6224SChanwoo Choi #define CLK_PCLK_WDT_ATLAS 8 23696bd6224SChanwoo Choi #define CLK_PCLK_MCT 9 23796bd6224SChanwoo Choi #define CLK_PCLK_HDMI_CEC 10 23856bcf3f3SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIS1P 11 23956bcf3f3SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIS0P 12 24056bcf3f3SChanwoo Choi #define CLK_ACLK_PERISNP_66 13 24156bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC12 14 24256bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC11 15 24356bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC10 16 24456bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC9 17 24556bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC8 18 24656bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC7 19 24756bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC6 20 24856bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC5 21 24956bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC4 22 25056bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC3 23 25156bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC2 24 25256bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC1 25 25356bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC0 26 25456bcf3f3SChanwoo Choi #define CLK_PCLK_SECKEY_APBIF 27 25556bcf3f3SChanwoo Choi #define CLK_PCLK_CHIPID_APBIF 28 25656bcf3f3SChanwoo Choi #define CLK_PCLK_TOPRTC 29 25756bcf3f3SChanwoo Choi #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 25856bcf3f3SChanwoo Choi #define CLK_PCLK_ANTIRBK_CNT_APBIF 31 25956bcf3f3SChanwoo Choi #define CLK_PCLK_OTP_CON_APBIF 32 26056bcf3f3SChanwoo Choi #define CLK_SCLK_ASV_TB 33 26156bcf3f3SChanwoo Choi #define CLK_SCLK_TMU1 34 26256bcf3f3SChanwoo Choi #define CLK_SCLK_TMU0 35 26356bcf3f3SChanwoo Choi #define CLK_SCLK_SECKEY 36 26456bcf3f3SChanwoo Choi #define CLK_SCLK_CHIPID 37 26556bcf3f3SChanwoo Choi #define CLK_SCLK_TOPRTC 38 26656bcf3f3SChanwoo Choi #define CLK_SCLK_CUSTOM_EFUSE 39 26756bcf3f3SChanwoo Choi #define CLK_SCLK_ANTIRBK_CNT 40 26856bcf3f3SChanwoo Choi #define CLK_SCLK_OTP_CON 41 26996bd6224SChanwoo Choi 27056bcf3f3SChanwoo Choi #define PERIS_NR_CLK 42 27196bd6224SChanwoo Choi 27296bd6224SChanwoo Choi /* CMU_FSYS */ 27396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_FSYS_200_USER 1 27496bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_USER 2 27596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_USER 3 27696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_USER 4 27796bd6224SChanwoo Choi 27896bd6224SChanwoo Choi #define CLK_ACLK_PCIE 50 27996bd6224SChanwoo Choi #define CLK_ACLK_PDMA1 51 28096bd6224SChanwoo Choi #define CLK_ACLK_TSI 52 28196bd6224SChanwoo Choi #define CLK_ACLK_MMC2 53 28296bd6224SChanwoo Choi #define CLK_ACLK_MMC1 54 28396bd6224SChanwoo Choi #define CLK_ACLK_MMC0 55 28496bd6224SChanwoo Choi #define CLK_ACLK_UFS 56 28596bd6224SChanwoo Choi #define CLK_ACLK_USBHOST20 57 28696bd6224SChanwoo Choi #define CLK_ACLK_USBHOST30 58 28796bd6224SChanwoo Choi #define CLK_ACLK_USBDRD30 59 28896bd6224SChanwoo Choi #define CLK_ACLK_PDMA0 60 28996bd6224SChanwoo Choi #define CLK_SCLK_MMC2 61 29096bd6224SChanwoo Choi #define CLK_SCLK_MMC1 62 29196bd6224SChanwoo Choi #define CLK_SCLK_MMC0 63 29296bd6224SChanwoo Choi #define CLK_PDMA1 64 29396bd6224SChanwoo Choi #define CLK_PDMA0 65 29496bd6224SChanwoo Choi 29596bd6224SChanwoo Choi #define FSYS_NR_CLK 66 29696bd6224SChanwoo Choi 297a29308daSChanwoo Choi /* CMU_G2D */ 298a29308daSChanwoo Choi #define CLK_MUX_ACLK_G2D_266_USER 1 299a29308daSChanwoo Choi #define CLK_MUX_ACLK_G2D_400_USER 2 300a29308daSChanwoo Choi 301a29308daSChanwoo Choi #define CLK_DIV_PCLK_G2D 3 302a29308daSChanwoo Choi 303a29308daSChanwoo Choi #define CLK_ACLK_SMMU_MDMA1 4 304a29308daSChanwoo Choi #define CLK_ACLK_BTS_MDMA1 5 305a29308daSChanwoo Choi #define CLK_ACLK_BTS_G2D 6 306a29308daSChanwoo Choi #define CLK_ACLK_ALB_G2D 7 307a29308daSChanwoo Choi #define CLK_ACLK_AXIUS_G2DX 8 308a29308daSChanwoo Choi #define CLK_ACLK_ASYNCAXI_SYSX 9 309a29308daSChanwoo Choi #define CLK_ACLK_AHB2APB_G2D1P 10 310a29308daSChanwoo Choi #define CLK_ACLK_AHB2APB_G2D0P 11 311a29308daSChanwoo Choi #define CLK_ACLK_XIU_G2DX 12 312a29308daSChanwoo Choi #define CLK_ACLK_G2DNP_133 13 313a29308daSChanwoo Choi #define CLK_ACLK_G2DND_400 14 314a29308daSChanwoo Choi #define CLK_ACLK_MDMA1 15 315a29308daSChanwoo Choi #define CLK_ACLK_G2D 16 316a29308daSChanwoo Choi #define CLK_ACLK_SMMU_G2D 17 317a29308daSChanwoo Choi #define CLK_PCLK_SMMU_MDMA1 18 318a29308daSChanwoo Choi #define CLK_PCLK_BTS_MDMA1 19 319a29308daSChanwoo Choi #define CLK_PCLK_BTS_G2D 20 320a29308daSChanwoo Choi #define CLK_PCLK_ALB_G2D 21 321a29308daSChanwoo Choi #define CLK_PCLK_ASYNCAXI_SYSX 22 322a29308daSChanwoo Choi #define CLK_PCLK_PMU_G2D 23 323a29308daSChanwoo Choi #define CLK_PCLK_SYSREG_G2D 24 324a29308daSChanwoo Choi #define CLK_PCLK_G2D 25 325a29308daSChanwoo Choi #define CLK_PCLK_SMMU_G2D 26 326a29308daSChanwoo Choi 327a29308daSChanwoo Choi #define G2D_NR_CLK 27 328a29308daSChanwoo Choi 32996bd6224SChanwoo Choi #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 330