196bd6224SChanwoo Choi /* 296bd6224SChanwoo Choi * Copyright (c) 2014 Samsung Electronics Co., Ltd. 396bd6224SChanwoo Choi * Author: Chanwoo Choi <cw00.choi@samsung.com> 496bd6224SChanwoo Choi * 596bd6224SChanwoo Choi * This program is free software; you can redistribute it and/or modify 696bd6224SChanwoo Choi * it under the terms of the GNU General Public License version 2 as 796bd6224SChanwoo Choi * published by the Free Software Foundation. 896bd6224SChanwoo Choi */ 996bd6224SChanwoo Choi 1096bd6224SChanwoo Choi #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 1196bd6224SChanwoo Choi #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 1296bd6224SChanwoo Choi 1396bd6224SChanwoo Choi /* CMU_TOP */ 1496bd6224SChanwoo Choi #define CLK_FOUT_ISP_PLL 1 1596bd6224SChanwoo Choi #define CLK_FOUT_AUD_PLL 2 1696bd6224SChanwoo Choi 1796bd6224SChanwoo Choi #define CLK_MOUT_AUD_PLL 10 1896bd6224SChanwoo Choi #define CLK_MOUT_ISP_PLL 11 1996bd6224SChanwoo Choi #define CLK_MOUT_AUD_PLL_USER_T 12 2096bd6224SChanwoo Choi #define CLK_MOUT_MPHY_PLL_USER 13 2196bd6224SChanwoo Choi #define CLK_MOUT_MFC_PLL_USER 14 2296bd6224SChanwoo Choi #define CLK_MOUT_BUS_PLL_USER 15 2396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_HEVC_400 16 2496bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_333 17 2596bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_B 18 2696bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_A 19 2796bd6224SChanwoo Choi #define CLK_MOUT_ACLK_ISP_DIS_400 20 2896bd6224SChanwoo Choi #define CLK_MOUT_ACLK_ISP_400 21 2996bd6224SChanwoo Choi #define CLK_MOUT_ACLK_BUS0_400 22 3096bd6224SChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_B 23 3196bd6224SChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_A 24 3296bd6224SChanwoo Choi #define CLK_MOUT_ACLK_GSCL_333 25 3396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_G2D_400_B 26 3496bd6224SChanwoo Choi #define CLK_MOUT_ACLK_G2D_400_A 27 3596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_C 28 3696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_B 29 3796bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_A 30 3896bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_B 31 3996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_A 32 4096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_B 33 4196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_A 34 4296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_D 35 4396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_C 36 4496bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_B 37 4596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_A 38 4696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI4 39 4796bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI3 40 4896bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART2 41 4996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART1 42 5096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART0 43 5196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI2 44 5296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI1 45 5396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI0 46 5423236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_C 47 5523236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_B 48 5623236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_A 49 5723236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR2 50 5823236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR1 51 5923236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR0 52 6023236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_UART 53 6123236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI1 54 6223236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI0 55 6323236496SChanwoo Choi #define CLK_MOUT_SCLK_PCIE_100 56 6423236496SChanwoo Choi #define CLK_MOUT_SCLK_UFSUNIPRO 57 6523236496SChanwoo Choi #define CLK_MOUT_SCLK_USBHOST30 58 6623236496SChanwoo Choi #define CLK_MOUT_SCLK_USBDRD30 59 6723236496SChanwoo Choi #define CLK_MOUT_SCLK_SLIMBUS 60 6823236496SChanwoo Choi #define CLK_MOUT_SCLK_SPDIF 61 6923236496SChanwoo Choi #define CLK_MOUT_SCLK_AUDIO1 62 7023236496SChanwoo Choi #define CLK_MOUT_SCLK_AUDIO0 63 712a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_HDMI_SPDIF 64 7296bd6224SChanwoo Choi 7396bd6224SChanwoo Choi #define CLK_DIV_ACLK_FSYS_200 100 7496bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_SSSX_266 101 7596bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_200 102 7696bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_266 103 7796bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIC_66_B 104 7896bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIC_66_A 105 7996bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIS_66_B 106 8096bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIS_66_A 107 8196bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC1_B 108 8296bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC1_A 109 8396bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC0_B 110 8496bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC0_A 111 8596bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC2_B 112 8696bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC2_A 113 8796bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI1_B 114 8896bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI1_A 115 8996bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI0_B 116 9096bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI0_A 117 9196bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI2_B 118 9296bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI2_A 119 9396bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART2 120 9496bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART1 121 9596bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART0 122 9696bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI4_B 123 9796bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI4_A 124 9896bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI3_B 125 9996bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI3_A 126 10023236496SChanwoo Choi #define CLK_DIV_SCLK_I2S1 127 10123236496SChanwoo Choi #define CLK_DIV_SCLK_PCM1 128 10223236496SChanwoo Choi #define CLK_DIV_SCLK_AUDIO1 129 10323236496SChanwoo Choi #define CLK_DIV_SCLK_AUDIO0 130 104a29308daSChanwoo Choi #define CLK_DIV_ACLK_GSCL_111 131 105a29308daSChanwoo Choi #define CLK_DIV_ACLK_GSCL_333 132 106a29308daSChanwoo Choi #define CLK_DIV_ACLK_HEVC_400 133 107a29308daSChanwoo Choi #define CLK_DIV_ACLK_MFC_400 134 108a29308daSChanwoo Choi #define CLK_DIV_ACLK_G2D_266 135 109a29308daSChanwoo Choi #define CLK_DIV_ACLK_G2D_400 136 1105785d6e6SChanwoo Choi #define CLK_DIV_ACLK_G3D_400 137 1115785d6e6SChanwoo Choi #define CLK_DIV_ACLK_BUS0_400 138 1125785d6e6SChanwoo Choi #define CLK_DIV_ACLK_BUS1_400 139 1134b801355SChanwoo Choi #define CLK_DIV_SCLK_PCIE_100 140 1144b801355SChanwoo Choi #define CLK_DIV_SCLK_USBHOST30 141 1154b801355SChanwoo Choi #define CLK_DIV_SCLK_UFSUNIPRO 142 1164b801355SChanwoo Choi #define CLK_DIV_SCLK_USBDRD30 143 117b274bbfdSChanwoo Choi #define CLK_DIV_SCLK_JPEG 144 118b274bbfdSChanwoo Choi #define CLK_DIV_ACLK_MSCL_400 145 1198e46c4b8SChanwoo Choi #define CLK_DIV_ACLK_ISP_DIS_400 146 1208e46c4b8SChanwoo Choi #define CLK_DIV_ACLK_ISP_400 147 12196bd6224SChanwoo Choi 12296bd6224SChanwoo Choi #define CLK_ACLK_PERIC_66 200 12396bd6224SChanwoo Choi #define CLK_ACLK_PERIS_66 201 12496bd6224SChanwoo Choi #define CLK_ACLK_FSYS_200 202 12596bd6224SChanwoo Choi #define CLK_SCLK_MMC2_FSYS 203 12696bd6224SChanwoo Choi #define CLK_SCLK_MMC1_FSYS 204 12796bd6224SChanwoo Choi #define CLK_SCLK_MMC0_FSYS 205 12896bd6224SChanwoo Choi #define CLK_SCLK_SPI4_PERIC 206 12996bd6224SChanwoo Choi #define CLK_SCLK_SPI3_PERIC 207 13096bd6224SChanwoo Choi #define CLK_SCLK_UART2_PERIC 208 13196bd6224SChanwoo Choi #define CLK_SCLK_UART1_PERIC 209 13296bd6224SChanwoo Choi #define CLK_SCLK_UART0_PERIC 210 13396bd6224SChanwoo Choi #define CLK_SCLK_SPI2_PERIC 211 13496bd6224SChanwoo Choi #define CLK_SCLK_SPI1_PERIC 212 13596bd6224SChanwoo Choi #define CLK_SCLK_SPI0_PERIC 213 13623236496SChanwoo Choi #define CLK_SCLK_SPDIF_PERIC 214 13723236496SChanwoo Choi #define CLK_SCLK_I2S1_PERIC 215 13823236496SChanwoo Choi #define CLK_SCLK_PCM1_PERIC 216 13923236496SChanwoo Choi #define CLK_SCLK_SLIMBUS 217 14023236496SChanwoo Choi #define CLK_SCLK_AUDIO1 218 14123236496SChanwoo Choi #define CLK_SCLK_AUDIO0 219 142a29308daSChanwoo Choi #define CLK_ACLK_G2D_266 220 143a29308daSChanwoo Choi #define CLK_ACLK_G2D_400 221 1445785d6e6SChanwoo Choi #define CLK_ACLK_G3D_400 222 1455785d6e6SChanwoo Choi #define CLK_ACLK_IMEM_SSX_266 223 1465785d6e6SChanwoo Choi #define CLK_ACLK_BUS0_400 224 1475785d6e6SChanwoo Choi #define CLK_ACLK_BUS1_400 225 1485785d6e6SChanwoo Choi #define CLK_ACLK_IMEM_200 226 1495785d6e6SChanwoo Choi #define CLK_ACLK_IMEM_266 227 1504b801355SChanwoo Choi #define CLK_SCLK_PCIE_100_FSYS 228 1514b801355SChanwoo Choi #define CLK_SCLK_UFSUNIPRO_FSYS 229 1524b801355SChanwoo Choi #define CLK_SCLK_USBHOST30_FSYS 230 1534b801355SChanwoo Choi #define CLK_SCLK_USBDRD30_FSYS 231 1542a2f33e8SChanwoo Choi #define CLK_ACLK_GSCL_111 232 1552a2f33e8SChanwoo Choi #define CLK_ACLK_GSCL_333 233 156b274bbfdSChanwoo Choi #define CLK_SCLK_JPEG_MSCL 234 157b274bbfdSChanwoo Choi #define CLK_ACLK_MSCL_400 235 1589910b6bbSChanwoo Choi #define CLK_ACLK_MFC_400 236 15945e58aa5SChanwoo Choi #define CLK_ACLK_HEVC_400 237 1608e46c4b8SChanwoo Choi #define CLK_ACLK_ISP_DIS_400 238 1618e46c4b8SChanwoo Choi #define CLK_ACLK_ISP_400 239 16296bd6224SChanwoo Choi 1638e46c4b8SChanwoo Choi #define TOP_NR_CLK 240 16496bd6224SChanwoo Choi 16596bd6224SChanwoo Choi /* CMU_CPIF */ 16696bd6224SChanwoo Choi #define CLK_FOUT_MPHY_PLL 1 16796bd6224SChanwoo Choi 16896bd6224SChanwoo Choi #define CLK_MOUT_MPHY_PLL 2 16996bd6224SChanwoo Choi 17096bd6224SChanwoo Choi #define CLK_DIV_SCLK_MPHY 10 17196bd6224SChanwoo Choi 17296bd6224SChanwoo Choi #define CLK_SCLK_MPHY_PLL 11 17396bd6224SChanwoo Choi #define CLK_SCLK_UFS_MPHY 11 17496bd6224SChanwoo Choi 17596bd6224SChanwoo Choi #define CPIF_NR_CLK 12 17696bd6224SChanwoo Choi 17796bd6224SChanwoo Choi /* CMU_MIF */ 17896bd6224SChanwoo Choi #define CLK_FOUT_MEM0_PLL 1 17996bd6224SChanwoo Choi #define CLK_FOUT_MEM1_PLL 2 18096bd6224SChanwoo Choi #define CLK_FOUT_BUS_PLL 3 18196bd6224SChanwoo Choi #define CLK_FOUT_MFC_PLL 4 18206d2f9dfSChanwoo Choi #define CLK_DOUT_MFC_PLL 5 18306d2f9dfSChanwoo Choi #define CLK_DOUT_BUS_PLL 6 18406d2f9dfSChanwoo Choi #define CLK_DOUT_MEM1_PLL 7 18506d2f9dfSChanwoo Choi #define CLK_DOUT_MEM0_PLL 8 18696bd6224SChanwoo Choi 18706d2f9dfSChanwoo Choi #define CLK_MOUT_MFC_PLL_DIV2 10 18806d2f9dfSChanwoo Choi #define CLK_MOUT_BUS_PLL_DIV2 11 18906d2f9dfSChanwoo Choi #define CLK_MOUT_MEM1_PLL_DIV2 12 19006d2f9dfSChanwoo Choi #define CLK_MOUT_MEM0_PLL_DIV2 13 19106d2f9dfSChanwoo Choi #define CLK_MOUT_MFC_PLL 14 19206d2f9dfSChanwoo Choi #define CLK_MOUT_BUS_PLL 15 19306d2f9dfSChanwoo Choi #define CLK_MOUT_MEM1_PLL 16 19406d2f9dfSChanwoo Choi #define CLK_MOUT_MEM0_PLL 17 19506d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_C 18 19606d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_B 19 19706d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_A 20 19806d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_C 21 19906d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_B 22 20006d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_A 23 20106d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_MIFNM_200 24 20206d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_MIFNM_400 25 20306d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_B 26 20406d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_A 27 20506d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_C 28 20606d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_B 29 20706d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_A 30 20806d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_C 31 20906d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_B 32 21006d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_A 33 21106d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34 21206d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35 21306d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36 21406d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_C 37 21506d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_B 38 21606d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_A 39 21706d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_C 40 21806d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_B 41 21906d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_A 42 22006d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46 22106d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47 22206d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48 22306d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_C 49 22406d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_B 50 22506d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_A 51 22606d2f9dfSChanwoo Choi 22706d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_HPM_MIF 55 22806d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DREX1 56 22906d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DREX0 57 23006d2f9dfSChanwoo Choi #define CLK_DIV_CLK2XPHY 58 23106d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_266 59 23206d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIFND_133 60 23306d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_133 61 23406d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIFNM_200 62 23506d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_200 63 23606d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_400 64 23706d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_BUS2_400 65 23806d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DISP_333 66 23906d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_CPIF_200 67 24006d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSIM1 68 24106d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_VCLK 69 24206d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSIM0 70 24306d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSD 71 24406d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_ECLK 72 24506d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_VCLK 73 24606d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_ECLK 74 24706d2f9dfSChanwoo Choi #define CLK_DIV_MIF_PRE 75 24806d2f9dfSChanwoo Choi 24906d2f9dfSChanwoo Choi #define CLK_CLK2X_PHY1 80 25006d2f9dfSChanwoo Choi #define CLK_CLK2X_PHY0 81 25106d2f9dfSChanwoo Choi #define CLK_CLKM_PHY1 82 25206d2f9dfSChanwoo Choi #define CLK_CLKM_PHY0 83 25306d2f9dfSChanwoo Choi #define CLK_RCLK_DREX1 84 25406d2f9dfSChanwoo Choi #define CLK_RCLK_DREX0 85 25506d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_TZ 86 25606d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_TZ 87 25706d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_PEREV 88 25806d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_PEREV 89 25906d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_MEMIF 90 26006d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_MEMIF 91 26106d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_SCH 92 26206d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_SCH 93 26306d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_BUSIF 94 26406d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_BUSIF 95 26506d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_BUSIF_RD 96 26606d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_BUSIF_RD 97 26706d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1 98 26806d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0 99 26906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100 27006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101 27106d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102 27206d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103 27306d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104 27406d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105 27506d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_CP1 106 27606d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_CP1 107 27706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_CP0 108 27806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_CP0 109 27906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_3 110 28006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_3 111 28106d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_1 112 28206d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_1 113 28306d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_0 114 28406d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_0 115 28506d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_3 116 28606d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_3 117 28706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_1 118 28806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_1 119 28906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_0 120 29006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_0 121 29106d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF2P 122 29206d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF1P 123 29306d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF0P 124 29406d2f9dfSChanwoo Choi #define CLK_ACLK_IXIU_CCI 125 29506d2f9dfSChanwoo Choi #define CLK_ACLK_XIU_MIFSFRX 126 29606d2f9dfSChanwoo Choi #define CLK_ACLK_MIFNP_133 127 29706d2f9dfSChanwoo Choi #define CLK_ACLK_MIFNM_200 128 29806d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_133 129 29906d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_400 130 30006d2f9dfSChanwoo Choi #define CLK_ACLK_CCI 131 30106d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_266 132 30206d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S3 133 30306d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S1 134 30406d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S0 135 30506d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S3 136 30606d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S1 137 30706d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S0 138 30806d2f9dfSChanwoo Choi #define CLK_ACLK_BTS_APOLLO 139 30906d2f9dfSChanwoo Choi #define CLK_ACLK_BTS_ATLAS 140 31006d2f9dfSChanwoo Choi #define CLK_ACLK_ACE_SEL_APOLL 141 31106d2f9dfSChanwoo Choi #define CLK_ACLK_ACE_SEL_ATLAS 142 31206d2f9dfSChanwoo Choi #define CLK_ACLK_AXIDS_CCI_MIFSFRX 143 31306d2f9dfSChanwoo Choi #define CLK_ACLK_AXIUS_ATLAS_CCI 144 31406d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDNS_CCI 145 31506d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDN_CCI 146 31606d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDN_NOC_D 147 31706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148 31806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149 31906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150 32006d2f9dfSChanwoo Choi #define CLK_ACLK_BUS2_400 151 32106d2f9dfSChanwoo Choi #define CLK_ACLK_DISP_333 152 32206d2f9dfSChanwoo Choi #define CLK_ACLK_CPIF_200 153 32306d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S3 154 32406d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S1 155 32506d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S0 156 32606d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S3 157 32706d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S1 158 32806d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S0 159 32906d2f9dfSChanwoo Choi #define CLK_PCLK_BTS_APOLLO 160 33006d2f9dfSChanwoo Choi #define CLK_PCLK_BTS_ATLAS 161 33106d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162 33206d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_CP1 163 33306d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_CP0 164 33406d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_3 165 33506d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_1 166 33606d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_0 167 33706d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_3 168 33806d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_1 169 33906d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_0 170 34006d2f9dfSChanwoo Choi #define CLK_PCLK_MIFSRVND_133 171 34106d2f9dfSChanwoo Choi #define CLK_PCLK_PMU_MIF 172 34206d2f9dfSChanwoo Choi #define CLK_PCLK_SYSREG_MIF 173 34306d2f9dfSChanwoo Choi #define CLK_PCLK_GPIO_ALIVE 174 34406d2f9dfSChanwoo Choi #define CLK_PCLK_ABB 175 34506d2f9dfSChanwoo Choi #define CLK_PCLK_PMU_APBIF 176 34606d2f9dfSChanwoo Choi #define CLK_PCLK_DDR_PHY1 177 34706d2f9dfSChanwoo Choi #define CLK_PCLK_DREX1 178 34806d2f9dfSChanwoo Choi #define CLK_PCLK_DDR_PHY0 179 34906d2f9dfSChanwoo Choi #define CLK_PCLK_DREX0 180 35006d2f9dfSChanwoo Choi #define CLK_PCLK_DREX0_TZ 181 35106d2f9dfSChanwoo Choi #define CLK_PCLK_DREX1_TZ 182 35206d2f9dfSChanwoo Choi #define CLK_PCLK_MONOTONIC_CNT 183 35306d2f9dfSChanwoo Choi #define CLK_PCLK_RTC 184 35406d2f9dfSChanwoo Choi #define CLK_SCLK_DSIM1_DISP 185 35506d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_TV_VCLK_DISP 186 35606d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_BUS_PLL 187 35706d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MFC_PLL 188 35806d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MEM0_PLL 189 35906d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MEM1_PLL 190 36006d2f9dfSChanwoo Choi #define CLK_SCLK_DSIM0_DISP 191 36106d2f9dfSChanwoo Choi #define CLK_SCLK_DSD_DISP 192 36206d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_TV_ECLK_DISP 193 36306d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_VCLK_DISP 194 36406d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_ECLK_DISP 195 36506d2f9dfSChanwoo Choi #define CLK_SCLK_HPM_MIF 196 36606d2f9dfSChanwoo Choi #define CLK_SCLK_MFC_PLL 197 36706d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL 198 36806d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL_APOLLO 199 36906d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL_ATLAS 200 3702a1808a6SChanwoo Choi #define CLK_SCLK_HDMI_SPDIF_DISP 201 37106d2f9dfSChanwoo Choi 3722a1808a6SChanwoo Choi #define MIF_NR_CLK 202 37396bd6224SChanwoo Choi 37496bd6224SChanwoo Choi /* CMU_PERIC */ 37596bd6224SChanwoo Choi #define CLK_PCLK_SPI2 1 37696bd6224SChanwoo Choi #define CLK_PCLK_SPI1 2 37796bd6224SChanwoo Choi #define CLK_PCLK_SPI0 3 37896bd6224SChanwoo Choi #define CLK_PCLK_UART2 4 37996bd6224SChanwoo Choi #define CLK_PCLK_UART1 5 38096bd6224SChanwoo Choi #define CLK_PCLK_UART0 6 38196bd6224SChanwoo Choi #define CLK_PCLK_HSI2C3 7 38296bd6224SChanwoo Choi #define CLK_PCLK_HSI2C2 8 38396bd6224SChanwoo Choi #define CLK_PCLK_HSI2C1 9 38496bd6224SChanwoo Choi #define CLK_PCLK_HSI2C0 10 38596bd6224SChanwoo Choi #define CLK_PCLK_I2C7 11 38696bd6224SChanwoo Choi #define CLK_PCLK_I2C6 12 38796bd6224SChanwoo Choi #define CLK_PCLK_I2C5 13 38896bd6224SChanwoo Choi #define CLK_PCLK_I2C4 14 38996bd6224SChanwoo Choi #define CLK_PCLK_I2C3 15 39096bd6224SChanwoo Choi #define CLK_PCLK_I2C2 16 39196bd6224SChanwoo Choi #define CLK_PCLK_I2C1 17 39296bd6224SChanwoo Choi #define CLK_PCLK_I2C0 18 39396bd6224SChanwoo Choi #define CLK_PCLK_SPI4 19 39496bd6224SChanwoo Choi #define CLK_PCLK_SPI3 20 39596bd6224SChanwoo Choi #define CLK_PCLK_HSI2C11 21 39696bd6224SChanwoo Choi #define CLK_PCLK_HSI2C10 22 39796bd6224SChanwoo Choi #define CLK_PCLK_HSI2C9 23 39896bd6224SChanwoo Choi #define CLK_PCLK_HSI2C8 24 39996bd6224SChanwoo Choi #define CLK_PCLK_HSI2C7 25 40096bd6224SChanwoo Choi #define CLK_PCLK_HSI2C6 26 40196bd6224SChanwoo Choi #define CLK_PCLK_HSI2C5 27 40296bd6224SChanwoo Choi #define CLK_PCLK_HSI2C4 28 40396bd6224SChanwoo Choi #define CLK_SCLK_SPI4 29 40496bd6224SChanwoo Choi #define CLK_SCLK_SPI3 30 40596bd6224SChanwoo Choi #define CLK_SCLK_SPI2 31 40696bd6224SChanwoo Choi #define CLK_SCLK_SPI1 32 40796bd6224SChanwoo Choi #define CLK_SCLK_SPI0 33 40896bd6224SChanwoo Choi #define CLK_SCLK_UART2 34 40996bd6224SChanwoo Choi #define CLK_SCLK_UART1 35 41096bd6224SChanwoo Choi #define CLK_SCLK_UART0 36 411d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC2P 37 412d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC1P 38 413d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC0P 39 414d0f5de66SChanwoo Choi #define CLK_ACLK_PERICNP_66 40 415d0f5de66SChanwoo Choi #define CLK_PCLK_SCI 41 416d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_FINGER 42 417d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_ESE 43 418d0f5de66SChanwoo Choi #define CLK_PCLK_PWM 44 419d0f5de66SChanwoo Choi #define CLK_PCLK_SPDIF 45 420d0f5de66SChanwoo Choi #define CLK_PCLK_PCM1 46 421d0f5de66SChanwoo Choi #define CLK_PCLK_I2S1 47 422d0f5de66SChanwoo Choi #define CLK_PCLK_ADCIF 48 423d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_TOUCH 49 424d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_NFC 50 425d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_PERIC 51 426d0f5de66SChanwoo Choi #define CLK_PCLK_PMU_PERIC 52 427d0f5de66SChanwoo Choi #define CLK_PCLK_SYSREG_PERIC 53 428d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI4 54 429d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI3 55 430d0f5de66SChanwoo Choi #define CLK_SCLK_SCI 56 431d0f5de66SChanwoo Choi #define CLK_SCLK_SC_IN 57 432d0f5de66SChanwoo Choi #define CLK_SCLK_PWM 58 433d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI2 59 434d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI1 60 435d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI0 61 436d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_I2S1_BCLK 62 437d0f5de66SChanwoo Choi #define CLK_SCLK_SPDIF 63 438d0f5de66SChanwoo Choi #define CLK_SCLK_PCM1 64 439d0f5de66SChanwoo Choi #define CLK_SCLK_I2S1 65 44096bd6224SChanwoo Choi 441d0f5de66SChanwoo Choi #define CLK_DIV_SCLK_SCI 70 442d0f5de66SChanwoo Choi #define CLK_DIV_SCLK_SC_IN 71 443d0f5de66SChanwoo Choi 444d0f5de66SChanwoo Choi #define PERIC_NR_CLK 72 44596bd6224SChanwoo Choi 44696bd6224SChanwoo Choi /* CMU_PERIS */ 44796bd6224SChanwoo Choi #define CLK_PCLK_HPM_APBIF 1 44896bd6224SChanwoo Choi #define CLK_PCLK_TMU1_APBIF 2 44996bd6224SChanwoo Choi #define CLK_PCLK_TMU0_APBIF 3 45096bd6224SChanwoo Choi #define CLK_PCLK_PMU_PERIS 4 45196bd6224SChanwoo Choi #define CLK_PCLK_SYSREG_PERIS 5 45296bd6224SChanwoo Choi #define CLK_PCLK_CMU_TOP_APBIF 6 45396bd6224SChanwoo Choi #define CLK_PCLK_WDT_APOLLO 7 45496bd6224SChanwoo Choi #define CLK_PCLK_WDT_ATLAS 8 45596bd6224SChanwoo Choi #define CLK_PCLK_MCT 9 45696bd6224SChanwoo Choi #define CLK_PCLK_HDMI_CEC 10 45756bcf3f3SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIS1P 11 45856bcf3f3SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIS0P 12 45956bcf3f3SChanwoo Choi #define CLK_ACLK_PERISNP_66 13 46056bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC12 14 46156bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC11 15 46256bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC10 16 46356bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC9 17 46456bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC8 18 46556bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC7 19 46656bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC6 20 46756bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC5 21 46856bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC4 22 46956bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC3 23 47056bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC2 24 47156bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC1 25 47256bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC0 26 47356bcf3f3SChanwoo Choi #define CLK_PCLK_SECKEY_APBIF 27 47456bcf3f3SChanwoo Choi #define CLK_PCLK_CHIPID_APBIF 28 47556bcf3f3SChanwoo Choi #define CLK_PCLK_TOPRTC 29 47656bcf3f3SChanwoo Choi #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 47756bcf3f3SChanwoo Choi #define CLK_PCLK_ANTIRBK_CNT_APBIF 31 47856bcf3f3SChanwoo Choi #define CLK_PCLK_OTP_CON_APBIF 32 47956bcf3f3SChanwoo Choi #define CLK_SCLK_ASV_TB 33 48056bcf3f3SChanwoo Choi #define CLK_SCLK_TMU1 34 48156bcf3f3SChanwoo Choi #define CLK_SCLK_TMU0 35 48256bcf3f3SChanwoo Choi #define CLK_SCLK_SECKEY 36 48356bcf3f3SChanwoo Choi #define CLK_SCLK_CHIPID 37 48456bcf3f3SChanwoo Choi #define CLK_SCLK_TOPRTC 38 48556bcf3f3SChanwoo Choi #define CLK_SCLK_CUSTOM_EFUSE 39 48656bcf3f3SChanwoo Choi #define CLK_SCLK_ANTIRBK_CNT 40 48756bcf3f3SChanwoo Choi #define CLK_SCLK_OTP_CON 41 48896bd6224SChanwoo Choi 48956bcf3f3SChanwoo Choi #define PERIS_NR_CLK 42 49096bd6224SChanwoo Choi 49196bd6224SChanwoo Choi /* CMU_FSYS */ 49296bd6224SChanwoo Choi #define CLK_MOUT_ACLK_FSYS_200_USER 1 49396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_USER 2 49496bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_USER 3 49596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_USER 4 4964b801355SChanwoo Choi #define CLK_MOUT_SCLK_UFS_MPHY_USER 5 4974b801355SChanwoo Choi #define CLK_MOUT_SCLK_PCIE_100_USER 6 4984b801355SChanwoo Choi #define CLK_MOUT_SCLK_UFSUNIPRO_USER 7 4994b801355SChanwoo Choi #define CLK_MOUT_SCLK_USBHOST30_USER 8 5004b801355SChanwoo Choi #define CLK_MOUT_SCLK_USBDRD30_USER 9 5014b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10 5024b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11 5034b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12 5044b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13 5054b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14 5064b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15 5074b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16 5084b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17 5094b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18 5104b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19 5114b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20 5124b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21 5134b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22 5144b801355SChanwoo Choi #define CLK_MOUT_SCLK_MPHY 23 5154b801355SChanwoo Choi 5164b801355SChanwoo Choi #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25 5174b801355SChanwoo Choi #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26 5184b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27 5194b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28 5204b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29 5214b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30 5224b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31 5234b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32 5244b801355SChanwoo Choi #define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33 5254b801355SChanwoo Choi #define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34 5264b801355SChanwoo Choi #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35 5274b801355SChanwoo Choi #define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36 5284b801355SChanwoo Choi #define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37 52996bd6224SChanwoo Choi 53096bd6224SChanwoo Choi #define CLK_ACLK_PCIE 50 53196bd6224SChanwoo Choi #define CLK_ACLK_PDMA1 51 53296bd6224SChanwoo Choi #define CLK_ACLK_TSI 52 53396bd6224SChanwoo Choi #define CLK_ACLK_MMC2 53 53496bd6224SChanwoo Choi #define CLK_ACLK_MMC1 54 53596bd6224SChanwoo Choi #define CLK_ACLK_MMC0 55 53696bd6224SChanwoo Choi #define CLK_ACLK_UFS 56 53796bd6224SChanwoo Choi #define CLK_ACLK_USBHOST20 57 53896bd6224SChanwoo Choi #define CLK_ACLK_USBHOST30 58 53996bd6224SChanwoo Choi #define CLK_ACLK_USBDRD30 59 54096bd6224SChanwoo Choi #define CLK_ACLK_PDMA0 60 54196bd6224SChanwoo Choi #define CLK_SCLK_MMC2 61 54296bd6224SChanwoo Choi #define CLK_SCLK_MMC1 62 54396bd6224SChanwoo Choi #define CLK_SCLK_MMC0 63 54496bd6224SChanwoo Choi #define CLK_PDMA1 64 54596bd6224SChanwoo Choi #define CLK_PDMA0 65 5464b801355SChanwoo Choi #define CLK_ACLK_XIU_FSYSPX 66 5474b801355SChanwoo Choi #define CLK_ACLK_AHB_USBLINKH1 67 5484b801355SChanwoo Choi #define CLK_ACLK_SMMU_PDMA1 68 5494b801355SChanwoo Choi #define CLK_ACLK_BTS_PCIE 69 5504b801355SChanwoo Choi #define CLK_ACLK_AXIUS_PDMA1 70 5514b801355SChanwoo Choi #define CLK_ACLK_SMMU_PDMA0 71 5524b801355SChanwoo Choi #define CLK_ACLK_BTS_UFS 72 5534b801355SChanwoo Choi #define CLK_ACLK_BTS_USBHOST30 73 5544b801355SChanwoo Choi #define CLK_ACLK_BTS_USBDRD30 74 5554b801355SChanwoo Choi #define CLK_ACLK_AXIUS_PDMA0 75 5564b801355SChanwoo Choi #define CLK_ACLK_AXIUS_USBHS 76 5574b801355SChanwoo Choi #define CLK_ACLK_AXIUS_FSYSSX 77 5584b801355SChanwoo Choi #define CLK_ACLK_AHB2APB_FSYSP 78 5594b801355SChanwoo Choi #define CLK_ACLK_AHB2AXI_USBHS 79 5604b801355SChanwoo Choi #define CLK_ACLK_AHB_USBLINKH0 80 5614b801355SChanwoo Choi #define CLK_ACLK_AHB_USBHS 81 5624b801355SChanwoo Choi #define CLK_ACLK_AHB_FSYSH 82 5634b801355SChanwoo Choi #define CLK_ACLK_XIU_FSYSX 83 5644b801355SChanwoo Choi #define CLK_ACLK_XIU_FSYSSX 84 5654b801355SChanwoo Choi #define CLK_ACLK_FSYSNP_200 85 5664b801355SChanwoo Choi #define CLK_ACLK_FSYSND_200 86 5674b801355SChanwoo Choi #define CLK_PCLK_PCIE_CTRL 87 5684b801355SChanwoo Choi #define CLK_PCLK_SMMU_PDMA1 88 5694b801355SChanwoo Choi #define CLK_PCLK_PCIE_PHY 89 5704b801355SChanwoo Choi #define CLK_PCLK_BTS_PCIE 90 5714b801355SChanwoo Choi #define CLK_PCLK_SMMU_PDMA0 91 5724b801355SChanwoo Choi #define CLK_PCLK_BTS_UFS 92 5734b801355SChanwoo Choi #define CLK_PCLK_BTS_USBHOST30 93 5744b801355SChanwoo Choi #define CLK_PCLK_BTS_USBDRD30 94 5754b801355SChanwoo Choi #define CLK_PCLK_GPIO_FSYS 95 5764b801355SChanwoo Choi #define CLK_PCLK_PMU_FSYS 96 5774b801355SChanwoo Choi #define CLK_PCLK_SYSREG_FSYS 97 5784b801355SChanwoo Choi #define CLK_SCLK_PCIE_100 98 5794b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99 5804b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100 5814b801355SChanwoo Choi #define CLK_PHYCLK_UFS_RX1_SYMBOL 101 5824b801355SChanwoo Choi #define CLK_PHYCLK_UFS_RX0_SYMBOL 102 5834b801355SChanwoo Choi #define CLK_PHYCLK_UFS_TX1_SYMBOL 103 5844b801355SChanwoo Choi #define CLK_PHYCLK_UFS_TX0_SYMBOL 104 5854b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105 5864b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106 5874b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107 5884b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108 5894b801355SChanwoo Choi #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109 5904b801355SChanwoo Choi #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110 5914b801355SChanwoo Choi #define CLK_SCLK_MPHY 111 5924b801355SChanwoo Choi #define CLK_SCLK_UFSUNIPRO 112 5934b801355SChanwoo Choi #define CLK_SCLK_USBHOST30 113 5944b801355SChanwoo Choi #define CLK_SCLK_USBDRD30 114 59596bd6224SChanwoo Choi 5964b801355SChanwoo Choi #define FSYS_NR_CLK 115 59796bd6224SChanwoo Choi 598a29308daSChanwoo Choi /* CMU_G2D */ 599a29308daSChanwoo Choi #define CLK_MUX_ACLK_G2D_266_USER 1 600a29308daSChanwoo Choi #define CLK_MUX_ACLK_G2D_400_USER 2 601a29308daSChanwoo Choi 602a29308daSChanwoo Choi #define CLK_DIV_PCLK_G2D 3 603a29308daSChanwoo Choi 604a29308daSChanwoo Choi #define CLK_ACLK_SMMU_MDMA1 4 605a29308daSChanwoo Choi #define CLK_ACLK_BTS_MDMA1 5 606a29308daSChanwoo Choi #define CLK_ACLK_BTS_G2D 6 607a29308daSChanwoo Choi #define CLK_ACLK_ALB_G2D 7 608a29308daSChanwoo Choi #define CLK_ACLK_AXIUS_G2DX 8 609a29308daSChanwoo Choi #define CLK_ACLK_ASYNCAXI_SYSX 9 610a29308daSChanwoo Choi #define CLK_ACLK_AHB2APB_G2D1P 10 611a29308daSChanwoo Choi #define CLK_ACLK_AHB2APB_G2D0P 11 612a29308daSChanwoo Choi #define CLK_ACLK_XIU_G2DX 12 613a29308daSChanwoo Choi #define CLK_ACLK_G2DNP_133 13 614a29308daSChanwoo Choi #define CLK_ACLK_G2DND_400 14 615a29308daSChanwoo Choi #define CLK_ACLK_MDMA1 15 616a29308daSChanwoo Choi #define CLK_ACLK_G2D 16 617a29308daSChanwoo Choi #define CLK_ACLK_SMMU_G2D 17 618a29308daSChanwoo Choi #define CLK_PCLK_SMMU_MDMA1 18 619a29308daSChanwoo Choi #define CLK_PCLK_BTS_MDMA1 19 620a29308daSChanwoo Choi #define CLK_PCLK_BTS_G2D 20 621a29308daSChanwoo Choi #define CLK_PCLK_ALB_G2D 21 622a29308daSChanwoo Choi #define CLK_PCLK_ASYNCAXI_SYSX 22 623a29308daSChanwoo Choi #define CLK_PCLK_PMU_G2D 23 624a29308daSChanwoo Choi #define CLK_PCLK_SYSREG_G2D 24 625a29308daSChanwoo Choi #define CLK_PCLK_G2D 25 626a29308daSChanwoo Choi #define CLK_PCLK_SMMU_G2D 26 627a29308daSChanwoo Choi 628a29308daSChanwoo Choi #define G2D_NR_CLK 27 629a29308daSChanwoo Choi 6302a1808a6SChanwoo Choi /* CMU_DISP */ 6312a1808a6SChanwoo Choi #define CLK_FOUT_DISP_PLL 1 6322a1808a6SChanwoo Choi 6332a1808a6SChanwoo Choi #define CLK_MOUT_DISP_PLL 2 6342a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_USER 3 6352a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_USER 4 6362a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSD_USER 5 6372a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6 6382a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_USER 7 6392a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_USER 8 6402a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9 6412a1808a6SChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_USER 10 6422a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11 6432a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12 6442a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13 6452a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14 6462a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15 6472a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16 6482a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM0 17 6492a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK 18 6502a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK 19 6512a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK 20 6522a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_B_DISP 21 6532a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_A_DISP 22 6542a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23 6552a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24 6562a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25 6572a1808a6SChanwoo Choi 6582a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DSIM1_DISP 30 6592a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31 6602a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DSIM0_DISP 32 6612a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33 6622a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_VCLK_DISP 34 6632a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_ECLK_DISP 35 6642a1808a6SChanwoo Choi #define CLK_DIV_PCLK_DISP 36 6652a1808a6SChanwoo Choi 6662a1808a6SChanwoo Choi #define CLK_ACLK_DECON_TV 40 6672a1808a6SChanwoo Choi #define CLK_ACLK_DECON 41 6682a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_TV1X 42 6692a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_TV0X 43 6702a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_DECON1X 44 6712a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_DECON0X 45 6722a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M3 46 6732a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M2 47 6742a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M1 48 6752a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M0 49 6762a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM4 50 6772a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM3 51 6782a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM2 52 6792a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM1 53 6802a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM0 54 6812a1808a6SChanwoo Choi #define CLK_ACLK_AHB2APB_DISPSFR2P 55 6822a1808a6SChanwoo Choi #define CLK_ACLK_AHB2APB_DISPSFR1P 56 6832a1808a6SChanwoo Choi #define CLK_ACLK_AHB2APB_DISPSFR0P 57 6842a1808a6SChanwoo Choi #define CLK_ACLK_AHB_DISPH 58 6852a1808a6SChanwoo Choi #define CLK_ACLK_XIU_TV1X 59 6862a1808a6SChanwoo Choi #define CLK_ACLK_XIU_TV0X 60 6872a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DECON1X 61 6882a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DECON0X 62 6892a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DISP1X 63 6902a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DISPNP_100 64 6912a1808a6SChanwoo Choi #define CLK_ACLK_DISP1ND_333 65 6922a1808a6SChanwoo Choi #define CLK_ACLK_DISP0ND_333 66 6932a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_TV1X 67 6942a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_TV0X 68 6952a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_DECON1X 69 6962a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_DECON0X 70 6972a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M3 71 6982a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M2 72 6992a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M1 73 7002a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M0 74 7012a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM4 75 7022a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM3 76 7032a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM2 77 7042a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM1 78 7052a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM0 79 7062a1808a6SChanwoo Choi #define CLK_PCLK_MIC1 80 7072a1808a6SChanwoo Choi #define CLK_PCLK_PMU_DISP 81 7082a1808a6SChanwoo Choi #define CLK_PCLK_SYSREG_DISP 82 7092a1808a6SChanwoo Choi #define CLK_PCLK_HDMIPHY 83 7102a1808a6SChanwoo Choi #define CLK_PCLK_HDMI 84 7112a1808a6SChanwoo Choi #define CLK_PCLK_MIC0 85 7122a1808a6SChanwoo Choi #define CLK_PCLK_DSIM1 86 7132a1808a6SChanwoo Choi #define CLK_PCLK_DSIM0 87 7142a1808a6SChanwoo Choi #define CLK_PCLK_DECON_TV 88 7152a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89 7162a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90 7172a1808a6SChanwoo Choi #define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91 7182a1808a6SChanwoo Choi #define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92 7192a1808a6SChanwoo Choi #define CLK_SCLK_DSIM1 93 7202a1808a6SChanwoo Choi #define CLK_SCLK_DECON_TV_VCLK 94 7212a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95 7222a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96 7232a1808a6SChanwoo Choi #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97 7242a1808a6SChanwoo Choi #define CLK_PHYCLK_HDMI_PIXEL 98 7252a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK_TO_SMIES 99 7262a1808a6SChanwoo Choi #define CLK_SCLK_FREQ_DET_DISP_PLL 100 7272a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK_TO_DSIM0 101 7282a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK_TO_MIC0 102 7292a1808a6SChanwoo Choi #define CLK_SCLK_DSD 103 7302a1808a6SChanwoo Choi #define CLK_SCLK_HDMI_SPDIF 104 7312a1808a6SChanwoo Choi #define CLK_SCLK_DSIM0 105 7322a1808a6SChanwoo Choi #define CLK_SCLK_DECON_TV_ECLK 106 7332a1808a6SChanwoo Choi #define CLK_SCLK_DECON_VCLK 107 7342a1808a6SChanwoo Choi #define CLK_SCLK_DECON_ECLK 108 7352a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK 109 7362a1808a6SChanwoo Choi #define CLK_SCLK_RGB_TV_VCLK 110 7372a1808a6SChanwoo Choi 7382a1808a6SChanwoo Choi #define DISP_NR_CLK 111 7392a1808a6SChanwoo Choi 7402e997c03SChanwoo Choi /* CMU_AUD */ 7412e997c03SChanwoo Choi #define CLK_MOUT_AUD_PLL_USER 1 7422e997c03SChanwoo Choi #define CLK_MOUT_SCLK_AUD_PCM 2 7432e997c03SChanwoo Choi #define CLK_MOUT_SCLK_AUD_I2S 3 7442e997c03SChanwoo Choi 7452e997c03SChanwoo Choi #define CLK_DIV_ATCLK_AUD 4 7462e997c03SChanwoo Choi #define CLK_DIV_PCLK_DBG_AUD 5 7472e997c03SChanwoo Choi #define CLK_DIV_ACLK_AUD 6 7482e997c03SChanwoo Choi #define CLK_DIV_AUD_CA5 7 7492e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_SLIMBUS 8 7502e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_UART 9 7512e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_PCM 10 7522e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_I2S 11 7532e997c03SChanwoo Choi 7542e997c03SChanwoo Choi #define CLK_ACLK_INTR_CTRL 12 7552e997c03SChanwoo Choi #define CLK_ACLK_AXIDS2_LPASSP 13 7562e997c03SChanwoo Choi #define CLK_ACLK_AXIDS1_LPASSP 14 7572e997c03SChanwoo Choi #define CLK_ACLK_AXI2APB1_LPASSP 15 7582e997c03SChanwoo Choi #define CLK_ACLK_AXI2APH_LPASSP 16 7592e997c03SChanwoo Choi #define CLK_ACLK_SMMU_LPASSX 17 7602e997c03SChanwoo Choi #define CLK_ACLK_AXIDS0_LPASSP 18 7612e997c03SChanwoo Choi #define CLK_ACLK_AXI2APB0_LPASSP 19 7622e997c03SChanwoo Choi #define CLK_ACLK_XIU_LPASSX 20 7632e997c03SChanwoo Choi #define CLK_ACLK_AUDNP_133 21 7642e997c03SChanwoo Choi #define CLK_ACLK_AUDND_133 22 7652e997c03SChanwoo Choi #define CLK_ACLK_SRAMC 23 7662e997c03SChanwoo Choi #define CLK_ACLK_DMAC 24 7672e997c03SChanwoo Choi #define CLK_PCLK_WDT1 25 7682e997c03SChanwoo Choi #define CLK_PCLK_WDT0 26 7692e997c03SChanwoo Choi #define CLK_PCLK_SFR1 27 7702e997c03SChanwoo Choi #define CLK_PCLK_SMMU_LPASSX 28 7712e997c03SChanwoo Choi #define CLK_PCLK_GPIO_AUD 29 7722e997c03SChanwoo Choi #define CLK_PCLK_PMU_AUD 30 7732e997c03SChanwoo Choi #define CLK_PCLK_SYSREG_AUD 31 7742e997c03SChanwoo Choi #define CLK_PCLK_AUD_SLIMBUS 32 7752e997c03SChanwoo Choi #define CLK_PCLK_AUD_UART 33 7762e997c03SChanwoo Choi #define CLK_PCLK_AUD_PCM 34 7772e997c03SChanwoo Choi #define CLK_PCLK_AUD_I2S 35 7782e997c03SChanwoo Choi #define CLK_PCLK_TIMER 36 7792e997c03SChanwoo Choi #define CLK_PCLK_SFR0_CTRL 37 7802e997c03SChanwoo Choi #define CLK_ATCLK_AUD 38 7812e997c03SChanwoo Choi #define CLK_PCLK_DBG_AUD 39 7822e997c03SChanwoo Choi #define CLK_SCLK_AUD_CA5 40 7832e997c03SChanwoo Choi #define CLK_SCLK_JTAG_TCK 41 7842e997c03SChanwoo Choi #define CLK_SCLK_SLIMBUS_CLKIN 42 7852e997c03SChanwoo Choi #define CLK_SCLK_AUD_SLIMBUS 43 7862e997c03SChanwoo Choi #define CLK_SCLK_AUD_UART 44 7872e997c03SChanwoo Choi #define CLK_SCLK_AUD_PCM 45 7882e997c03SChanwoo Choi #define CLK_SCLK_I2S_BCLK 46 7892e997c03SChanwoo Choi #define CLK_SCLK_AUD_I2S 47 7902e997c03SChanwoo Choi 7912e997c03SChanwoo Choi #define AUD_NR_CLK 48 7922e997c03SChanwoo Choi 7935785d6e6SChanwoo Choi /* CMU_BUS{0|1|2} */ 7945785d6e6SChanwoo Choi #define CLK_DIV_PCLK_BUS_133 1 7955785d6e6SChanwoo Choi 7965785d6e6SChanwoo Choi #define CLK_ACLK_AHB2APB_BUSP 2 7975785d6e6SChanwoo Choi #define CLK_ACLK_BUSNP_133 3 7985785d6e6SChanwoo Choi #define CLK_ACLK_BUSND_400 4 7995785d6e6SChanwoo Choi #define CLK_PCLK_BUSSRVND_133 5 8005785d6e6SChanwoo Choi #define CLK_PCLK_PMU_BUS 6 8015785d6e6SChanwoo Choi #define CLK_PCLK_SYSREG_BUS 7 8025785d6e6SChanwoo Choi 8035785d6e6SChanwoo Choi #define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */ 8045785d6e6SChanwoo Choi #define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ 8055785d6e6SChanwoo Choi #define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ 8065785d6e6SChanwoo Choi 8075785d6e6SChanwoo Choi #define BUSx_NR_CLK 11 8085785d6e6SChanwoo Choi 809453e519eSChanwoo Choi /* CMU_G3D */ 810453e519eSChanwoo Choi #define CLK_FOUT_G3D_PLL 1 811453e519eSChanwoo Choi 812453e519eSChanwoo Choi #define CLK_MOUT_ACLK_G3D_400 2 813453e519eSChanwoo Choi #define CLK_MOUT_G3D_PLL 3 814453e519eSChanwoo Choi 815453e519eSChanwoo Choi #define CLK_DIV_SCLK_HPM_G3D 4 816453e519eSChanwoo Choi #define CLK_DIV_PCLK_G3D 5 817453e519eSChanwoo Choi #define CLK_DIV_ACLK_G3D 6 818453e519eSChanwoo Choi #define CLK_ACLK_BTS_G3D1 7 819453e519eSChanwoo Choi #define CLK_ACLK_BTS_G3D0 8 820453e519eSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_G3D 9 821453e519eSChanwoo Choi #define CLK_ACLK_ASYNCAPBM_G3D 10 822453e519eSChanwoo Choi #define CLK_ACLK_AHB2APB_G3DP 11 823453e519eSChanwoo Choi #define CLK_ACLK_G3DNP_150 12 824453e519eSChanwoo Choi #define CLK_ACLK_G3DND_600 13 825453e519eSChanwoo Choi #define CLK_ACLK_G3D 14 826453e519eSChanwoo Choi #define CLK_PCLK_BTS_G3D1 15 827453e519eSChanwoo Choi #define CLK_PCLK_BTS_G3D0 16 828453e519eSChanwoo Choi #define CLK_PCLK_PMU_G3D 17 829453e519eSChanwoo Choi #define CLK_PCLK_SYSREG_G3D 18 830453e519eSChanwoo Choi #define CLK_SCLK_HPM_G3D 19 831453e519eSChanwoo Choi 832453e519eSChanwoo Choi #define G3D_NR_CLK 20 833453e519eSChanwoo Choi 8342a2f33e8SChanwoo Choi /* CMU_GSCL */ 8352a2f33e8SChanwoo Choi #define CLK_MOUT_ACLK_GSCL_111_USER 1 8362a2f33e8SChanwoo Choi #define CLK_MOUT_ACLK_GSCL_333_USER 2 8372a2f33e8SChanwoo Choi 8382a2f33e8SChanwoo Choi #define CLK_ACLK_BTS_GSCL2 3 8392a2f33e8SChanwoo Choi #define CLK_ACLK_BTS_GSCL1 4 8402a2f33e8SChanwoo Choi #define CLK_ACLK_BTS_GSCL0 5 8412a2f33e8SChanwoo Choi #define CLK_ACLK_AHB2APB_GSCLP 6 8422a2f33e8SChanwoo Choi #define CLK_ACLK_XIU_GSCLX 7 8432a2f33e8SChanwoo Choi #define CLK_ACLK_GSCLNP_111 8 8442a2f33e8SChanwoo Choi #define CLK_ACLK_GSCLRTND_333 9 8452a2f33e8SChanwoo Choi #define CLK_ACLK_GSCLBEND_333 10 8462a2f33e8SChanwoo Choi #define CLK_ACLK_GSD 11 8472a2f33e8SChanwoo Choi #define CLK_ACLK_GSCL2 12 8482a2f33e8SChanwoo Choi #define CLK_ACLK_GSCL1 13 8492a2f33e8SChanwoo Choi #define CLK_ACLK_GSCL0 14 8502a2f33e8SChanwoo Choi #define CLK_ACLK_SMMU_GSCL0 15 8512a2f33e8SChanwoo Choi #define CLK_ACLK_SMMU_GSCL1 16 8522a2f33e8SChanwoo Choi #define CLK_ACLK_SMMU_GSCL2 17 8532a2f33e8SChanwoo Choi #define CLK_PCLK_BTS_GSCL2 18 8542a2f33e8SChanwoo Choi #define CLK_PCLK_BTS_GSCL1 19 8552a2f33e8SChanwoo Choi #define CLK_PCLK_BTS_GSCL0 20 8562a2f33e8SChanwoo Choi #define CLK_PCLK_PMU_GSCL 21 8572a2f33e8SChanwoo Choi #define CLK_PCLK_SYSREG_GSCL 22 8582a2f33e8SChanwoo Choi #define CLK_PCLK_GSCL2 23 8592a2f33e8SChanwoo Choi #define CLK_PCLK_GSCL1 24 8602a2f33e8SChanwoo Choi #define CLK_PCLK_GSCL0 25 8612a2f33e8SChanwoo Choi #define CLK_PCLK_SMMU_GSCL0 26 8622a2f33e8SChanwoo Choi #define CLK_PCLK_SMMU_GSCL1 27 8632a2f33e8SChanwoo Choi #define CLK_PCLK_SMMU_GSCL2 28 8642a2f33e8SChanwoo Choi 8652a2f33e8SChanwoo Choi #define GSCL_NR_CLK 29 8662a2f33e8SChanwoo Choi 867df40a13cSChanwoo Choi /* CMU_APOLLO */ 868df40a13cSChanwoo Choi #define CLK_FOUT_APOLLO_PLL 1 869df40a13cSChanwoo Choi 870df40a13cSChanwoo Choi #define CLK_MOUT_APOLLO_PLL 2 871df40a13cSChanwoo Choi #define CLK_MOUT_BUS_PLL_APOLLO_USER 3 872df40a13cSChanwoo Choi #define CLK_MOUT_APOLLO 4 873df40a13cSChanwoo Choi 874df40a13cSChanwoo Choi #define CLK_DIV_CNTCLK_APOLLO 5 875df40a13cSChanwoo Choi #define CLK_DIV_PCLK_DBG_APOLLO 6 876df40a13cSChanwoo Choi #define CLK_DIV_ATCLK_APOLLO 7 877df40a13cSChanwoo Choi #define CLK_DIV_PCLK_APOLLO 8 878df40a13cSChanwoo Choi #define CLK_DIV_ACLK_APOLLO 9 879df40a13cSChanwoo Choi #define CLK_DIV_APOLLO2 10 880df40a13cSChanwoo Choi #define CLK_DIV_APOLLO1 11 881df40a13cSChanwoo Choi #define CLK_DIV_SCLK_HPM_APOLLO 12 882df40a13cSChanwoo Choi #define CLK_DIV_APOLLO_PLL 13 883df40a13cSChanwoo Choi 884df40a13cSChanwoo Choi #define CLK_ACLK_ATBDS_APOLLO_3 14 885df40a13cSChanwoo Choi #define CLK_ACLK_ATBDS_APOLLO_2 15 886df40a13cSChanwoo Choi #define CLK_ACLK_ATBDS_APOLLO_1 16 887df40a13cSChanwoo Choi #define CLK_ACLK_ATBDS_APOLLO_0 17 888df40a13cSChanwoo Choi #define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18 889df40a13cSChanwoo Choi #define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19 890df40a13cSChanwoo Choi #define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20 891df40a13cSChanwoo Choi #define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21 892df40a13cSChanwoo Choi #define CLK_ACLK_ASYNCACES_APOLLO_CCI 22 893df40a13cSChanwoo Choi #define CLK_ACLK_AHB2APB_APOLLOP 23 894df40a13cSChanwoo Choi #define CLK_ACLK_APOLLONP_200 24 895df40a13cSChanwoo Choi #define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25 896df40a13cSChanwoo Choi #define CLK_PCLK_PMU_APOLLO 26 897df40a13cSChanwoo Choi #define CLK_PCLK_SYSREG_APOLLO 27 898df40a13cSChanwoo Choi #define CLK_CNTCLK_APOLLO 28 899df40a13cSChanwoo Choi #define CLK_SCLK_HPM_APOLLO 29 900df40a13cSChanwoo Choi #define CLK_SCLK_APOLLO 30 901df40a13cSChanwoo Choi 902df40a13cSChanwoo Choi #define APOLLO_NR_CLK 31 903df40a13cSChanwoo Choi 9046c5d76d1SChanwoo Choi /* CMU_ATLAS */ 9056c5d76d1SChanwoo Choi #define CLK_FOUT_ATLAS_PLL 1 9066c5d76d1SChanwoo Choi 9076c5d76d1SChanwoo Choi #define CLK_MOUT_ATLAS_PLL 2 9086c5d76d1SChanwoo Choi #define CLK_MOUT_BUS_PLL_ATLAS_USER 3 9096c5d76d1SChanwoo Choi #define CLK_MOUT_ATLAS 4 9106c5d76d1SChanwoo Choi 9116c5d76d1SChanwoo Choi #define CLK_DIV_CNTCLK_ATLAS 5 9126c5d76d1SChanwoo Choi #define CLK_DIV_PCLK_DBG_ATLAS 6 9136c5d76d1SChanwoo Choi #define CLK_DIV_ATCLK_ATLASO 7 9146c5d76d1SChanwoo Choi #define CLK_DIV_PCLK_ATLAS 8 9156c5d76d1SChanwoo Choi #define CLK_DIV_ACLK_ATLAS 9 9166c5d76d1SChanwoo Choi #define CLK_DIV_ATLAS2 10 9176c5d76d1SChanwoo Choi #define CLK_DIV_ATLAS1 11 9186c5d76d1SChanwoo Choi #define CLK_DIV_SCLK_HPM_ATLAS 12 9196c5d76d1SChanwoo Choi #define CLK_DIV_ATLAS_PLL 13 9206c5d76d1SChanwoo Choi 9216c5d76d1SChanwoo Choi #define CLK_ACLK_ATB_AUD_CSSYS 14 9226c5d76d1SChanwoo Choi #define CLK_ACLK_ATB_APOLLO3_CSSYS 15 9236c5d76d1SChanwoo Choi #define CLK_ACLK_ATB_APOLLO2_CSSYS 16 9246c5d76d1SChanwoo Choi #define CLK_ACLK_ATB_APOLLO1_CSSYS 17 9256c5d76d1SChanwoo Choi #define CLK_ACLK_ATB_APOLLO0_CSSYS 18 9266c5d76d1SChanwoo Choi #define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19 9276c5d76d1SChanwoo Choi #define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20 9286c5d76d1SChanwoo Choi #define CLK_ACLK_ASYNCACES_ATLAS_CCI 21 9296c5d76d1SChanwoo Choi #define CLK_ACLK_AHB2APB_ATLASP 22 9306c5d76d1SChanwoo Choi #define CLK_ACLK_ATLASNP_200 23 9316c5d76d1SChanwoo Choi #define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24 9326c5d76d1SChanwoo Choi #define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25 9336c5d76d1SChanwoo Choi #define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26 9346c5d76d1SChanwoo Choi #define CLK_PCLK_PMU_ATLAS 27 9356c5d76d1SChanwoo Choi #define CLK_PCLK_SYSREG_ATLAS 28 9366c5d76d1SChanwoo Choi #define CLK_PCLK_SECJTAG 29 9376c5d76d1SChanwoo Choi #define CLK_CNTCLK_ATLAS 30 9386c5d76d1SChanwoo Choi #define CLK_SCLK_FREQ_DET_ATLAS_PLL 31 9396c5d76d1SChanwoo Choi #define CLK_SCLK_HPM_ATLAS 32 9406c5d76d1SChanwoo Choi #define CLK_TRACECLK 33 9416c5d76d1SChanwoo Choi #define CLK_CTMCLK 34 9426c5d76d1SChanwoo Choi #define CLK_HCLK_CSSYS 35 9436c5d76d1SChanwoo Choi #define CLK_PCLK_DBG_CSSYS 36 9446c5d76d1SChanwoo Choi #define CLK_PCLK_DBG 37 9456c5d76d1SChanwoo Choi #define CLK_ATCLK 38 9466c5d76d1SChanwoo Choi #define CLK_SCLK_ATLAS 39 9476c5d76d1SChanwoo Choi 9486c5d76d1SChanwoo Choi #define ATLAS_NR_CLK 40 9496c5d76d1SChanwoo Choi 950b274bbfdSChanwoo Choi /* CMU_MSCL */ 951b274bbfdSChanwoo Choi #define CLK_MOUT_SCLK_JPEG_USER 1 952b274bbfdSChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_USER 2 953b274bbfdSChanwoo Choi #define CLK_MOUT_SCLK_JPEG 3 954b274bbfdSChanwoo Choi 955b274bbfdSChanwoo Choi #define CLK_DIV_PCLK_MSCL 4 956b274bbfdSChanwoo Choi 957b274bbfdSChanwoo Choi #define CLK_ACLK_BTS_JPEG 5 958b274bbfdSChanwoo Choi #define CLK_ACLK_BTS_M2MSCALER1 6 959b274bbfdSChanwoo Choi #define CLK_ACLK_BTS_M2MSCALER0 7 960b274bbfdSChanwoo Choi #define CLK_ACLK_AHB2APB_MSCL0P 8 961b274bbfdSChanwoo Choi #define CLK_ACLK_XIU_MSCLX 9 962b274bbfdSChanwoo Choi #define CLK_ACLK_MSCLNP_100 10 963b274bbfdSChanwoo Choi #define CLK_ACLK_MSCLND_400 11 964b274bbfdSChanwoo Choi #define CLK_ACLK_JPEG 12 965b274bbfdSChanwoo Choi #define CLK_ACLK_M2MSCALER1 13 966b274bbfdSChanwoo Choi #define CLK_ACLK_M2MSCALER0 14 967b274bbfdSChanwoo Choi #define CLK_ACLK_SMMU_M2MSCALER0 15 968b274bbfdSChanwoo Choi #define CLK_ACLK_SMMU_M2MSCALER1 16 969b274bbfdSChanwoo Choi #define CLK_ACLK_SMMU_JPEG 17 970b274bbfdSChanwoo Choi #define CLK_PCLK_BTS_JPEG 18 971b274bbfdSChanwoo Choi #define CLK_PCLK_BTS_M2MSCALER1 19 972b274bbfdSChanwoo Choi #define CLK_PCLK_BTS_M2MSCALER0 20 973b274bbfdSChanwoo Choi #define CLK_PCLK_PMU_MSCL 21 974b274bbfdSChanwoo Choi #define CLK_PCLK_SYSREG_MSCL 22 975b274bbfdSChanwoo Choi #define CLK_PCLK_JPEG 23 976b274bbfdSChanwoo Choi #define CLK_PCLK_M2MSCALER1 24 977b274bbfdSChanwoo Choi #define CLK_PCLK_M2MSCALER0 25 978b274bbfdSChanwoo Choi #define CLK_PCLK_SMMU_M2MSCALER0 26 979b274bbfdSChanwoo Choi #define CLK_PCLK_SMMU_M2MSCALER1 27 980b274bbfdSChanwoo Choi #define CLK_PCLK_SMMU_JPEG 28 981b274bbfdSChanwoo Choi #define CLK_SCLK_JPEG 29 982b274bbfdSChanwoo Choi 983b274bbfdSChanwoo Choi #define MSCL_NR_CLK 30 984b274bbfdSChanwoo Choi 9859910b6bbSChanwoo Choi /* CMU_MFC */ 9869910b6bbSChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_USER 1 9879910b6bbSChanwoo Choi 9889910b6bbSChanwoo Choi #define CLK_DIV_PCLK_MFC 2 9899910b6bbSChanwoo Choi 9909910b6bbSChanwoo Choi #define CLK_ACLK_BTS_MFC_1 3 9919910b6bbSChanwoo Choi #define CLK_ACLK_BTS_MFC_0 4 9929910b6bbSChanwoo Choi #define CLK_ACLK_AHB2APB_MFCP 5 9939910b6bbSChanwoo Choi #define CLK_ACLK_XIU_MFCX 6 9949910b6bbSChanwoo Choi #define CLK_ACLK_MFCNP_100 7 9959910b6bbSChanwoo Choi #define CLK_ACLK_MFCND_400 8 9969910b6bbSChanwoo Choi #define CLK_ACLK_MFC 9 9979910b6bbSChanwoo Choi #define CLK_ACLK_SMMU_MFC_1 10 9989910b6bbSChanwoo Choi #define CLK_ACLK_SMMU_MFC_0 11 9999910b6bbSChanwoo Choi #define CLK_PCLK_BTS_MFC_1 12 10009910b6bbSChanwoo Choi #define CLK_PCLK_BTS_MFC_0 13 10019910b6bbSChanwoo Choi #define CLK_PCLK_PMU_MFC 14 10029910b6bbSChanwoo Choi #define CLK_PCLK_SYSREG_MFC 15 10039910b6bbSChanwoo Choi #define CLK_PCLK_MFC 16 10049910b6bbSChanwoo Choi #define CLK_PCLK_SMMU_MFC_1 17 10059910b6bbSChanwoo Choi #define CLK_PCLK_SMMU_MFC_0 18 10069910b6bbSChanwoo Choi 10079910b6bbSChanwoo Choi #define MFC_NR_CLK 19 10089910b6bbSChanwoo Choi 100945e58aa5SChanwoo Choi /* CMU_HEVC */ 101045e58aa5SChanwoo Choi #define CLK_MOUT_ACLK_HEVC_400_USER 1 101145e58aa5SChanwoo Choi 101245e58aa5SChanwoo Choi #define CLK_DIV_PCLK_HEVC 2 101345e58aa5SChanwoo Choi 101445e58aa5SChanwoo Choi #define CLK_ACLK_BTS_HEVC_1 3 101545e58aa5SChanwoo Choi #define CLK_ACLK_BTS_HEVC_0 4 101645e58aa5SChanwoo Choi #define CLK_ACLK_AHB2APB_HEVCP 5 101745e58aa5SChanwoo Choi #define CLK_ACLK_XIU_HEVCX 6 101845e58aa5SChanwoo Choi #define CLK_ACLK_HEVCNP_100 7 101945e58aa5SChanwoo Choi #define CLK_ACLK_HEVCND_400 8 102045e58aa5SChanwoo Choi #define CLK_ACLK_HEVC 9 102145e58aa5SChanwoo Choi #define CLK_ACLK_SMMU_HEVC_1 10 102245e58aa5SChanwoo Choi #define CLK_ACLK_SMMU_HEVC_0 11 102345e58aa5SChanwoo Choi #define CLK_PCLK_BTS_HEVC_1 12 102445e58aa5SChanwoo Choi #define CLK_PCLK_BTS_HEVC_0 13 102545e58aa5SChanwoo Choi #define CLK_PCLK_PMU_HEVC 14 102645e58aa5SChanwoo Choi #define CLK_PCLK_SYSREG_HEVC 15 102745e58aa5SChanwoo Choi #define CLK_PCLK_HEVC 16 102845e58aa5SChanwoo Choi #define CLK_PCLK_SMMU_HEVC_1 17 102945e58aa5SChanwoo Choi #define CLK_PCLK_SMMU_HEVC_0 18 103045e58aa5SChanwoo Choi 103145e58aa5SChanwoo Choi #define HEVC_NR_CLK 19 103245e58aa5SChanwoo Choi 10338e46c4b8SChanwoo Choi /* CMU_ISP */ 10348e46c4b8SChanwoo Choi #define CLK_MOUT_ACLK_ISP_DIS_400_USER 1 10358e46c4b8SChanwoo Choi #define CLK_MOUT_ACLK_ISP_400_USER 2 10368e46c4b8SChanwoo Choi 10378e46c4b8SChanwoo Choi #define CLK_DIV_PCLK_ISP_DIS 3 10388e46c4b8SChanwoo Choi #define CLK_DIV_PCLK_ISP 4 10398e46c4b8SChanwoo Choi #define CLK_DIV_ACLK_ISP_D_200 5 10408e46c4b8SChanwoo Choi #define CLK_DIV_ACLK_ISP_C_200 6 10418e46c4b8SChanwoo Choi 10428e46c4b8SChanwoo Choi #define CLK_ACLK_ISP_D_GLUE 7 10438e46c4b8SChanwoo Choi #define CLK_ACLK_SCALERP 8 10448e46c4b8SChanwoo Choi #define CLK_ACLK_3DNR 9 10458e46c4b8SChanwoo Choi #define CLK_ACLK_DIS 10 10468e46c4b8SChanwoo Choi #define CLK_ACLK_SCALERC 11 10478e46c4b8SChanwoo Choi #define CLK_ACLK_DRC 12 10488e46c4b8SChanwoo Choi #define CLK_ACLK_ISP 13 10498e46c4b8SChanwoo Choi #define CLK_ACLK_AXIUS_SCALERP 14 10508e46c4b8SChanwoo Choi #define CLK_ACLK_AXIUS_SCALERC 15 10518e46c4b8SChanwoo Choi #define CLK_ACLK_AXIUS_DRC 16 10528e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAHBM_ISP2P 17 10538e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAHBM_ISP1P 18 10548e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DIS1 19 10558e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DIS0 20 10568e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DIS1 21 10578e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DIS0 22 10588e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ISP2P 23 10598e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ISP1P 24 10608e46c4b8SChanwoo Choi #define CLK_ACLK_AHB2APB_ISP2P 25 10618e46c4b8SChanwoo Choi #define CLK_ACLK_AHB2APB_ISP1P 26 10628e46c4b8SChanwoo Choi #define CLK_ACLK_AXI2APB_ISP2P 27 10638e46c4b8SChanwoo Choi #define CLK_ACLK_AXI2APB_ISP1P 28 10648e46c4b8SChanwoo Choi #define CLK_ACLK_XIU_ISPEX1 29 10658e46c4b8SChanwoo Choi #define CLK_ACLK_XIU_ISPEX0 30 10668e46c4b8SChanwoo Choi #define CLK_ACLK_ISPND_400 31 10678e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_SCALERP 32 10688e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_3DNR 33 10698e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_DIS1 34 10708e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_DIS0 35 10718e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_SCALERC 36 10728e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_DRC 37 10738e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_ISP 38 10748e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_SCALERP 39 10758e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_3DR 40 10768e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_DIS1 41 10778e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_DIS0 42 10788e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_SCALERC 43 10798e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_DRC 44 10808e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_ISP 45 10818e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_SCALERP 46 10828e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_3DNR 47 10838e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_DIS1 48 10848e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_DIS0 49 10858e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_SCALERC 50 10868e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_DRC 51 10878e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_ISP 52 10888e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_SCALERP 53 10898e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_3DNR 54 10908e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_DIS1 55 10918e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_DIS0 56 10928e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_SCALERC 57 10938e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_DRC 58 10948e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_ISP 59 10958e46c4b8SChanwoo Choi #define CLK_PCLK_ASYNCAXI_DIS1 60 10968e46c4b8SChanwoo Choi #define CLK_PCLK_ASYNCAXI_DIS0 61 10978e46c4b8SChanwoo Choi #define CLK_PCLK_PMU_ISP 62 10988e46c4b8SChanwoo Choi #define CLK_PCLK_SYSREG_ISP 63 10998e46c4b8SChanwoo Choi #define CLK_PCLK_CMU_ISP_LOCAL 64 11008e46c4b8SChanwoo Choi #define CLK_PCLK_SCALERP 65 11018e46c4b8SChanwoo Choi #define CLK_PCLK_3DNR 66 11028e46c4b8SChanwoo Choi #define CLK_PCLK_DIS_CORE 67 11038e46c4b8SChanwoo Choi #define CLK_PCLK_DIS 68 11048e46c4b8SChanwoo Choi #define CLK_PCLK_SCALERC 69 11058e46c4b8SChanwoo Choi #define CLK_PCLK_DRC 70 11068e46c4b8SChanwoo Choi #define CLK_PCLK_ISP 71 11078e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCS_DIS 72 11088e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCM_DIS 73 11098e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCS_SCALERP 74 11108e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCM_ISPD 75 11118e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCS_ISPC 76 11128e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCM_ISPC 77 11138e46c4b8SChanwoo Choi 11148e46c4b8SChanwoo Choi #define ISP_NR_CLK 78 11158e46c4b8SChanwoo Choi 111696bd6224SChanwoo Choi #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 1117