196bd6224SChanwoo Choi /* 296bd6224SChanwoo Choi * Copyright (c) 2014 Samsung Electronics Co., Ltd. 396bd6224SChanwoo Choi * Author: Chanwoo Choi <cw00.choi@samsung.com> 496bd6224SChanwoo Choi * 596bd6224SChanwoo Choi * This program is free software; you can redistribute it and/or modify 696bd6224SChanwoo Choi * it under the terms of the GNU General Public License version 2 as 796bd6224SChanwoo Choi * published by the Free Software Foundation. 896bd6224SChanwoo Choi */ 996bd6224SChanwoo Choi 1096bd6224SChanwoo Choi #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 1196bd6224SChanwoo Choi #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 1296bd6224SChanwoo Choi 1396bd6224SChanwoo Choi /* CMU_TOP */ 1496bd6224SChanwoo Choi #define CLK_FOUT_ISP_PLL 1 1596bd6224SChanwoo Choi #define CLK_FOUT_AUD_PLL 2 1696bd6224SChanwoo Choi 1796bd6224SChanwoo Choi #define CLK_MOUT_AUD_PLL 10 1896bd6224SChanwoo Choi #define CLK_MOUT_ISP_PLL 11 1996bd6224SChanwoo Choi #define CLK_MOUT_AUD_PLL_USER_T 12 2096bd6224SChanwoo Choi #define CLK_MOUT_MPHY_PLL_USER 13 2196bd6224SChanwoo Choi #define CLK_MOUT_MFC_PLL_USER 14 2296bd6224SChanwoo Choi #define CLK_MOUT_BUS_PLL_USER 15 2396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_HEVC_400 16 2496bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_333 17 2596bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_B 18 2696bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_A 19 2796bd6224SChanwoo Choi #define CLK_MOUT_ACLK_ISP_DIS_400 20 2896bd6224SChanwoo Choi #define CLK_MOUT_ACLK_ISP_400 21 2996bd6224SChanwoo Choi #define CLK_MOUT_ACLK_BUS0_400 22 3096bd6224SChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_B 23 3196bd6224SChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_A 24 3296bd6224SChanwoo Choi #define CLK_MOUT_ACLK_GSCL_333 25 3396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_G2D_400_B 26 3496bd6224SChanwoo Choi #define CLK_MOUT_ACLK_G2D_400_A 27 3596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_C 28 3696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_B 29 3796bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_A 30 3896bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_B 31 3996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_A 32 4096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_B 33 4196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_A 34 4296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_D 35 4396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_C 36 4496bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_B 37 4596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_A 38 4696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI4 39 4796bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI3 40 4896bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART2 41 4996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART1 42 5096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART0 43 5196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI2 44 5296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI1 45 5396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI0 46 5423236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_C 47 5523236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_B 48 5623236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_A 49 5723236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR2 50 5823236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR1 51 5923236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR0 52 6023236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_UART 53 6123236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI1 54 6223236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI0 55 6323236496SChanwoo Choi #define CLK_MOUT_SCLK_PCIE_100 56 6423236496SChanwoo Choi #define CLK_MOUT_SCLK_UFSUNIPRO 57 6523236496SChanwoo Choi #define CLK_MOUT_SCLK_USBHOST30 58 6623236496SChanwoo Choi #define CLK_MOUT_SCLK_USBDRD30 59 6723236496SChanwoo Choi #define CLK_MOUT_SCLK_SLIMBUS 60 6823236496SChanwoo Choi #define CLK_MOUT_SCLK_SPDIF 61 6923236496SChanwoo Choi #define CLK_MOUT_SCLK_AUDIO1 62 7023236496SChanwoo Choi #define CLK_MOUT_SCLK_AUDIO0 63 712a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_HDMI_SPDIF 64 7296bd6224SChanwoo Choi 7396bd6224SChanwoo Choi #define CLK_DIV_ACLK_FSYS_200 100 7496bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_SSSX_266 101 7596bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_200 102 7696bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_266 103 7796bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIC_66_B 104 7896bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIC_66_A 105 7996bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIS_66_B 106 8096bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIS_66_A 107 8196bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC1_B 108 8296bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC1_A 109 8396bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC0_B 110 8496bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC0_A 111 8596bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC2_B 112 8696bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC2_A 113 8796bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI1_B 114 8896bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI1_A 115 8996bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI0_B 116 9096bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI0_A 117 9196bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI2_B 118 9296bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI2_A 119 9396bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART2 120 9496bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART1 121 9596bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART0 122 9696bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI4_B 123 9796bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI4_A 124 9896bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI3_B 125 9996bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI3_A 126 10023236496SChanwoo Choi #define CLK_DIV_SCLK_I2S1 127 10123236496SChanwoo Choi #define CLK_DIV_SCLK_PCM1 128 10223236496SChanwoo Choi #define CLK_DIV_SCLK_AUDIO1 129 10323236496SChanwoo Choi #define CLK_DIV_SCLK_AUDIO0 130 104a29308daSChanwoo Choi #define CLK_DIV_ACLK_GSCL_111 131 105a29308daSChanwoo Choi #define CLK_DIV_ACLK_GSCL_333 132 106a29308daSChanwoo Choi #define CLK_DIV_ACLK_HEVC_400 133 107a29308daSChanwoo Choi #define CLK_DIV_ACLK_MFC_400 134 108a29308daSChanwoo Choi #define CLK_DIV_ACLK_G2D_266 135 109a29308daSChanwoo Choi #define CLK_DIV_ACLK_G2D_400 136 1105785d6e6SChanwoo Choi #define CLK_DIV_ACLK_G3D_400 137 1115785d6e6SChanwoo Choi #define CLK_DIV_ACLK_BUS0_400 138 1125785d6e6SChanwoo Choi #define CLK_DIV_ACLK_BUS1_400 139 1134b801355SChanwoo Choi #define CLK_DIV_SCLK_PCIE_100 140 1144b801355SChanwoo Choi #define CLK_DIV_SCLK_USBHOST30 141 1154b801355SChanwoo Choi #define CLK_DIV_SCLK_UFSUNIPRO 142 1164b801355SChanwoo Choi #define CLK_DIV_SCLK_USBDRD30 143 117b274bbfdSChanwoo Choi #define CLK_DIV_SCLK_JPEG 144 118b274bbfdSChanwoo Choi #define CLK_DIV_ACLK_MSCL_400 145 1198e46c4b8SChanwoo Choi #define CLK_DIV_ACLK_ISP_DIS_400 146 1208e46c4b8SChanwoo Choi #define CLK_DIV_ACLK_ISP_400 147 1216958f22fSChanwoo Choi #define CLK_DIV_ACLK_CAM0_333 148 1226958f22fSChanwoo Choi #define CLK_DIV_ACLK_CAM0_400 149 1236958f22fSChanwoo Choi #define CLK_DIV_ACLK_CAM0_552 150 12496bd6224SChanwoo Choi 12596bd6224SChanwoo Choi #define CLK_ACLK_PERIC_66 200 12696bd6224SChanwoo Choi #define CLK_ACLK_PERIS_66 201 12796bd6224SChanwoo Choi #define CLK_ACLK_FSYS_200 202 12896bd6224SChanwoo Choi #define CLK_SCLK_MMC2_FSYS 203 12996bd6224SChanwoo Choi #define CLK_SCLK_MMC1_FSYS 204 13096bd6224SChanwoo Choi #define CLK_SCLK_MMC0_FSYS 205 13196bd6224SChanwoo Choi #define CLK_SCLK_SPI4_PERIC 206 13296bd6224SChanwoo Choi #define CLK_SCLK_SPI3_PERIC 207 13396bd6224SChanwoo Choi #define CLK_SCLK_UART2_PERIC 208 13496bd6224SChanwoo Choi #define CLK_SCLK_UART1_PERIC 209 13596bd6224SChanwoo Choi #define CLK_SCLK_UART0_PERIC 210 13696bd6224SChanwoo Choi #define CLK_SCLK_SPI2_PERIC 211 13796bd6224SChanwoo Choi #define CLK_SCLK_SPI1_PERIC 212 13896bd6224SChanwoo Choi #define CLK_SCLK_SPI0_PERIC 213 13923236496SChanwoo Choi #define CLK_SCLK_SPDIF_PERIC 214 14023236496SChanwoo Choi #define CLK_SCLK_I2S1_PERIC 215 14123236496SChanwoo Choi #define CLK_SCLK_PCM1_PERIC 216 14223236496SChanwoo Choi #define CLK_SCLK_SLIMBUS 217 14323236496SChanwoo Choi #define CLK_SCLK_AUDIO1 218 14423236496SChanwoo Choi #define CLK_SCLK_AUDIO0 219 145a29308daSChanwoo Choi #define CLK_ACLK_G2D_266 220 146a29308daSChanwoo Choi #define CLK_ACLK_G2D_400 221 1475785d6e6SChanwoo Choi #define CLK_ACLK_G3D_400 222 1485785d6e6SChanwoo Choi #define CLK_ACLK_IMEM_SSX_266 223 1495785d6e6SChanwoo Choi #define CLK_ACLK_BUS0_400 224 1505785d6e6SChanwoo Choi #define CLK_ACLK_BUS1_400 225 1515785d6e6SChanwoo Choi #define CLK_ACLK_IMEM_200 226 1525785d6e6SChanwoo Choi #define CLK_ACLK_IMEM_266 227 1534b801355SChanwoo Choi #define CLK_SCLK_PCIE_100_FSYS 228 1544b801355SChanwoo Choi #define CLK_SCLK_UFSUNIPRO_FSYS 229 1554b801355SChanwoo Choi #define CLK_SCLK_USBHOST30_FSYS 230 1564b801355SChanwoo Choi #define CLK_SCLK_USBDRD30_FSYS 231 1572a2f33e8SChanwoo Choi #define CLK_ACLK_GSCL_111 232 1582a2f33e8SChanwoo Choi #define CLK_ACLK_GSCL_333 233 159b274bbfdSChanwoo Choi #define CLK_SCLK_JPEG_MSCL 234 160b274bbfdSChanwoo Choi #define CLK_ACLK_MSCL_400 235 1619910b6bbSChanwoo Choi #define CLK_ACLK_MFC_400 236 16245e58aa5SChanwoo Choi #define CLK_ACLK_HEVC_400 237 1638e46c4b8SChanwoo Choi #define CLK_ACLK_ISP_DIS_400 238 1648e46c4b8SChanwoo Choi #define CLK_ACLK_ISP_400 239 1656958f22fSChanwoo Choi #define CLK_ACLK_CAM0_333 240 1666958f22fSChanwoo Choi #define CLK_ACLK_CAM0_400 241 1676958f22fSChanwoo Choi #define CLK_ACLK_CAM0_552 242 16896bd6224SChanwoo Choi 1696958f22fSChanwoo Choi #define TOP_NR_CLK 243 17096bd6224SChanwoo Choi 17196bd6224SChanwoo Choi /* CMU_CPIF */ 17296bd6224SChanwoo Choi #define CLK_FOUT_MPHY_PLL 1 17396bd6224SChanwoo Choi 17496bd6224SChanwoo Choi #define CLK_MOUT_MPHY_PLL 2 17596bd6224SChanwoo Choi 17696bd6224SChanwoo Choi #define CLK_DIV_SCLK_MPHY 10 17796bd6224SChanwoo Choi 17896bd6224SChanwoo Choi #define CLK_SCLK_MPHY_PLL 11 17996bd6224SChanwoo Choi #define CLK_SCLK_UFS_MPHY 11 18096bd6224SChanwoo Choi 18196bd6224SChanwoo Choi #define CPIF_NR_CLK 12 18296bd6224SChanwoo Choi 18396bd6224SChanwoo Choi /* CMU_MIF */ 18496bd6224SChanwoo Choi #define CLK_FOUT_MEM0_PLL 1 18596bd6224SChanwoo Choi #define CLK_FOUT_MEM1_PLL 2 18696bd6224SChanwoo Choi #define CLK_FOUT_BUS_PLL 3 18796bd6224SChanwoo Choi #define CLK_FOUT_MFC_PLL 4 18806d2f9dfSChanwoo Choi #define CLK_DOUT_MFC_PLL 5 18906d2f9dfSChanwoo Choi #define CLK_DOUT_BUS_PLL 6 19006d2f9dfSChanwoo Choi #define CLK_DOUT_MEM1_PLL 7 19106d2f9dfSChanwoo Choi #define CLK_DOUT_MEM0_PLL 8 19296bd6224SChanwoo Choi 19306d2f9dfSChanwoo Choi #define CLK_MOUT_MFC_PLL_DIV2 10 19406d2f9dfSChanwoo Choi #define CLK_MOUT_BUS_PLL_DIV2 11 19506d2f9dfSChanwoo Choi #define CLK_MOUT_MEM1_PLL_DIV2 12 19606d2f9dfSChanwoo Choi #define CLK_MOUT_MEM0_PLL_DIV2 13 19706d2f9dfSChanwoo Choi #define CLK_MOUT_MFC_PLL 14 19806d2f9dfSChanwoo Choi #define CLK_MOUT_BUS_PLL 15 19906d2f9dfSChanwoo Choi #define CLK_MOUT_MEM1_PLL 16 20006d2f9dfSChanwoo Choi #define CLK_MOUT_MEM0_PLL 17 20106d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_C 18 20206d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_B 19 20306d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_A 20 20406d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_C 21 20506d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_B 22 20606d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_A 23 20706d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_MIFNM_200 24 20806d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_MIFNM_400 25 20906d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_B 26 21006d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_A 27 21106d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_C 28 21206d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_B 29 21306d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_A 30 21406d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_C 31 21506d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_B 32 21606d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_A 33 21706d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34 21806d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35 21906d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36 22006d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_C 37 22106d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_B 38 22206d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_A 39 22306d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_C 40 22406d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_B 41 22506d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_A 42 22606d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46 22706d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47 22806d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48 22906d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_C 49 23006d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_B 50 23106d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_A 51 23206d2f9dfSChanwoo Choi 23306d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_HPM_MIF 55 23406d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DREX1 56 23506d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DREX0 57 23606d2f9dfSChanwoo Choi #define CLK_DIV_CLK2XPHY 58 23706d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_266 59 23806d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIFND_133 60 23906d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_133 61 24006d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIFNM_200 62 24106d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_200 63 24206d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_400 64 24306d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_BUS2_400 65 24406d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DISP_333 66 24506d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_CPIF_200 67 24606d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSIM1 68 24706d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_VCLK 69 24806d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSIM0 70 24906d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSD 71 25006d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_ECLK 72 25106d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_VCLK 73 25206d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_ECLK 74 25306d2f9dfSChanwoo Choi #define CLK_DIV_MIF_PRE 75 25406d2f9dfSChanwoo Choi 25506d2f9dfSChanwoo Choi #define CLK_CLK2X_PHY1 80 25606d2f9dfSChanwoo Choi #define CLK_CLK2X_PHY0 81 25706d2f9dfSChanwoo Choi #define CLK_CLKM_PHY1 82 25806d2f9dfSChanwoo Choi #define CLK_CLKM_PHY0 83 25906d2f9dfSChanwoo Choi #define CLK_RCLK_DREX1 84 26006d2f9dfSChanwoo Choi #define CLK_RCLK_DREX0 85 26106d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_TZ 86 26206d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_TZ 87 26306d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_PEREV 88 26406d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_PEREV 89 26506d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_MEMIF 90 26606d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_MEMIF 91 26706d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_SCH 92 26806d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_SCH 93 26906d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_BUSIF 94 27006d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_BUSIF 95 27106d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_BUSIF_RD 96 27206d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_BUSIF_RD 97 27306d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1 98 27406d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0 99 27506d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100 27606d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101 27706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102 27806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103 27906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104 28006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105 28106d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_CP1 106 28206d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_CP1 107 28306d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_CP0 108 28406d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_CP0 109 28506d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_3 110 28606d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_3 111 28706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_1 112 28806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_1 113 28906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_0 114 29006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_0 115 29106d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_3 116 29206d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_3 117 29306d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_1 118 29406d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_1 119 29506d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_0 120 29606d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_0 121 29706d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF2P 122 29806d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF1P 123 29906d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF0P 124 30006d2f9dfSChanwoo Choi #define CLK_ACLK_IXIU_CCI 125 30106d2f9dfSChanwoo Choi #define CLK_ACLK_XIU_MIFSFRX 126 30206d2f9dfSChanwoo Choi #define CLK_ACLK_MIFNP_133 127 30306d2f9dfSChanwoo Choi #define CLK_ACLK_MIFNM_200 128 30406d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_133 129 30506d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_400 130 30606d2f9dfSChanwoo Choi #define CLK_ACLK_CCI 131 30706d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_266 132 30806d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S3 133 30906d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S1 134 31006d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S0 135 31106d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S3 136 31206d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S1 137 31306d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S0 138 31406d2f9dfSChanwoo Choi #define CLK_ACLK_BTS_APOLLO 139 31506d2f9dfSChanwoo Choi #define CLK_ACLK_BTS_ATLAS 140 31606d2f9dfSChanwoo Choi #define CLK_ACLK_ACE_SEL_APOLL 141 31706d2f9dfSChanwoo Choi #define CLK_ACLK_ACE_SEL_ATLAS 142 31806d2f9dfSChanwoo Choi #define CLK_ACLK_AXIDS_CCI_MIFSFRX 143 31906d2f9dfSChanwoo Choi #define CLK_ACLK_AXIUS_ATLAS_CCI 144 32006d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDNS_CCI 145 32106d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDN_CCI 146 32206d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDN_NOC_D 147 32306d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148 32406d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149 32506d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150 32606d2f9dfSChanwoo Choi #define CLK_ACLK_BUS2_400 151 32706d2f9dfSChanwoo Choi #define CLK_ACLK_DISP_333 152 32806d2f9dfSChanwoo Choi #define CLK_ACLK_CPIF_200 153 32906d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S3 154 33006d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S1 155 33106d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S0 156 33206d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S3 157 33306d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S1 158 33406d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S0 159 33506d2f9dfSChanwoo Choi #define CLK_PCLK_BTS_APOLLO 160 33606d2f9dfSChanwoo Choi #define CLK_PCLK_BTS_ATLAS 161 33706d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162 33806d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_CP1 163 33906d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_CP0 164 34006d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_3 165 34106d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_1 166 34206d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_0 167 34306d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_3 168 34406d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_1 169 34506d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_0 170 34606d2f9dfSChanwoo Choi #define CLK_PCLK_MIFSRVND_133 171 34706d2f9dfSChanwoo Choi #define CLK_PCLK_PMU_MIF 172 34806d2f9dfSChanwoo Choi #define CLK_PCLK_SYSREG_MIF 173 34906d2f9dfSChanwoo Choi #define CLK_PCLK_GPIO_ALIVE 174 35006d2f9dfSChanwoo Choi #define CLK_PCLK_ABB 175 35106d2f9dfSChanwoo Choi #define CLK_PCLK_PMU_APBIF 176 35206d2f9dfSChanwoo Choi #define CLK_PCLK_DDR_PHY1 177 35306d2f9dfSChanwoo Choi #define CLK_PCLK_DREX1 178 35406d2f9dfSChanwoo Choi #define CLK_PCLK_DDR_PHY0 179 35506d2f9dfSChanwoo Choi #define CLK_PCLK_DREX0 180 35606d2f9dfSChanwoo Choi #define CLK_PCLK_DREX0_TZ 181 35706d2f9dfSChanwoo Choi #define CLK_PCLK_DREX1_TZ 182 35806d2f9dfSChanwoo Choi #define CLK_PCLK_MONOTONIC_CNT 183 35906d2f9dfSChanwoo Choi #define CLK_PCLK_RTC 184 36006d2f9dfSChanwoo Choi #define CLK_SCLK_DSIM1_DISP 185 36106d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_TV_VCLK_DISP 186 36206d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_BUS_PLL 187 36306d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MFC_PLL 188 36406d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MEM0_PLL 189 36506d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MEM1_PLL 190 36606d2f9dfSChanwoo Choi #define CLK_SCLK_DSIM0_DISP 191 36706d2f9dfSChanwoo Choi #define CLK_SCLK_DSD_DISP 192 36806d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_TV_ECLK_DISP 193 36906d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_VCLK_DISP 194 37006d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_ECLK_DISP 195 37106d2f9dfSChanwoo Choi #define CLK_SCLK_HPM_MIF 196 37206d2f9dfSChanwoo Choi #define CLK_SCLK_MFC_PLL 197 37306d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL 198 37406d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL_APOLLO 199 37506d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL_ATLAS 200 3762a1808a6SChanwoo Choi #define CLK_SCLK_HDMI_SPDIF_DISP 201 37706d2f9dfSChanwoo Choi 3782a1808a6SChanwoo Choi #define MIF_NR_CLK 202 37996bd6224SChanwoo Choi 38096bd6224SChanwoo Choi /* CMU_PERIC */ 38196bd6224SChanwoo Choi #define CLK_PCLK_SPI2 1 38296bd6224SChanwoo Choi #define CLK_PCLK_SPI1 2 38396bd6224SChanwoo Choi #define CLK_PCLK_SPI0 3 38496bd6224SChanwoo Choi #define CLK_PCLK_UART2 4 38596bd6224SChanwoo Choi #define CLK_PCLK_UART1 5 38696bd6224SChanwoo Choi #define CLK_PCLK_UART0 6 38796bd6224SChanwoo Choi #define CLK_PCLK_HSI2C3 7 38896bd6224SChanwoo Choi #define CLK_PCLK_HSI2C2 8 38996bd6224SChanwoo Choi #define CLK_PCLK_HSI2C1 9 39096bd6224SChanwoo Choi #define CLK_PCLK_HSI2C0 10 39196bd6224SChanwoo Choi #define CLK_PCLK_I2C7 11 39296bd6224SChanwoo Choi #define CLK_PCLK_I2C6 12 39396bd6224SChanwoo Choi #define CLK_PCLK_I2C5 13 39496bd6224SChanwoo Choi #define CLK_PCLK_I2C4 14 39596bd6224SChanwoo Choi #define CLK_PCLK_I2C3 15 39696bd6224SChanwoo Choi #define CLK_PCLK_I2C2 16 39796bd6224SChanwoo Choi #define CLK_PCLK_I2C1 17 39896bd6224SChanwoo Choi #define CLK_PCLK_I2C0 18 39996bd6224SChanwoo Choi #define CLK_PCLK_SPI4 19 40096bd6224SChanwoo Choi #define CLK_PCLK_SPI3 20 40196bd6224SChanwoo Choi #define CLK_PCLK_HSI2C11 21 40296bd6224SChanwoo Choi #define CLK_PCLK_HSI2C10 22 40396bd6224SChanwoo Choi #define CLK_PCLK_HSI2C9 23 40496bd6224SChanwoo Choi #define CLK_PCLK_HSI2C8 24 40596bd6224SChanwoo Choi #define CLK_PCLK_HSI2C7 25 40696bd6224SChanwoo Choi #define CLK_PCLK_HSI2C6 26 40796bd6224SChanwoo Choi #define CLK_PCLK_HSI2C5 27 40896bd6224SChanwoo Choi #define CLK_PCLK_HSI2C4 28 40996bd6224SChanwoo Choi #define CLK_SCLK_SPI4 29 41096bd6224SChanwoo Choi #define CLK_SCLK_SPI3 30 41196bd6224SChanwoo Choi #define CLK_SCLK_SPI2 31 41296bd6224SChanwoo Choi #define CLK_SCLK_SPI1 32 41396bd6224SChanwoo Choi #define CLK_SCLK_SPI0 33 41496bd6224SChanwoo Choi #define CLK_SCLK_UART2 34 41596bd6224SChanwoo Choi #define CLK_SCLK_UART1 35 41696bd6224SChanwoo Choi #define CLK_SCLK_UART0 36 417d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC2P 37 418d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC1P 38 419d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC0P 39 420d0f5de66SChanwoo Choi #define CLK_ACLK_PERICNP_66 40 421d0f5de66SChanwoo Choi #define CLK_PCLK_SCI 41 422d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_FINGER 42 423d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_ESE 43 424d0f5de66SChanwoo Choi #define CLK_PCLK_PWM 44 425d0f5de66SChanwoo Choi #define CLK_PCLK_SPDIF 45 426d0f5de66SChanwoo Choi #define CLK_PCLK_PCM1 46 427d0f5de66SChanwoo Choi #define CLK_PCLK_I2S1 47 428d0f5de66SChanwoo Choi #define CLK_PCLK_ADCIF 48 429d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_TOUCH 49 430d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_NFC 50 431d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_PERIC 51 432d0f5de66SChanwoo Choi #define CLK_PCLK_PMU_PERIC 52 433d0f5de66SChanwoo Choi #define CLK_PCLK_SYSREG_PERIC 53 434d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI4 54 435d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI3 55 436d0f5de66SChanwoo Choi #define CLK_SCLK_SCI 56 437d0f5de66SChanwoo Choi #define CLK_SCLK_SC_IN 57 438d0f5de66SChanwoo Choi #define CLK_SCLK_PWM 58 439d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI2 59 440d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI1 60 441d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI0 61 442d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_I2S1_BCLK 62 443d0f5de66SChanwoo Choi #define CLK_SCLK_SPDIF 63 444d0f5de66SChanwoo Choi #define CLK_SCLK_PCM1 64 445d0f5de66SChanwoo Choi #define CLK_SCLK_I2S1 65 44696bd6224SChanwoo Choi 447d0f5de66SChanwoo Choi #define CLK_DIV_SCLK_SCI 70 448d0f5de66SChanwoo Choi #define CLK_DIV_SCLK_SC_IN 71 449d0f5de66SChanwoo Choi 450d0f5de66SChanwoo Choi #define PERIC_NR_CLK 72 45196bd6224SChanwoo Choi 45296bd6224SChanwoo Choi /* CMU_PERIS */ 45396bd6224SChanwoo Choi #define CLK_PCLK_HPM_APBIF 1 45496bd6224SChanwoo Choi #define CLK_PCLK_TMU1_APBIF 2 45596bd6224SChanwoo Choi #define CLK_PCLK_TMU0_APBIF 3 45696bd6224SChanwoo Choi #define CLK_PCLK_PMU_PERIS 4 45796bd6224SChanwoo Choi #define CLK_PCLK_SYSREG_PERIS 5 45896bd6224SChanwoo Choi #define CLK_PCLK_CMU_TOP_APBIF 6 45996bd6224SChanwoo Choi #define CLK_PCLK_WDT_APOLLO 7 46096bd6224SChanwoo Choi #define CLK_PCLK_WDT_ATLAS 8 46196bd6224SChanwoo Choi #define CLK_PCLK_MCT 9 46296bd6224SChanwoo Choi #define CLK_PCLK_HDMI_CEC 10 46356bcf3f3SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIS1P 11 46456bcf3f3SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIS0P 12 46556bcf3f3SChanwoo Choi #define CLK_ACLK_PERISNP_66 13 46656bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC12 14 46756bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC11 15 46856bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC10 16 46956bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC9 17 47056bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC8 18 47156bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC7 19 47256bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC6 20 47356bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC5 21 47456bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC4 22 47556bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC3 23 47656bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC2 24 47756bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC1 25 47856bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC0 26 47956bcf3f3SChanwoo Choi #define CLK_PCLK_SECKEY_APBIF 27 48056bcf3f3SChanwoo Choi #define CLK_PCLK_CHIPID_APBIF 28 48156bcf3f3SChanwoo Choi #define CLK_PCLK_TOPRTC 29 48256bcf3f3SChanwoo Choi #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 48356bcf3f3SChanwoo Choi #define CLK_PCLK_ANTIRBK_CNT_APBIF 31 48456bcf3f3SChanwoo Choi #define CLK_PCLK_OTP_CON_APBIF 32 48556bcf3f3SChanwoo Choi #define CLK_SCLK_ASV_TB 33 48656bcf3f3SChanwoo Choi #define CLK_SCLK_TMU1 34 48756bcf3f3SChanwoo Choi #define CLK_SCLK_TMU0 35 48856bcf3f3SChanwoo Choi #define CLK_SCLK_SECKEY 36 48956bcf3f3SChanwoo Choi #define CLK_SCLK_CHIPID 37 49056bcf3f3SChanwoo Choi #define CLK_SCLK_TOPRTC 38 49156bcf3f3SChanwoo Choi #define CLK_SCLK_CUSTOM_EFUSE 39 49256bcf3f3SChanwoo Choi #define CLK_SCLK_ANTIRBK_CNT 40 49356bcf3f3SChanwoo Choi #define CLK_SCLK_OTP_CON 41 49496bd6224SChanwoo Choi 49556bcf3f3SChanwoo Choi #define PERIS_NR_CLK 42 49696bd6224SChanwoo Choi 49796bd6224SChanwoo Choi /* CMU_FSYS */ 49896bd6224SChanwoo Choi #define CLK_MOUT_ACLK_FSYS_200_USER 1 49996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_USER 2 50096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_USER 3 50196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_USER 4 5024b801355SChanwoo Choi #define CLK_MOUT_SCLK_UFS_MPHY_USER 5 5034b801355SChanwoo Choi #define CLK_MOUT_SCLK_PCIE_100_USER 6 5044b801355SChanwoo Choi #define CLK_MOUT_SCLK_UFSUNIPRO_USER 7 5054b801355SChanwoo Choi #define CLK_MOUT_SCLK_USBHOST30_USER 8 5064b801355SChanwoo Choi #define CLK_MOUT_SCLK_USBDRD30_USER 9 5074b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10 5084b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11 5094b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12 5104b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13 5114b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14 5124b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15 5134b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16 5144b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17 5154b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18 5164b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19 5174b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20 5184b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21 5194b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22 5204b801355SChanwoo Choi #define CLK_MOUT_SCLK_MPHY 23 5214b801355SChanwoo Choi 5224b801355SChanwoo Choi #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25 5234b801355SChanwoo Choi #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26 5244b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27 5254b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28 5264b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29 5274b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30 5284b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31 5294b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32 5304b801355SChanwoo Choi #define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33 5314b801355SChanwoo Choi #define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34 5324b801355SChanwoo Choi #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35 5334b801355SChanwoo Choi #define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36 5344b801355SChanwoo Choi #define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37 53596bd6224SChanwoo Choi 53696bd6224SChanwoo Choi #define CLK_ACLK_PCIE 50 53796bd6224SChanwoo Choi #define CLK_ACLK_PDMA1 51 53896bd6224SChanwoo Choi #define CLK_ACLK_TSI 52 53996bd6224SChanwoo Choi #define CLK_ACLK_MMC2 53 54096bd6224SChanwoo Choi #define CLK_ACLK_MMC1 54 54196bd6224SChanwoo Choi #define CLK_ACLK_MMC0 55 54296bd6224SChanwoo Choi #define CLK_ACLK_UFS 56 54396bd6224SChanwoo Choi #define CLK_ACLK_USBHOST20 57 54496bd6224SChanwoo Choi #define CLK_ACLK_USBHOST30 58 54596bd6224SChanwoo Choi #define CLK_ACLK_USBDRD30 59 54696bd6224SChanwoo Choi #define CLK_ACLK_PDMA0 60 54796bd6224SChanwoo Choi #define CLK_SCLK_MMC2 61 54896bd6224SChanwoo Choi #define CLK_SCLK_MMC1 62 54996bd6224SChanwoo Choi #define CLK_SCLK_MMC0 63 55096bd6224SChanwoo Choi #define CLK_PDMA1 64 55196bd6224SChanwoo Choi #define CLK_PDMA0 65 5524b801355SChanwoo Choi #define CLK_ACLK_XIU_FSYSPX 66 5534b801355SChanwoo Choi #define CLK_ACLK_AHB_USBLINKH1 67 5544b801355SChanwoo Choi #define CLK_ACLK_SMMU_PDMA1 68 5554b801355SChanwoo Choi #define CLK_ACLK_BTS_PCIE 69 5564b801355SChanwoo Choi #define CLK_ACLK_AXIUS_PDMA1 70 5574b801355SChanwoo Choi #define CLK_ACLK_SMMU_PDMA0 71 5584b801355SChanwoo Choi #define CLK_ACLK_BTS_UFS 72 5594b801355SChanwoo Choi #define CLK_ACLK_BTS_USBHOST30 73 5604b801355SChanwoo Choi #define CLK_ACLK_BTS_USBDRD30 74 5614b801355SChanwoo Choi #define CLK_ACLK_AXIUS_PDMA0 75 5624b801355SChanwoo Choi #define CLK_ACLK_AXIUS_USBHS 76 5634b801355SChanwoo Choi #define CLK_ACLK_AXIUS_FSYSSX 77 5644b801355SChanwoo Choi #define CLK_ACLK_AHB2APB_FSYSP 78 5654b801355SChanwoo Choi #define CLK_ACLK_AHB2AXI_USBHS 79 5664b801355SChanwoo Choi #define CLK_ACLK_AHB_USBLINKH0 80 5674b801355SChanwoo Choi #define CLK_ACLK_AHB_USBHS 81 5684b801355SChanwoo Choi #define CLK_ACLK_AHB_FSYSH 82 5694b801355SChanwoo Choi #define CLK_ACLK_XIU_FSYSX 83 5704b801355SChanwoo Choi #define CLK_ACLK_XIU_FSYSSX 84 5714b801355SChanwoo Choi #define CLK_ACLK_FSYSNP_200 85 5724b801355SChanwoo Choi #define CLK_ACLK_FSYSND_200 86 5734b801355SChanwoo Choi #define CLK_PCLK_PCIE_CTRL 87 5744b801355SChanwoo Choi #define CLK_PCLK_SMMU_PDMA1 88 5754b801355SChanwoo Choi #define CLK_PCLK_PCIE_PHY 89 5764b801355SChanwoo Choi #define CLK_PCLK_BTS_PCIE 90 5774b801355SChanwoo Choi #define CLK_PCLK_SMMU_PDMA0 91 5784b801355SChanwoo Choi #define CLK_PCLK_BTS_UFS 92 5794b801355SChanwoo Choi #define CLK_PCLK_BTS_USBHOST30 93 5804b801355SChanwoo Choi #define CLK_PCLK_BTS_USBDRD30 94 5814b801355SChanwoo Choi #define CLK_PCLK_GPIO_FSYS 95 5824b801355SChanwoo Choi #define CLK_PCLK_PMU_FSYS 96 5834b801355SChanwoo Choi #define CLK_PCLK_SYSREG_FSYS 97 5844b801355SChanwoo Choi #define CLK_SCLK_PCIE_100 98 5854b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99 5864b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100 5874b801355SChanwoo Choi #define CLK_PHYCLK_UFS_RX1_SYMBOL 101 5884b801355SChanwoo Choi #define CLK_PHYCLK_UFS_RX0_SYMBOL 102 5894b801355SChanwoo Choi #define CLK_PHYCLK_UFS_TX1_SYMBOL 103 5904b801355SChanwoo Choi #define CLK_PHYCLK_UFS_TX0_SYMBOL 104 5914b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105 5924b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106 5934b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107 5944b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108 5954b801355SChanwoo Choi #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109 5964b801355SChanwoo Choi #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110 5974b801355SChanwoo Choi #define CLK_SCLK_MPHY 111 5984b801355SChanwoo Choi #define CLK_SCLK_UFSUNIPRO 112 5994b801355SChanwoo Choi #define CLK_SCLK_USBHOST30 113 6004b801355SChanwoo Choi #define CLK_SCLK_USBDRD30 114 60196bd6224SChanwoo Choi 6024b801355SChanwoo Choi #define FSYS_NR_CLK 115 60396bd6224SChanwoo Choi 604a29308daSChanwoo Choi /* CMU_G2D */ 605a29308daSChanwoo Choi #define CLK_MUX_ACLK_G2D_266_USER 1 606a29308daSChanwoo Choi #define CLK_MUX_ACLK_G2D_400_USER 2 607a29308daSChanwoo Choi 608a29308daSChanwoo Choi #define CLK_DIV_PCLK_G2D 3 609a29308daSChanwoo Choi 610a29308daSChanwoo Choi #define CLK_ACLK_SMMU_MDMA1 4 611a29308daSChanwoo Choi #define CLK_ACLK_BTS_MDMA1 5 612a29308daSChanwoo Choi #define CLK_ACLK_BTS_G2D 6 613a29308daSChanwoo Choi #define CLK_ACLK_ALB_G2D 7 614a29308daSChanwoo Choi #define CLK_ACLK_AXIUS_G2DX 8 615a29308daSChanwoo Choi #define CLK_ACLK_ASYNCAXI_SYSX 9 616a29308daSChanwoo Choi #define CLK_ACLK_AHB2APB_G2D1P 10 617a29308daSChanwoo Choi #define CLK_ACLK_AHB2APB_G2D0P 11 618a29308daSChanwoo Choi #define CLK_ACLK_XIU_G2DX 12 619a29308daSChanwoo Choi #define CLK_ACLK_G2DNP_133 13 620a29308daSChanwoo Choi #define CLK_ACLK_G2DND_400 14 621a29308daSChanwoo Choi #define CLK_ACLK_MDMA1 15 622a29308daSChanwoo Choi #define CLK_ACLK_G2D 16 623a29308daSChanwoo Choi #define CLK_ACLK_SMMU_G2D 17 624a29308daSChanwoo Choi #define CLK_PCLK_SMMU_MDMA1 18 625a29308daSChanwoo Choi #define CLK_PCLK_BTS_MDMA1 19 626a29308daSChanwoo Choi #define CLK_PCLK_BTS_G2D 20 627a29308daSChanwoo Choi #define CLK_PCLK_ALB_G2D 21 628a29308daSChanwoo Choi #define CLK_PCLK_ASYNCAXI_SYSX 22 629a29308daSChanwoo Choi #define CLK_PCLK_PMU_G2D 23 630a29308daSChanwoo Choi #define CLK_PCLK_SYSREG_G2D 24 631a29308daSChanwoo Choi #define CLK_PCLK_G2D 25 632a29308daSChanwoo Choi #define CLK_PCLK_SMMU_G2D 26 633a29308daSChanwoo Choi 634a29308daSChanwoo Choi #define G2D_NR_CLK 27 635a29308daSChanwoo Choi 6362a1808a6SChanwoo Choi /* CMU_DISP */ 6372a1808a6SChanwoo Choi #define CLK_FOUT_DISP_PLL 1 6382a1808a6SChanwoo Choi 6392a1808a6SChanwoo Choi #define CLK_MOUT_DISP_PLL 2 6402a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_USER 3 6412a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_USER 4 6422a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSD_USER 5 6432a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6 6442a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_USER 7 6452a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_USER 8 6462a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9 6472a1808a6SChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_USER 10 6482a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11 6492a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12 6502a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13 6512a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14 6522a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15 6532a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16 6542a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM0 17 6552a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK 18 6562a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK 19 6572a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK 20 6582a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_B_DISP 21 6592a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_A_DISP 22 6602a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23 6612a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24 6622a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25 6632a1808a6SChanwoo Choi 6642a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DSIM1_DISP 30 6652a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31 6662a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DSIM0_DISP 32 6672a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33 6682a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_VCLK_DISP 34 6692a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_ECLK_DISP 35 6702a1808a6SChanwoo Choi #define CLK_DIV_PCLK_DISP 36 6712a1808a6SChanwoo Choi 6722a1808a6SChanwoo Choi #define CLK_ACLK_DECON_TV 40 6732a1808a6SChanwoo Choi #define CLK_ACLK_DECON 41 6742a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_TV1X 42 6752a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_TV0X 43 6762a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_DECON1X 44 6772a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_DECON0X 45 6782a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M3 46 6792a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M2 47 6802a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M1 48 6812a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M0 49 6822a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM4 50 6832a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM3 51 6842a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM2 52 6852a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM1 53 6862a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM0 54 6872a1808a6SChanwoo Choi #define CLK_ACLK_AHB2APB_DISPSFR2P 55 6882a1808a6SChanwoo Choi #define CLK_ACLK_AHB2APB_DISPSFR1P 56 6892a1808a6SChanwoo Choi #define CLK_ACLK_AHB2APB_DISPSFR0P 57 6902a1808a6SChanwoo Choi #define CLK_ACLK_AHB_DISPH 58 6912a1808a6SChanwoo Choi #define CLK_ACLK_XIU_TV1X 59 6922a1808a6SChanwoo Choi #define CLK_ACLK_XIU_TV0X 60 6932a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DECON1X 61 6942a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DECON0X 62 6952a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DISP1X 63 6962a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DISPNP_100 64 6972a1808a6SChanwoo Choi #define CLK_ACLK_DISP1ND_333 65 6982a1808a6SChanwoo Choi #define CLK_ACLK_DISP0ND_333 66 6992a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_TV1X 67 7002a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_TV0X 68 7012a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_DECON1X 69 7022a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_DECON0X 70 7032a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M3 71 7042a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M2 72 7052a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M1 73 7062a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M0 74 7072a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM4 75 7082a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM3 76 7092a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM2 77 7102a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM1 78 7112a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM0 79 7122a1808a6SChanwoo Choi #define CLK_PCLK_MIC1 80 7132a1808a6SChanwoo Choi #define CLK_PCLK_PMU_DISP 81 7142a1808a6SChanwoo Choi #define CLK_PCLK_SYSREG_DISP 82 7152a1808a6SChanwoo Choi #define CLK_PCLK_HDMIPHY 83 7162a1808a6SChanwoo Choi #define CLK_PCLK_HDMI 84 7172a1808a6SChanwoo Choi #define CLK_PCLK_MIC0 85 7182a1808a6SChanwoo Choi #define CLK_PCLK_DSIM1 86 7192a1808a6SChanwoo Choi #define CLK_PCLK_DSIM0 87 7202a1808a6SChanwoo Choi #define CLK_PCLK_DECON_TV 88 7212a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89 7222a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90 7232a1808a6SChanwoo Choi #define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91 7242a1808a6SChanwoo Choi #define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92 7252a1808a6SChanwoo Choi #define CLK_SCLK_DSIM1 93 7262a1808a6SChanwoo Choi #define CLK_SCLK_DECON_TV_VCLK 94 7272a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95 7282a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96 7292a1808a6SChanwoo Choi #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97 7302a1808a6SChanwoo Choi #define CLK_PHYCLK_HDMI_PIXEL 98 7312a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK_TO_SMIES 99 7322a1808a6SChanwoo Choi #define CLK_SCLK_FREQ_DET_DISP_PLL 100 7332a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK_TO_DSIM0 101 7342a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK_TO_MIC0 102 7352a1808a6SChanwoo Choi #define CLK_SCLK_DSD 103 7362a1808a6SChanwoo Choi #define CLK_SCLK_HDMI_SPDIF 104 7372a1808a6SChanwoo Choi #define CLK_SCLK_DSIM0 105 7382a1808a6SChanwoo Choi #define CLK_SCLK_DECON_TV_ECLK 106 7392a1808a6SChanwoo Choi #define CLK_SCLK_DECON_VCLK 107 7402a1808a6SChanwoo Choi #define CLK_SCLK_DECON_ECLK 108 7412a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK 109 7422a1808a6SChanwoo Choi #define CLK_SCLK_RGB_TV_VCLK 110 7432a1808a6SChanwoo Choi 7442a1808a6SChanwoo Choi #define DISP_NR_CLK 111 7452a1808a6SChanwoo Choi 7462e997c03SChanwoo Choi /* CMU_AUD */ 7472e997c03SChanwoo Choi #define CLK_MOUT_AUD_PLL_USER 1 7482e997c03SChanwoo Choi #define CLK_MOUT_SCLK_AUD_PCM 2 7492e997c03SChanwoo Choi #define CLK_MOUT_SCLK_AUD_I2S 3 7502e997c03SChanwoo Choi 7512e997c03SChanwoo Choi #define CLK_DIV_ATCLK_AUD 4 7522e997c03SChanwoo Choi #define CLK_DIV_PCLK_DBG_AUD 5 7532e997c03SChanwoo Choi #define CLK_DIV_ACLK_AUD 6 7542e997c03SChanwoo Choi #define CLK_DIV_AUD_CA5 7 7552e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_SLIMBUS 8 7562e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_UART 9 7572e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_PCM 10 7582e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_I2S 11 7592e997c03SChanwoo Choi 7602e997c03SChanwoo Choi #define CLK_ACLK_INTR_CTRL 12 7612e997c03SChanwoo Choi #define CLK_ACLK_AXIDS2_LPASSP 13 7622e997c03SChanwoo Choi #define CLK_ACLK_AXIDS1_LPASSP 14 7632e997c03SChanwoo Choi #define CLK_ACLK_AXI2APB1_LPASSP 15 7642e997c03SChanwoo Choi #define CLK_ACLK_AXI2APH_LPASSP 16 7652e997c03SChanwoo Choi #define CLK_ACLK_SMMU_LPASSX 17 7662e997c03SChanwoo Choi #define CLK_ACLK_AXIDS0_LPASSP 18 7672e997c03SChanwoo Choi #define CLK_ACLK_AXI2APB0_LPASSP 19 7682e997c03SChanwoo Choi #define CLK_ACLK_XIU_LPASSX 20 7692e997c03SChanwoo Choi #define CLK_ACLK_AUDNP_133 21 7702e997c03SChanwoo Choi #define CLK_ACLK_AUDND_133 22 7712e997c03SChanwoo Choi #define CLK_ACLK_SRAMC 23 7722e997c03SChanwoo Choi #define CLK_ACLK_DMAC 24 7732e997c03SChanwoo Choi #define CLK_PCLK_WDT1 25 7742e997c03SChanwoo Choi #define CLK_PCLK_WDT0 26 7752e997c03SChanwoo Choi #define CLK_PCLK_SFR1 27 7762e997c03SChanwoo Choi #define CLK_PCLK_SMMU_LPASSX 28 7772e997c03SChanwoo Choi #define CLK_PCLK_GPIO_AUD 29 7782e997c03SChanwoo Choi #define CLK_PCLK_PMU_AUD 30 7792e997c03SChanwoo Choi #define CLK_PCLK_SYSREG_AUD 31 7802e997c03SChanwoo Choi #define CLK_PCLK_AUD_SLIMBUS 32 7812e997c03SChanwoo Choi #define CLK_PCLK_AUD_UART 33 7822e997c03SChanwoo Choi #define CLK_PCLK_AUD_PCM 34 7832e997c03SChanwoo Choi #define CLK_PCLK_AUD_I2S 35 7842e997c03SChanwoo Choi #define CLK_PCLK_TIMER 36 7852e997c03SChanwoo Choi #define CLK_PCLK_SFR0_CTRL 37 7862e997c03SChanwoo Choi #define CLK_ATCLK_AUD 38 7872e997c03SChanwoo Choi #define CLK_PCLK_DBG_AUD 39 7882e997c03SChanwoo Choi #define CLK_SCLK_AUD_CA5 40 7892e997c03SChanwoo Choi #define CLK_SCLK_JTAG_TCK 41 7902e997c03SChanwoo Choi #define CLK_SCLK_SLIMBUS_CLKIN 42 7912e997c03SChanwoo Choi #define CLK_SCLK_AUD_SLIMBUS 43 7922e997c03SChanwoo Choi #define CLK_SCLK_AUD_UART 44 7932e997c03SChanwoo Choi #define CLK_SCLK_AUD_PCM 45 7942e997c03SChanwoo Choi #define CLK_SCLK_I2S_BCLK 46 7952e997c03SChanwoo Choi #define CLK_SCLK_AUD_I2S 47 7962e997c03SChanwoo Choi 7972e997c03SChanwoo Choi #define AUD_NR_CLK 48 7982e997c03SChanwoo Choi 7995785d6e6SChanwoo Choi /* CMU_BUS{0|1|2} */ 8005785d6e6SChanwoo Choi #define CLK_DIV_PCLK_BUS_133 1 8015785d6e6SChanwoo Choi 8025785d6e6SChanwoo Choi #define CLK_ACLK_AHB2APB_BUSP 2 8035785d6e6SChanwoo Choi #define CLK_ACLK_BUSNP_133 3 8045785d6e6SChanwoo Choi #define CLK_ACLK_BUSND_400 4 8055785d6e6SChanwoo Choi #define CLK_PCLK_BUSSRVND_133 5 8065785d6e6SChanwoo Choi #define CLK_PCLK_PMU_BUS 6 8075785d6e6SChanwoo Choi #define CLK_PCLK_SYSREG_BUS 7 8085785d6e6SChanwoo Choi 8095785d6e6SChanwoo Choi #define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */ 8105785d6e6SChanwoo Choi #define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ 8115785d6e6SChanwoo Choi #define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ 8125785d6e6SChanwoo Choi 8135785d6e6SChanwoo Choi #define BUSx_NR_CLK 11 8145785d6e6SChanwoo Choi 815453e519eSChanwoo Choi /* CMU_G3D */ 816453e519eSChanwoo Choi #define CLK_FOUT_G3D_PLL 1 817453e519eSChanwoo Choi 818453e519eSChanwoo Choi #define CLK_MOUT_ACLK_G3D_400 2 819453e519eSChanwoo Choi #define CLK_MOUT_G3D_PLL 3 820453e519eSChanwoo Choi 821453e519eSChanwoo Choi #define CLK_DIV_SCLK_HPM_G3D 4 822453e519eSChanwoo Choi #define CLK_DIV_PCLK_G3D 5 823453e519eSChanwoo Choi #define CLK_DIV_ACLK_G3D 6 824453e519eSChanwoo Choi #define CLK_ACLK_BTS_G3D1 7 825453e519eSChanwoo Choi #define CLK_ACLK_BTS_G3D0 8 826453e519eSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_G3D 9 827453e519eSChanwoo Choi #define CLK_ACLK_ASYNCAPBM_G3D 10 828453e519eSChanwoo Choi #define CLK_ACLK_AHB2APB_G3DP 11 829453e519eSChanwoo Choi #define CLK_ACLK_G3DNP_150 12 830453e519eSChanwoo Choi #define CLK_ACLK_G3DND_600 13 831453e519eSChanwoo Choi #define CLK_ACLK_G3D 14 832453e519eSChanwoo Choi #define CLK_PCLK_BTS_G3D1 15 833453e519eSChanwoo Choi #define CLK_PCLK_BTS_G3D0 16 834453e519eSChanwoo Choi #define CLK_PCLK_PMU_G3D 17 835453e519eSChanwoo Choi #define CLK_PCLK_SYSREG_G3D 18 836453e519eSChanwoo Choi #define CLK_SCLK_HPM_G3D 19 837453e519eSChanwoo Choi 838453e519eSChanwoo Choi #define G3D_NR_CLK 20 839453e519eSChanwoo Choi 8402a2f33e8SChanwoo Choi /* CMU_GSCL */ 8412a2f33e8SChanwoo Choi #define CLK_MOUT_ACLK_GSCL_111_USER 1 8422a2f33e8SChanwoo Choi #define CLK_MOUT_ACLK_GSCL_333_USER 2 8432a2f33e8SChanwoo Choi 8442a2f33e8SChanwoo Choi #define CLK_ACLK_BTS_GSCL2 3 8452a2f33e8SChanwoo Choi #define CLK_ACLK_BTS_GSCL1 4 8462a2f33e8SChanwoo Choi #define CLK_ACLK_BTS_GSCL0 5 8472a2f33e8SChanwoo Choi #define CLK_ACLK_AHB2APB_GSCLP 6 8482a2f33e8SChanwoo Choi #define CLK_ACLK_XIU_GSCLX 7 8492a2f33e8SChanwoo Choi #define CLK_ACLK_GSCLNP_111 8 8502a2f33e8SChanwoo Choi #define CLK_ACLK_GSCLRTND_333 9 8512a2f33e8SChanwoo Choi #define CLK_ACLK_GSCLBEND_333 10 8522a2f33e8SChanwoo Choi #define CLK_ACLK_GSD 11 8532a2f33e8SChanwoo Choi #define CLK_ACLK_GSCL2 12 8542a2f33e8SChanwoo Choi #define CLK_ACLK_GSCL1 13 8552a2f33e8SChanwoo Choi #define CLK_ACLK_GSCL0 14 8562a2f33e8SChanwoo Choi #define CLK_ACLK_SMMU_GSCL0 15 8572a2f33e8SChanwoo Choi #define CLK_ACLK_SMMU_GSCL1 16 8582a2f33e8SChanwoo Choi #define CLK_ACLK_SMMU_GSCL2 17 8592a2f33e8SChanwoo Choi #define CLK_PCLK_BTS_GSCL2 18 8602a2f33e8SChanwoo Choi #define CLK_PCLK_BTS_GSCL1 19 8612a2f33e8SChanwoo Choi #define CLK_PCLK_BTS_GSCL0 20 8622a2f33e8SChanwoo Choi #define CLK_PCLK_PMU_GSCL 21 8632a2f33e8SChanwoo Choi #define CLK_PCLK_SYSREG_GSCL 22 8642a2f33e8SChanwoo Choi #define CLK_PCLK_GSCL2 23 8652a2f33e8SChanwoo Choi #define CLK_PCLK_GSCL1 24 8662a2f33e8SChanwoo Choi #define CLK_PCLK_GSCL0 25 8672a2f33e8SChanwoo Choi #define CLK_PCLK_SMMU_GSCL0 26 8682a2f33e8SChanwoo Choi #define CLK_PCLK_SMMU_GSCL1 27 8692a2f33e8SChanwoo Choi #define CLK_PCLK_SMMU_GSCL2 28 8702a2f33e8SChanwoo Choi 8712a2f33e8SChanwoo Choi #define GSCL_NR_CLK 29 8722a2f33e8SChanwoo Choi 873df40a13cSChanwoo Choi /* CMU_APOLLO */ 874df40a13cSChanwoo Choi #define CLK_FOUT_APOLLO_PLL 1 875df40a13cSChanwoo Choi 876df40a13cSChanwoo Choi #define CLK_MOUT_APOLLO_PLL 2 877df40a13cSChanwoo Choi #define CLK_MOUT_BUS_PLL_APOLLO_USER 3 878df40a13cSChanwoo Choi #define CLK_MOUT_APOLLO 4 879df40a13cSChanwoo Choi 880df40a13cSChanwoo Choi #define CLK_DIV_CNTCLK_APOLLO 5 881df40a13cSChanwoo Choi #define CLK_DIV_PCLK_DBG_APOLLO 6 882df40a13cSChanwoo Choi #define CLK_DIV_ATCLK_APOLLO 7 883df40a13cSChanwoo Choi #define CLK_DIV_PCLK_APOLLO 8 884df40a13cSChanwoo Choi #define CLK_DIV_ACLK_APOLLO 9 885df40a13cSChanwoo Choi #define CLK_DIV_APOLLO2 10 886df40a13cSChanwoo Choi #define CLK_DIV_APOLLO1 11 887df40a13cSChanwoo Choi #define CLK_DIV_SCLK_HPM_APOLLO 12 888df40a13cSChanwoo Choi #define CLK_DIV_APOLLO_PLL 13 889df40a13cSChanwoo Choi 890df40a13cSChanwoo Choi #define CLK_ACLK_ATBDS_APOLLO_3 14 891df40a13cSChanwoo Choi #define CLK_ACLK_ATBDS_APOLLO_2 15 892df40a13cSChanwoo Choi #define CLK_ACLK_ATBDS_APOLLO_1 16 893df40a13cSChanwoo Choi #define CLK_ACLK_ATBDS_APOLLO_0 17 894df40a13cSChanwoo Choi #define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18 895df40a13cSChanwoo Choi #define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19 896df40a13cSChanwoo Choi #define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20 897df40a13cSChanwoo Choi #define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21 898df40a13cSChanwoo Choi #define CLK_ACLK_ASYNCACES_APOLLO_CCI 22 899df40a13cSChanwoo Choi #define CLK_ACLK_AHB2APB_APOLLOP 23 900df40a13cSChanwoo Choi #define CLK_ACLK_APOLLONP_200 24 901df40a13cSChanwoo Choi #define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25 902df40a13cSChanwoo Choi #define CLK_PCLK_PMU_APOLLO 26 903df40a13cSChanwoo Choi #define CLK_PCLK_SYSREG_APOLLO 27 904df40a13cSChanwoo Choi #define CLK_CNTCLK_APOLLO 28 905df40a13cSChanwoo Choi #define CLK_SCLK_HPM_APOLLO 29 906df40a13cSChanwoo Choi #define CLK_SCLK_APOLLO 30 907df40a13cSChanwoo Choi 908df40a13cSChanwoo Choi #define APOLLO_NR_CLK 31 909df40a13cSChanwoo Choi 9106c5d76d1SChanwoo Choi /* CMU_ATLAS */ 9116c5d76d1SChanwoo Choi #define CLK_FOUT_ATLAS_PLL 1 9126c5d76d1SChanwoo Choi 9136c5d76d1SChanwoo Choi #define CLK_MOUT_ATLAS_PLL 2 9146c5d76d1SChanwoo Choi #define CLK_MOUT_BUS_PLL_ATLAS_USER 3 9156c5d76d1SChanwoo Choi #define CLK_MOUT_ATLAS 4 9166c5d76d1SChanwoo Choi 9176c5d76d1SChanwoo Choi #define CLK_DIV_CNTCLK_ATLAS 5 9186c5d76d1SChanwoo Choi #define CLK_DIV_PCLK_DBG_ATLAS 6 9196c5d76d1SChanwoo Choi #define CLK_DIV_ATCLK_ATLASO 7 9206c5d76d1SChanwoo Choi #define CLK_DIV_PCLK_ATLAS 8 9216c5d76d1SChanwoo Choi #define CLK_DIV_ACLK_ATLAS 9 9226c5d76d1SChanwoo Choi #define CLK_DIV_ATLAS2 10 9236c5d76d1SChanwoo Choi #define CLK_DIV_ATLAS1 11 9246c5d76d1SChanwoo Choi #define CLK_DIV_SCLK_HPM_ATLAS 12 9256c5d76d1SChanwoo Choi #define CLK_DIV_ATLAS_PLL 13 9266c5d76d1SChanwoo Choi 9276c5d76d1SChanwoo Choi #define CLK_ACLK_ATB_AUD_CSSYS 14 9286c5d76d1SChanwoo Choi #define CLK_ACLK_ATB_APOLLO3_CSSYS 15 9296c5d76d1SChanwoo Choi #define CLK_ACLK_ATB_APOLLO2_CSSYS 16 9306c5d76d1SChanwoo Choi #define CLK_ACLK_ATB_APOLLO1_CSSYS 17 9316c5d76d1SChanwoo Choi #define CLK_ACLK_ATB_APOLLO0_CSSYS 18 9326c5d76d1SChanwoo Choi #define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19 9336c5d76d1SChanwoo Choi #define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20 9346c5d76d1SChanwoo Choi #define CLK_ACLK_ASYNCACES_ATLAS_CCI 21 9356c5d76d1SChanwoo Choi #define CLK_ACLK_AHB2APB_ATLASP 22 9366c5d76d1SChanwoo Choi #define CLK_ACLK_ATLASNP_200 23 9376c5d76d1SChanwoo Choi #define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24 9386c5d76d1SChanwoo Choi #define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25 9396c5d76d1SChanwoo Choi #define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26 9406c5d76d1SChanwoo Choi #define CLK_PCLK_PMU_ATLAS 27 9416c5d76d1SChanwoo Choi #define CLK_PCLK_SYSREG_ATLAS 28 9426c5d76d1SChanwoo Choi #define CLK_PCLK_SECJTAG 29 9436c5d76d1SChanwoo Choi #define CLK_CNTCLK_ATLAS 30 9446c5d76d1SChanwoo Choi #define CLK_SCLK_FREQ_DET_ATLAS_PLL 31 9456c5d76d1SChanwoo Choi #define CLK_SCLK_HPM_ATLAS 32 9466c5d76d1SChanwoo Choi #define CLK_TRACECLK 33 9476c5d76d1SChanwoo Choi #define CLK_CTMCLK 34 9486c5d76d1SChanwoo Choi #define CLK_HCLK_CSSYS 35 9496c5d76d1SChanwoo Choi #define CLK_PCLK_DBG_CSSYS 36 9506c5d76d1SChanwoo Choi #define CLK_PCLK_DBG 37 9516c5d76d1SChanwoo Choi #define CLK_ATCLK 38 9526c5d76d1SChanwoo Choi #define CLK_SCLK_ATLAS 39 9536c5d76d1SChanwoo Choi 9546c5d76d1SChanwoo Choi #define ATLAS_NR_CLK 40 9556c5d76d1SChanwoo Choi 956b274bbfdSChanwoo Choi /* CMU_MSCL */ 957b274bbfdSChanwoo Choi #define CLK_MOUT_SCLK_JPEG_USER 1 958b274bbfdSChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_USER 2 959b274bbfdSChanwoo Choi #define CLK_MOUT_SCLK_JPEG 3 960b274bbfdSChanwoo Choi 961b274bbfdSChanwoo Choi #define CLK_DIV_PCLK_MSCL 4 962b274bbfdSChanwoo Choi 963b274bbfdSChanwoo Choi #define CLK_ACLK_BTS_JPEG 5 964b274bbfdSChanwoo Choi #define CLK_ACLK_BTS_M2MSCALER1 6 965b274bbfdSChanwoo Choi #define CLK_ACLK_BTS_M2MSCALER0 7 966b274bbfdSChanwoo Choi #define CLK_ACLK_AHB2APB_MSCL0P 8 967b274bbfdSChanwoo Choi #define CLK_ACLK_XIU_MSCLX 9 968b274bbfdSChanwoo Choi #define CLK_ACLK_MSCLNP_100 10 969b274bbfdSChanwoo Choi #define CLK_ACLK_MSCLND_400 11 970b274bbfdSChanwoo Choi #define CLK_ACLK_JPEG 12 971b274bbfdSChanwoo Choi #define CLK_ACLK_M2MSCALER1 13 972b274bbfdSChanwoo Choi #define CLK_ACLK_M2MSCALER0 14 973b274bbfdSChanwoo Choi #define CLK_ACLK_SMMU_M2MSCALER0 15 974b274bbfdSChanwoo Choi #define CLK_ACLK_SMMU_M2MSCALER1 16 975b274bbfdSChanwoo Choi #define CLK_ACLK_SMMU_JPEG 17 976b274bbfdSChanwoo Choi #define CLK_PCLK_BTS_JPEG 18 977b274bbfdSChanwoo Choi #define CLK_PCLK_BTS_M2MSCALER1 19 978b274bbfdSChanwoo Choi #define CLK_PCLK_BTS_M2MSCALER0 20 979b274bbfdSChanwoo Choi #define CLK_PCLK_PMU_MSCL 21 980b274bbfdSChanwoo Choi #define CLK_PCLK_SYSREG_MSCL 22 981b274bbfdSChanwoo Choi #define CLK_PCLK_JPEG 23 982b274bbfdSChanwoo Choi #define CLK_PCLK_M2MSCALER1 24 983b274bbfdSChanwoo Choi #define CLK_PCLK_M2MSCALER0 25 984b274bbfdSChanwoo Choi #define CLK_PCLK_SMMU_M2MSCALER0 26 985b274bbfdSChanwoo Choi #define CLK_PCLK_SMMU_M2MSCALER1 27 986b274bbfdSChanwoo Choi #define CLK_PCLK_SMMU_JPEG 28 987b274bbfdSChanwoo Choi #define CLK_SCLK_JPEG 29 988b274bbfdSChanwoo Choi 989b274bbfdSChanwoo Choi #define MSCL_NR_CLK 30 990b274bbfdSChanwoo Choi 9919910b6bbSChanwoo Choi /* CMU_MFC */ 9929910b6bbSChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_USER 1 9939910b6bbSChanwoo Choi 9949910b6bbSChanwoo Choi #define CLK_DIV_PCLK_MFC 2 9959910b6bbSChanwoo Choi 9969910b6bbSChanwoo Choi #define CLK_ACLK_BTS_MFC_1 3 9979910b6bbSChanwoo Choi #define CLK_ACLK_BTS_MFC_0 4 9989910b6bbSChanwoo Choi #define CLK_ACLK_AHB2APB_MFCP 5 9999910b6bbSChanwoo Choi #define CLK_ACLK_XIU_MFCX 6 10009910b6bbSChanwoo Choi #define CLK_ACLK_MFCNP_100 7 10019910b6bbSChanwoo Choi #define CLK_ACLK_MFCND_400 8 10029910b6bbSChanwoo Choi #define CLK_ACLK_MFC 9 10039910b6bbSChanwoo Choi #define CLK_ACLK_SMMU_MFC_1 10 10049910b6bbSChanwoo Choi #define CLK_ACLK_SMMU_MFC_0 11 10059910b6bbSChanwoo Choi #define CLK_PCLK_BTS_MFC_1 12 10069910b6bbSChanwoo Choi #define CLK_PCLK_BTS_MFC_0 13 10079910b6bbSChanwoo Choi #define CLK_PCLK_PMU_MFC 14 10089910b6bbSChanwoo Choi #define CLK_PCLK_SYSREG_MFC 15 10099910b6bbSChanwoo Choi #define CLK_PCLK_MFC 16 10109910b6bbSChanwoo Choi #define CLK_PCLK_SMMU_MFC_1 17 10119910b6bbSChanwoo Choi #define CLK_PCLK_SMMU_MFC_0 18 10129910b6bbSChanwoo Choi 10139910b6bbSChanwoo Choi #define MFC_NR_CLK 19 10149910b6bbSChanwoo Choi 101545e58aa5SChanwoo Choi /* CMU_HEVC */ 101645e58aa5SChanwoo Choi #define CLK_MOUT_ACLK_HEVC_400_USER 1 101745e58aa5SChanwoo Choi 101845e58aa5SChanwoo Choi #define CLK_DIV_PCLK_HEVC 2 101945e58aa5SChanwoo Choi 102045e58aa5SChanwoo Choi #define CLK_ACLK_BTS_HEVC_1 3 102145e58aa5SChanwoo Choi #define CLK_ACLK_BTS_HEVC_0 4 102245e58aa5SChanwoo Choi #define CLK_ACLK_AHB2APB_HEVCP 5 102345e58aa5SChanwoo Choi #define CLK_ACLK_XIU_HEVCX 6 102445e58aa5SChanwoo Choi #define CLK_ACLK_HEVCNP_100 7 102545e58aa5SChanwoo Choi #define CLK_ACLK_HEVCND_400 8 102645e58aa5SChanwoo Choi #define CLK_ACLK_HEVC 9 102745e58aa5SChanwoo Choi #define CLK_ACLK_SMMU_HEVC_1 10 102845e58aa5SChanwoo Choi #define CLK_ACLK_SMMU_HEVC_0 11 102945e58aa5SChanwoo Choi #define CLK_PCLK_BTS_HEVC_1 12 103045e58aa5SChanwoo Choi #define CLK_PCLK_BTS_HEVC_0 13 103145e58aa5SChanwoo Choi #define CLK_PCLK_PMU_HEVC 14 103245e58aa5SChanwoo Choi #define CLK_PCLK_SYSREG_HEVC 15 103345e58aa5SChanwoo Choi #define CLK_PCLK_HEVC 16 103445e58aa5SChanwoo Choi #define CLK_PCLK_SMMU_HEVC_1 17 103545e58aa5SChanwoo Choi #define CLK_PCLK_SMMU_HEVC_0 18 103645e58aa5SChanwoo Choi 103745e58aa5SChanwoo Choi #define HEVC_NR_CLK 19 103845e58aa5SChanwoo Choi 10398e46c4b8SChanwoo Choi /* CMU_ISP */ 10408e46c4b8SChanwoo Choi #define CLK_MOUT_ACLK_ISP_DIS_400_USER 1 10418e46c4b8SChanwoo Choi #define CLK_MOUT_ACLK_ISP_400_USER 2 10428e46c4b8SChanwoo Choi 10438e46c4b8SChanwoo Choi #define CLK_DIV_PCLK_ISP_DIS 3 10448e46c4b8SChanwoo Choi #define CLK_DIV_PCLK_ISP 4 10458e46c4b8SChanwoo Choi #define CLK_DIV_ACLK_ISP_D_200 5 10468e46c4b8SChanwoo Choi #define CLK_DIV_ACLK_ISP_C_200 6 10478e46c4b8SChanwoo Choi 10488e46c4b8SChanwoo Choi #define CLK_ACLK_ISP_D_GLUE 7 10498e46c4b8SChanwoo Choi #define CLK_ACLK_SCALERP 8 10508e46c4b8SChanwoo Choi #define CLK_ACLK_3DNR 9 10518e46c4b8SChanwoo Choi #define CLK_ACLK_DIS 10 10528e46c4b8SChanwoo Choi #define CLK_ACLK_SCALERC 11 10538e46c4b8SChanwoo Choi #define CLK_ACLK_DRC 12 10548e46c4b8SChanwoo Choi #define CLK_ACLK_ISP 13 10558e46c4b8SChanwoo Choi #define CLK_ACLK_AXIUS_SCALERP 14 10568e46c4b8SChanwoo Choi #define CLK_ACLK_AXIUS_SCALERC 15 10578e46c4b8SChanwoo Choi #define CLK_ACLK_AXIUS_DRC 16 10588e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAHBM_ISP2P 17 10598e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAHBM_ISP1P 18 10608e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DIS1 19 10618e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DIS0 20 10628e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DIS1 21 10638e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DIS0 22 10648e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ISP2P 23 10658e46c4b8SChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ISP1P 24 10668e46c4b8SChanwoo Choi #define CLK_ACLK_AHB2APB_ISP2P 25 10678e46c4b8SChanwoo Choi #define CLK_ACLK_AHB2APB_ISP1P 26 10688e46c4b8SChanwoo Choi #define CLK_ACLK_AXI2APB_ISP2P 27 10698e46c4b8SChanwoo Choi #define CLK_ACLK_AXI2APB_ISP1P 28 10708e46c4b8SChanwoo Choi #define CLK_ACLK_XIU_ISPEX1 29 10718e46c4b8SChanwoo Choi #define CLK_ACLK_XIU_ISPEX0 30 10728e46c4b8SChanwoo Choi #define CLK_ACLK_ISPND_400 31 10738e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_SCALERP 32 10748e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_3DNR 33 10758e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_DIS1 34 10768e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_DIS0 35 10778e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_SCALERC 36 10788e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_DRC 37 10798e46c4b8SChanwoo Choi #define CLK_ACLK_SMMU_ISP 38 10808e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_SCALERP 39 10818e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_3DR 40 10828e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_DIS1 41 10838e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_DIS0 42 10848e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_SCALERC 43 10858e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_DRC 44 10868e46c4b8SChanwoo Choi #define CLK_ACLK_BTS_ISP 45 10878e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_SCALERP 46 10888e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_3DNR 47 10898e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_DIS1 48 10908e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_DIS0 49 10918e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_SCALERC 50 10928e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_DRC 51 10938e46c4b8SChanwoo Choi #define CLK_PCLK_SMMU_ISP 52 10948e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_SCALERP 53 10958e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_3DNR 54 10968e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_DIS1 55 10978e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_DIS0 56 10988e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_SCALERC 57 10998e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_DRC 58 11008e46c4b8SChanwoo Choi #define CLK_PCLK_BTS_ISP 59 11018e46c4b8SChanwoo Choi #define CLK_PCLK_ASYNCAXI_DIS1 60 11028e46c4b8SChanwoo Choi #define CLK_PCLK_ASYNCAXI_DIS0 61 11038e46c4b8SChanwoo Choi #define CLK_PCLK_PMU_ISP 62 11048e46c4b8SChanwoo Choi #define CLK_PCLK_SYSREG_ISP 63 11058e46c4b8SChanwoo Choi #define CLK_PCLK_CMU_ISP_LOCAL 64 11068e46c4b8SChanwoo Choi #define CLK_PCLK_SCALERP 65 11078e46c4b8SChanwoo Choi #define CLK_PCLK_3DNR 66 11088e46c4b8SChanwoo Choi #define CLK_PCLK_DIS_CORE 67 11098e46c4b8SChanwoo Choi #define CLK_PCLK_DIS 68 11108e46c4b8SChanwoo Choi #define CLK_PCLK_SCALERC 69 11118e46c4b8SChanwoo Choi #define CLK_PCLK_DRC 70 11128e46c4b8SChanwoo Choi #define CLK_PCLK_ISP 71 11138e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCS_DIS 72 11148e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCM_DIS 73 11158e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCS_SCALERP 74 11168e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCM_ISPD 75 11178e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCS_ISPC 76 11188e46c4b8SChanwoo Choi #define CLK_SCLK_PIXELASYNCM_ISPC 77 11198e46c4b8SChanwoo Choi 11208e46c4b8SChanwoo Choi #define ISP_NR_CLK 78 11218e46c4b8SChanwoo Choi 11226958f22fSChanwoo Choi /* CMU_CAM0 */ 11236958f22fSChanwoo Choi #define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1 11246958f22fSChanwoo Choi #define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2 11256958f22fSChanwoo Choi 11266958f22fSChanwoo Choi #define CLK_MOUT_ACLK_CAM0_333_USER 3 11276958f22fSChanwoo Choi #define CLK_MOUT_ACLK_CAM0_400_USER 4 11286958f22fSChanwoo Choi #define CLK_MOUT_ACLK_CAM0_552_USER 5 11296958f22fSChanwoo Choi #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER 6 11306958f22fSChanwoo Choi #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER 7 11316958f22fSChanwoo Choi #define CLK_MOUT_ACLK_LITE_D_B 8 11326958f22fSChanwoo Choi #define CLK_MOUT_ACLK_LITE_D_A 9 11336958f22fSChanwoo Choi #define CLK_MOUT_ACLK_LITE_B_B 10 11346958f22fSChanwoo Choi #define CLK_MOUT_ACLK_LITE_B_A 11 11356958f22fSChanwoo Choi #define CLK_MOUT_ACLK_LITE_A_B 12 11366958f22fSChanwoo Choi #define CLK_MOUT_ACLK_LITE_A_A 13 11376958f22fSChanwoo Choi #define CLK_MOUT_ACLK_CAM0_400 14 11386958f22fSChanwoo Choi #define CLK_MOUT_ACLK_CSIS1_B 15 11396958f22fSChanwoo Choi #define CLK_MOUT_ACLK_CSIS1_A 16 11406958f22fSChanwoo Choi #define CLK_MOUT_ACLK_CSIS0_B 17 11416958f22fSChanwoo Choi #define CLK_MOUT_ACLK_CSIS0_A 18 11426958f22fSChanwoo Choi #define CLK_MOUT_ACLK_3AA1_B 19 11436958f22fSChanwoo Choi #define CLK_MOUT_ACLK_3AA1_A 20 11446958f22fSChanwoo Choi #define CLK_MOUT_ACLK_3AA0_B 21 11456958f22fSChanwoo Choi #define CLK_MOUT_ACLK_3AA0_A 22 11466958f22fSChanwoo Choi #define CLK_MOUT_SCLK_LITE_FREECNT_C 23 11476958f22fSChanwoo Choi #define CLK_MOUT_SCLK_LITE_FREECNT_B 24 11486958f22fSChanwoo Choi #define CLK_MOUT_SCLK_LITE_FREECNT_A 25 11496958f22fSChanwoo Choi #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B 26 11506958f22fSChanwoo Choi #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A 27 11516958f22fSChanwoo Choi #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B 28 11526958f22fSChanwoo Choi #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A 29 11536958f22fSChanwoo Choi 11546958f22fSChanwoo Choi #define CLK_DIV_PCLK_CAM0_50 30 11556958f22fSChanwoo Choi #define CLK_DIV_ACLK_CAM0_200 31 11566958f22fSChanwoo Choi #define CLK_DIV_ACLK_CAM0_BUS_400 32 11576958f22fSChanwoo Choi #define CLK_DIV_PCLK_LITE_D 33 11586958f22fSChanwoo Choi #define CLK_DIV_ACLK_LITE_D 34 11596958f22fSChanwoo Choi #define CLK_DIV_PCLK_LITE_B 35 11606958f22fSChanwoo Choi #define CLK_DIV_ACLK_LITE_B 36 11616958f22fSChanwoo Choi #define CLK_DIV_PCLK_LITE_A 37 11626958f22fSChanwoo Choi #define CLK_DIV_ACLK_LITE_A 38 11636958f22fSChanwoo Choi #define CLK_DIV_ACLK_CSIS1 39 11646958f22fSChanwoo Choi #define CLK_DIV_ACLK_CSIS0 40 11656958f22fSChanwoo Choi #define CLK_DIV_PCLK_3AA1 41 11666958f22fSChanwoo Choi #define CLK_DIV_ACLK_3AA1 42 11676958f22fSChanwoo Choi #define CLK_DIV_PCLK_3AA0 43 11686958f22fSChanwoo Choi #define CLK_DIV_ACLK_3AA0 44 11696958f22fSChanwoo Choi #define CLK_DIV_SCLK_PIXELASYNC_LITE_C 45 11706958f22fSChanwoo Choi #define CLK_DIV_PCLK_PIXELASYNC_LITE_C 46 11716958f22fSChanwoo Choi #define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT 47 11726958f22fSChanwoo Choi 11736958f22fSChanwoo Choi #define CLK_ACLK_CSIS1 50 11746958f22fSChanwoo Choi #define CLK_ACLK_CSIS0 51 11756958f22fSChanwoo Choi #define CLK_ACLK_3AA1 52 11766958f22fSChanwoo Choi #define CLK_ACLK_3AA0 53 11776958f22fSChanwoo Choi #define CLK_ACLK_LITE_D 54 11786958f22fSChanwoo Choi #define CLK_ACLK_LITE_B 55 11796958f22fSChanwoo Choi #define CLK_ACLK_LITE_A 56 11806958f22fSChanwoo Choi #define CLK_ACLK_AHBSYNCDN 57 11816958f22fSChanwoo Choi #define CLK_ACLK_AXIUS_LITE_D 58 11826958f22fSChanwoo Choi #define CLK_ACLK_AXIUS_LITE_B 59 11836958f22fSChanwoo Choi #define CLK_ACLK_AXIUS_LITE_A 60 11846958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBM_3AA1 61 11856958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_3AA1 62 11866958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBM_3AA0 63 11876958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_3AA0 64 11886958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBM_LITE_D 65 11896958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_LITE_D 66 11906958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBM_LITE_B 67 11916958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_LITE_B 68 11926958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBM_LITE_A 69 11936958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_LITE_A 70 11946958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ISP0P 71 11956958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_3AA1 72 11966958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_3AA1 73 11976958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_3AA0 74 11986958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_3AA0 75 11996958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_LITE_D 76 12006958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_LITE_D 77 12016958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_LITE_B 78 12026958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_LITE_B 79 12036958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_LITE_A 80 12046958f22fSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_LITE_A 81 12056958f22fSChanwoo Choi #define CLK_ACLK_AHB2APB_ISPSFRP 82 12066958f22fSChanwoo Choi #define CLK_ACLK_AXI2APB_ISP0P 83 12076958f22fSChanwoo Choi #define CLK_ACLK_AXI2AHB_ISP0P 84 12086958f22fSChanwoo Choi #define CLK_ACLK_XIU_IS0X 85 12096958f22fSChanwoo Choi #define CLK_ACLK_XIU_ISP0EX 86 12106958f22fSChanwoo Choi #define CLK_ACLK_CAM0NP_276 87 12116958f22fSChanwoo Choi #define CLK_ACLK_CAM0ND_400 88 12126958f22fSChanwoo Choi #define CLK_ACLK_SMMU_3AA1 89 12136958f22fSChanwoo Choi #define CLK_ACLK_SMMU_3AA0 90 12146958f22fSChanwoo Choi #define CLK_ACLK_SMMU_LITE_D 91 12156958f22fSChanwoo Choi #define CLK_ACLK_SMMU_LITE_B 92 12166958f22fSChanwoo Choi #define CLK_ACLK_SMMU_LITE_A 93 12176958f22fSChanwoo Choi #define CLK_ACLK_BTS_3AA1 94 12186958f22fSChanwoo Choi #define CLK_ACLK_BTS_3AA0 95 12196958f22fSChanwoo Choi #define CLK_ACLK_BTS_LITE_D 96 12206958f22fSChanwoo Choi #define CLK_ACLK_BTS_LITE_B 97 12216958f22fSChanwoo Choi #define CLK_ACLK_BTS_LITE_A 98 12226958f22fSChanwoo Choi #define CLK_PCLK_SMMU_3AA1 99 12236958f22fSChanwoo Choi #define CLK_PCLK_SMMU_3AA0 100 12246958f22fSChanwoo Choi #define CLK_PCLK_SMMU_LITE_D 101 12256958f22fSChanwoo Choi #define CLK_PCLK_SMMU_LITE_B 102 12266958f22fSChanwoo Choi #define CLK_PCLK_SMMU_LITE_A 103 12276958f22fSChanwoo Choi #define CLK_PCLK_BTS_3AA1 104 12286958f22fSChanwoo Choi #define CLK_PCLK_BTS_3AA0 105 12296958f22fSChanwoo Choi #define CLK_PCLK_BTS_LITE_D 106 12306958f22fSChanwoo Choi #define CLK_PCLK_BTS_LITE_B 107 12316958f22fSChanwoo Choi #define CLK_PCLK_BTS_LITE_A 108 12326958f22fSChanwoo Choi #define CLK_PCLK_ASYNCAXI_CAM1 109 12336958f22fSChanwoo Choi #define CLK_PCLK_ASYNCAXI_3AA1 110 12346958f22fSChanwoo Choi #define CLK_PCLK_ASYNCAXI_3AA0 111 12356958f22fSChanwoo Choi #define CLK_PCLK_ASYNCAXI_LITE_D 112 12366958f22fSChanwoo Choi #define CLK_PCLK_ASYNCAXI_LITE_B 113 12376958f22fSChanwoo Choi #define CLK_PCLK_ASYNCAXI_LITE_A 114 12386958f22fSChanwoo Choi #define CLK_PCLK_PMU_CAM0 115 12396958f22fSChanwoo Choi #define CLK_PCLK_SYSREG_CAM0 116 12406958f22fSChanwoo Choi #define CLK_PCLK_CMU_CAM0_LOCAL 117 12416958f22fSChanwoo Choi #define CLK_PCLK_CSIS1 118 12426958f22fSChanwoo Choi #define CLK_PCLK_CSIS0 119 12436958f22fSChanwoo Choi #define CLK_PCLK_3AA1 120 12446958f22fSChanwoo Choi #define CLK_PCLK_3AA0 121 12456958f22fSChanwoo Choi #define CLK_PCLK_LITE_D 122 12466958f22fSChanwoo Choi #define CLK_PCLK_LITE_B 123 12476958f22fSChanwoo Choi #define CLK_PCLK_LITE_A 124 12486958f22fSChanwoo Choi #define CLK_PHYCLK_RXBYTECLKHS0_S4 125 12496958f22fSChanwoo Choi #define CLK_PHYCLK_RXBYTECLKHS0_S2A 126 12506958f22fSChanwoo Choi #define CLK_SCLK_LITE_FREECNT 127 12516958f22fSChanwoo Choi #define CLK_SCLK_PIXELASYNCM_3AA1 128 12526958f22fSChanwoo Choi #define CLK_SCLK_PIXELASYNCM_3AA0 129 12536958f22fSChanwoo Choi #define CLK_SCLK_PIXELASYNCS_3AA0 130 12546958f22fSChanwoo Choi #define CLK_SCLK_PIXELASYNCM_LITE_C 131 12556958f22fSChanwoo Choi #define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132 12566958f22fSChanwoo Choi #define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133 12576958f22fSChanwoo Choi 12586958f22fSChanwoo Choi #define CAM0_NR_CLK 134 12596958f22fSChanwoo Choi 126096bd6224SChanwoo Choi #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 1261