196bd6224SChanwoo Choi /* 296bd6224SChanwoo Choi * Copyright (c) 2014 Samsung Electronics Co., Ltd. 396bd6224SChanwoo Choi * Author: Chanwoo Choi <cw00.choi@samsung.com> 496bd6224SChanwoo Choi * 596bd6224SChanwoo Choi * This program is free software; you can redistribute it and/or modify 696bd6224SChanwoo Choi * it under the terms of the GNU General Public License version 2 as 796bd6224SChanwoo Choi * published by the Free Software Foundation. 896bd6224SChanwoo Choi */ 996bd6224SChanwoo Choi 1096bd6224SChanwoo Choi #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 1196bd6224SChanwoo Choi #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 1296bd6224SChanwoo Choi 1396bd6224SChanwoo Choi /* CMU_TOP */ 1496bd6224SChanwoo Choi #define CLK_FOUT_ISP_PLL 1 1596bd6224SChanwoo Choi #define CLK_FOUT_AUD_PLL 2 1696bd6224SChanwoo Choi 1796bd6224SChanwoo Choi #define CLK_MOUT_AUD_PLL 10 1896bd6224SChanwoo Choi #define CLK_MOUT_ISP_PLL 11 1996bd6224SChanwoo Choi #define CLK_MOUT_AUD_PLL_USER_T 12 2096bd6224SChanwoo Choi #define CLK_MOUT_MPHY_PLL_USER 13 2196bd6224SChanwoo Choi #define CLK_MOUT_MFC_PLL_USER 14 2296bd6224SChanwoo Choi #define CLK_MOUT_BUS_PLL_USER 15 2396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_HEVC_400 16 2496bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_333 17 2596bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_B 18 2696bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_A 19 2796bd6224SChanwoo Choi #define CLK_MOUT_ACLK_ISP_DIS_400 20 2896bd6224SChanwoo Choi #define CLK_MOUT_ACLK_ISP_400 21 2996bd6224SChanwoo Choi #define CLK_MOUT_ACLK_BUS0_400 22 3096bd6224SChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_B 23 3196bd6224SChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_A 24 3296bd6224SChanwoo Choi #define CLK_MOUT_ACLK_GSCL_333 25 3396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_G2D_400_B 26 3496bd6224SChanwoo Choi #define CLK_MOUT_ACLK_G2D_400_A 27 3596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_C 28 3696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_B 29 3796bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_A 30 3896bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_B 31 3996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_A 32 4096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_B 33 4196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_A 34 4296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_D 35 4396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_C 36 4496bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_B 37 4596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_A 38 4696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI4 39 4796bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI3 40 4896bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART2 41 4996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART1 42 5096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART0 43 5196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI2 44 5296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI1 45 5396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI0 46 5423236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_C 47 5523236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_B 48 5623236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_A 49 5723236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR2 50 5823236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR1 51 5923236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR0 52 6023236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_UART 53 6123236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI1 54 6223236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI0 55 6323236496SChanwoo Choi #define CLK_MOUT_SCLK_PCIE_100 56 6423236496SChanwoo Choi #define CLK_MOUT_SCLK_UFSUNIPRO 57 6523236496SChanwoo Choi #define CLK_MOUT_SCLK_USBHOST30 58 6623236496SChanwoo Choi #define CLK_MOUT_SCLK_USBDRD30 59 6723236496SChanwoo Choi #define CLK_MOUT_SCLK_SLIMBUS 60 6823236496SChanwoo Choi #define CLK_MOUT_SCLK_SPDIF 61 6923236496SChanwoo Choi #define CLK_MOUT_SCLK_AUDIO1 62 7023236496SChanwoo Choi #define CLK_MOUT_SCLK_AUDIO0 63 712a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_HDMI_SPDIF 64 7296bd6224SChanwoo Choi 7396bd6224SChanwoo Choi #define CLK_DIV_ACLK_FSYS_200 100 7496bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_SSSX_266 101 7596bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_200 102 7696bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_266 103 7796bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIC_66_B 104 7896bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIC_66_A 105 7996bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIS_66_B 106 8096bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIS_66_A 107 8196bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC1_B 108 8296bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC1_A 109 8396bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC0_B 110 8496bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC0_A 111 8596bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC2_B 112 8696bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC2_A 113 8796bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI1_B 114 8896bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI1_A 115 8996bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI0_B 116 9096bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI0_A 117 9196bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI2_B 118 9296bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI2_A 119 9396bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART2 120 9496bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART1 121 9596bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART0 122 9696bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI4_B 123 9796bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI4_A 124 9896bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI3_B 125 9996bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI3_A 126 10023236496SChanwoo Choi #define CLK_DIV_SCLK_I2S1 127 10123236496SChanwoo Choi #define CLK_DIV_SCLK_PCM1 128 10223236496SChanwoo Choi #define CLK_DIV_SCLK_AUDIO1 129 10323236496SChanwoo Choi #define CLK_DIV_SCLK_AUDIO0 130 104a29308daSChanwoo Choi #define CLK_DIV_ACLK_GSCL_111 131 105a29308daSChanwoo Choi #define CLK_DIV_ACLK_GSCL_333 132 106a29308daSChanwoo Choi #define CLK_DIV_ACLK_HEVC_400 133 107a29308daSChanwoo Choi #define CLK_DIV_ACLK_MFC_400 134 108a29308daSChanwoo Choi #define CLK_DIV_ACLK_G2D_266 135 109a29308daSChanwoo Choi #define CLK_DIV_ACLK_G2D_400 136 1105785d6e6SChanwoo Choi #define CLK_DIV_ACLK_G3D_400 137 1115785d6e6SChanwoo Choi #define CLK_DIV_ACLK_BUS0_400 138 1125785d6e6SChanwoo Choi #define CLK_DIV_ACLK_BUS1_400 139 11396bd6224SChanwoo Choi 11496bd6224SChanwoo Choi #define CLK_ACLK_PERIC_66 200 11596bd6224SChanwoo Choi #define CLK_ACLK_PERIS_66 201 11696bd6224SChanwoo Choi #define CLK_ACLK_FSYS_200 202 11796bd6224SChanwoo Choi #define CLK_SCLK_MMC2_FSYS 203 11896bd6224SChanwoo Choi #define CLK_SCLK_MMC1_FSYS 204 11996bd6224SChanwoo Choi #define CLK_SCLK_MMC0_FSYS 205 12096bd6224SChanwoo Choi #define CLK_SCLK_SPI4_PERIC 206 12196bd6224SChanwoo Choi #define CLK_SCLK_SPI3_PERIC 207 12296bd6224SChanwoo Choi #define CLK_SCLK_UART2_PERIC 208 12396bd6224SChanwoo Choi #define CLK_SCLK_UART1_PERIC 209 12496bd6224SChanwoo Choi #define CLK_SCLK_UART0_PERIC 210 12596bd6224SChanwoo Choi #define CLK_SCLK_SPI2_PERIC 211 12696bd6224SChanwoo Choi #define CLK_SCLK_SPI1_PERIC 212 12796bd6224SChanwoo Choi #define CLK_SCLK_SPI0_PERIC 213 12823236496SChanwoo Choi #define CLK_SCLK_SPDIF_PERIC 214 12923236496SChanwoo Choi #define CLK_SCLK_I2S1_PERIC 215 13023236496SChanwoo Choi #define CLK_SCLK_PCM1_PERIC 216 13123236496SChanwoo Choi #define CLK_SCLK_SLIMBUS 217 13223236496SChanwoo Choi #define CLK_SCLK_AUDIO1 218 13323236496SChanwoo Choi #define CLK_SCLK_AUDIO0 219 134a29308daSChanwoo Choi #define CLK_ACLK_G2D_266 220 135a29308daSChanwoo Choi #define CLK_ACLK_G2D_400 221 1365785d6e6SChanwoo Choi #define CLK_ACLK_G3D_400 222 1375785d6e6SChanwoo Choi #define CLK_ACLK_IMEM_SSX_266 223 1385785d6e6SChanwoo Choi #define CLK_ACLK_BUS0_400 224 1395785d6e6SChanwoo Choi #define CLK_ACLK_BUS1_400 225 1405785d6e6SChanwoo Choi #define CLK_ACLK_IMEM_200 226 1415785d6e6SChanwoo Choi #define CLK_ACLK_IMEM_266 227 14296bd6224SChanwoo Choi 1435785d6e6SChanwoo Choi #define TOP_NR_CLK 228 14496bd6224SChanwoo Choi 14596bd6224SChanwoo Choi /* CMU_CPIF */ 14696bd6224SChanwoo Choi #define CLK_FOUT_MPHY_PLL 1 14796bd6224SChanwoo Choi 14896bd6224SChanwoo Choi #define CLK_MOUT_MPHY_PLL 2 14996bd6224SChanwoo Choi 15096bd6224SChanwoo Choi #define CLK_DIV_SCLK_MPHY 10 15196bd6224SChanwoo Choi 15296bd6224SChanwoo Choi #define CLK_SCLK_MPHY_PLL 11 15396bd6224SChanwoo Choi #define CLK_SCLK_UFS_MPHY 11 15496bd6224SChanwoo Choi 15596bd6224SChanwoo Choi #define CPIF_NR_CLK 12 15696bd6224SChanwoo Choi 15796bd6224SChanwoo Choi /* CMU_MIF */ 15896bd6224SChanwoo Choi #define CLK_FOUT_MEM0_PLL 1 15996bd6224SChanwoo Choi #define CLK_FOUT_MEM1_PLL 2 16096bd6224SChanwoo Choi #define CLK_FOUT_BUS_PLL 3 16196bd6224SChanwoo Choi #define CLK_FOUT_MFC_PLL 4 16206d2f9dfSChanwoo Choi #define CLK_DOUT_MFC_PLL 5 16306d2f9dfSChanwoo Choi #define CLK_DOUT_BUS_PLL 6 16406d2f9dfSChanwoo Choi #define CLK_DOUT_MEM1_PLL 7 16506d2f9dfSChanwoo Choi #define CLK_DOUT_MEM0_PLL 8 16696bd6224SChanwoo Choi 16706d2f9dfSChanwoo Choi #define CLK_MOUT_MFC_PLL_DIV2 10 16806d2f9dfSChanwoo Choi #define CLK_MOUT_BUS_PLL_DIV2 11 16906d2f9dfSChanwoo Choi #define CLK_MOUT_MEM1_PLL_DIV2 12 17006d2f9dfSChanwoo Choi #define CLK_MOUT_MEM0_PLL_DIV2 13 17106d2f9dfSChanwoo Choi #define CLK_MOUT_MFC_PLL 14 17206d2f9dfSChanwoo Choi #define CLK_MOUT_BUS_PLL 15 17306d2f9dfSChanwoo Choi #define CLK_MOUT_MEM1_PLL 16 17406d2f9dfSChanwoo Choi #define CLK_MOUT_MEM0_PLL 17 17506d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_C 18 17606d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_B 19 17706d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_A 20 17806d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_C 21 17906d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_B 22 18006d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_A 23 18106d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_MIFNM_200 24 18206d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_MIFNM_400 25 18306d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_B 26 18406d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_A 27 18506d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_C 28 18606d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_B 29 18706d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_A 30 18806d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_C 31 18906d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_B 32 19006d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_A 33 19106d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34 19206d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35 19306d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36 19406d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_C 37 19506d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_B 38 19606d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_A 39 19706d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_C 40 19806d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_B 41 19906d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_A 42 20006d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46 20106d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47 20206d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48 20306d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_C 49 20406d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_B 50 20506d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_A 51 20606d2f9dfSChanwoo Choi 20706d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_HPM_MIF 55 20806d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DREX1 56 20906d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DREX0 57 21006d2f9dfSChanwoo Choi #define CLK_DIV_CLK2XPHY 58 21106d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_266 59 21206d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIFND_133 60 21306d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_133 61 21406d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIFNM_200 62 21506d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_200 63 21606d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_400 64 21706d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_BUS2_400 65 21806d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DISP_333 66 21906d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_CPIF_200 67 22006d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSIM1 68 22106d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_VCLK 69 22206d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSIM0 70 22306d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSD 71 22406d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_ECLK 72 22506d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_VCLK 73 22606d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_ECLK 74 22706d2f9dfSChanwoo Choi #define CLK_DIV_MIF_PRE 75 22806d2f9dfSChanwoo Choi 22906d2f9dfSChanwoo Choi #define CLK_CLK2X_PHY1 80 23006d2f9dfSChanwoo Choi #define CLK_CLK2X_PHY0 81 23106d2f9dfSChanwoo Choi #define CLK_CLKM_PHY1 82 23206d2f9dfSChanwoo Choi #define CLK_CLKM_PHY0 83 23306d2f9dfSChanwoo Choi #define CLK_RCLK_DREX1 84 23406d2f9dfSChanwoo Choi #define CLK_RCLK_DREX0 85 23506d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_TZ 86 23606d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_TZ 87 23706d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_PEREV 88 23806d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_PEREV 89 23906d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_MEMIF 90 24006d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_MEMIF 91 24106d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_SCH 92 24206d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_SCH 93 24306d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_BUSIF 94 24406d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_BUSIF 95 24506d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_BUSIF_RD 96 24606d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_BUSIF_RD 97 24706d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1 98 24806d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0 99 24906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100 25006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101 25106d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102 25206d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103 25306d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104 25406d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105 25506d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_CP1 106 25606d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_CP1 107 25706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_CP0 108 25806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_CP0 109 25906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_3 110 26006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_3 111 26106d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_1 112 26206d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_1 113 26306d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_0 114 26406d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_0 115 26506d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_3 116 26606d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_3 117 26706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_1 118 26806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_1 119 26906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_0 120 27006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_0 121 27106d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF2P 122 27206d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF1P 123 27306d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF0P 124 27406d2f9dfSChanwoo Choi #define CLK_ACLK_IXIU_CCI 125 27506d2f9dfSChanwoo Choi #define CLK_ACLK_XIU_MIFSFRX 126 27606d2f9dfSChanwoo Choi #define CLK_ACLK_MIFNP_133 127 27706d2f9dfSChanwoo Choi #define CLK_ACLK_MIFNM_200 128 27806d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_133 129 27906d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_400 130 28006d2f9dfSChanwoo Choi #define CLK_ACLK_CCI 131 28106d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_266 132 28206d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S3 133 28306d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S1 134 28406d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S0 135 28506d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S3 136 28606d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S1 137 28706d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S0 138 28806d2f9dfSChanwoo Choi #define CLK_ACLK_BTS_APOLLO 139 28906d2f9dfSChanwoo Choi #define CLK_ACLK_BTS_ATLAS 140 29006d2f9dfSChanwoo Choi #define CLK_ACLK_ACE_SEL_APOLL 141 29106d2f9dfSChanwoo Choi #define CLK_ACLK_ACE_SEL_ATLAS 142 29206d2f9dfSChanwoo Choi #define CLK_ACLK_AXIDS_CCI_MIFSFRX 143 29306d2f9dfSChanwoo Choi #define CLK_ACLK_AXIUS_ATLAS_CCI 144 29406d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDNS_CCI 145 29506d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDN_CCI 146 29606d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDN_NOC_D 147 29706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148 29806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149 29906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150 30006d2f9dfSChanwoo Choi #define CLK_ACLK_BUS2_400 151 30106d2f9dfSChanwoo Choi #define CLK_ACLK_DISP_333 152 30206d2f9dfSChanwoo Choi #define CLK_ACLK_CPIF_200 153 30306d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S3 154 30406d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S1 155 30506d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S0 156 30606d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S3 157 30706d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S1 158 30806d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S0 159 30906d2f9dfSChanwoo Choi #define CLK_PCLK_BTS_APOLLO 160 31006d2f9dfSChanwoo Choi #define CLK_PCLK_BTS_ATLAS 161 31106d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162 31206d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_CP1 163 31306d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_CP0 164 31406d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_3 165 31506d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_1 166 31606d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_0 167 31706d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_3 168 31806d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_1 169 31906d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_0 170 32006d2f9dfSChanwoo Choi #define CLK_PCLK_MIFSRVND_133 171 32106d2f9dfSChanwoo Choi #define CLK_PCLK_PMU_MIF 172 32206d2f9dfSChanwoo Choi #define CLK_PCLK_SYSREG_MIF 173 32306d2f9dfSChanwoo Choi #define CLK_PCLK_GPIO_ALIVE 174 32406d2f9dfSChanwoo Choi #define CLK_PCLK_ABB 175 32506d2f9dfSChanwoo Choi #define CLK_PCLK_PMU_APBIF 176 32606d2f9dfSChanwoo Choi #define CLK_PCLK_DDR_PHY1 177 32706d2f9dfSChanwoo Choi #define CLK_PCLK_DREX1 178 32806d2f9dfSChanwoo Choi #define CLK_PCLK_DDR_PHY0 179 32906d2f9dfSChanwoo Choi #define CLK_PCLK_DREX0 180 33006d2f9dfSChanwoo Choi #define CLK_PCLK_DREX0_TZ 181 33106d2f9dfSChanwoo Choi #define CLK_PCLK_DREX1_TZ 182 33206d2f9dfSChanwoo Choi #define CLK_PCLK_MONOTONIC_CNT 183 33306d2f9dfSChanwoo Choi #define CLK_PCLK_RTC 184 33406d2f9dfSChanwoo Choi #define CLK_SCLK_DSIM1_DISP 185 33506d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_TV_VCLK_DISP 186 33606d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_BUS_PLL 187 33706d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MFC_PLL 188 33806d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MEM0_PLL 189 33906d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MEM1_PLL 190 34006d2f9dfSChanwoo Choi #define CLK_SCLK_DSIM0_DISP 191 34106d2f9dfSChanwoo Choi #define CLK_SCLK_DSD_DISP 192 34206d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_TV_ECLK_DISP 193 34306d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_VCLK_DISP 194 34406d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_ECLK_DISP 195 34506d2f9dfSChanwoo Choi #define CLK_SCLK_HPM_MIF 196 34606d2f9dfSChanwoo Choi #define CLK_SCLK_MFC_PLL 197 34706d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL 198 34806d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL_APOLLO 199 34906d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL_ATLAS 200 3502a1808a6SChanwoo Choi #define CLK_SCLK_HDMI_SPDIF_DISP 201 35106d2f9dfSChanwoo Choi 3522a1808a6SChanwoo Choi #define MIF_NR_CLK 202 35396bd6224SChanwoo Choi 35496bd6224SChanwoo Choi /* CMU_PERIC */ 35596bd6224SChanwoo Choi #define CLK_PCLK_SPI2 1 35696bd6224SChanwoo Choi #define CLK_PCLK_SPI1 2 35796bd6224SChanwoo Choi #define CLK_PCLK_SPI0 3 35896bd6224SChanwoo Choi #define CLK_PCLK_UART2 4 35996bd6224SChanwoo Choi #define CLK_PCLK_UART1 5 36096bd6224SChanwoo Choi #define CLK_PCLK_UART0 6 36196bd6224SChanwoo Choi #define CLK_PCLK_HSI2C3 7 36296bd6224SChanwoo Choi #define CLK_PCLK_HSI2C2 8 36396bd6224SChanwoo Choi #define CLK_PCLK_HSI2C1 9 36496bd6224SChanwoo Choi #define CLK_PCLK_HSI2C0 10 36596bd6224SChanwoo Choi #define CLK_PCLK_I2C7 11 36696bd6224SChanwoo Choi #define CLK_PCLK_I2C6 12 36796bd6224SChanwoo Choi #define CLK_PCLK_I2C5 13 36896bd6224SChanwoo Choi #define CLK_PCLK_I2C4 14 36996bd6224SChanwoo Choi #define CLK_PCLK_I2C3 15 37096bd6224SChanwoo Choi #define CLK_PCLK_I2C2 16 37196bd6224SChanwoo Choi #define CLK_PCLK_I2C1 17 37296bd6224SChanwoo Choi #define CLK_PCLK_I2C0 18 37396bd6224SChanwoo Choi #define CLK_PCLK_SPI4 19 37496bd6224SChanwoo Choi #define CLK_PCLK_SPI3 20 37596bd6224SChanwoo Choi #define CLK_PCLK_HSI2C11 21 37696bd6224SChanwoo Choi #define CLK_PCLK_HSI2C10 22 37796bd6224SChanwoo Choi #define CLK_PCLK_HSI2C9 23 37896bd6224SChanwoo Choi #define CLK_PCLK_HSI2C8 24 37996bd6224SChanwoo Choi #define CLK_PCLK_HSI2C7 25 38096bd6224SChanwoo Choi #define CLK_PCLK_HSI2C6 26 38196bd6224SChanwoo Choi #define CLK_PCLK_HSI2C5 27 38296bd6224SChanwoo Choi #define CLK_PCLK_HSI2C4 28 38396bd6224SChanwoo Choi #define CLK_SCLK_SPI4 29 38496bd6224SChanwoo Choi #define CLK_SCLK_SPI3 30 38596bd6224SChanwoo Choi #define CLK_SCLK_SPI2 31 38696bd6224SChanwoo Choi #define CLK_SCLK_SPI1 32 38796bd6224SChanwoo Choi #define CLK_SCLK_SPI0 33 38896bd6224SChanwoo Choi #define CLK_SCLK_UART2 34 38996bd6224SChanwoo Choi #define CLK_SCLK_UART1 35 39096bd6224SChanwoo Choi #define CLK_SCLK_UART0 36 391d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC2P 37 392d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC1P 38 393d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC0P 39 394d0f5de66SChanwoo Choi #define CLK_ACLK_PERICNP_66 40 395d0f5de66SChanwoo Choi #define CLK_PCLK_SCI 41 396d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_FINGER 42 397d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_ESE 43 398d0f5de66SChanwoo Choi #define CLK_PCLK_PWM 44 399d0f5de66SChanwoo Choi #define CLK_PCLK_SPDIF 45 400d0f5de66SChanwoo Choi #define CLK_PCLK_PCM1 46 401d0f5de66SChanwoo Choi #define CLK_PCLK_I2S1 47 402d0f5de66SChanwoo Choi #define CLK_PCLK_ADCIF 48 403d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_TOUCH 49 404d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_NFC 50 405d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_PERIC 51 406d0f5de66SChanwoo Choi #define CLK_PCLK_PMU_PERIC 52 407d0f5de66SChanwoo Choi #define CLK_PCLK_SYSREG_PERIC 53 408d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI4 54 409d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI3 55 410d0f5de66SChanwoo Choi #define CLK_SCLK_SCI 56 411d0f5de66SChanwoo Choi #define CLK_SCLK_SC_IN 57 412d0f5de66SChanwoo Choi #define CLK_SCLK_PWM 58 413d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI2 59 414d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI1 60 415d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI0 61 416d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_I2S1_BCLK 62 417d0f5de66SChanwoo Choi #define CLK_SCLK_SPDIF 63 418d0f5de66SChanwoo Choi #define CLK_SCLK_PCM1 64 419d0f5de66SChanwoo Choi #define CLK_SCLK_I2S1 65 42096bd6224SChanwoo Choi 421d0f5de66SChanwoo Choi #define CLK_DIV_SCLK_SCI 70 422d0f5de66SChanwoo Choi #define CLK_DIV_SCLK_SC_IN 71 423d0f5de66SChanwoo Choi 424d0f5de66SChanwoo Choi #define PERIC_NR_CLK 72 42596bd6224SChanwoo Choi 42696bd6224SChanwoo Choi /* CMU_PERIS */ 42796bd6224SChanwoo Choi #define CLK_PCLK_HPM_APBIF 1 42896bd6224SChanwoo Choi #define CLK_PCLK_TMU1_APBIF 2 42996bd6224SChanwoo Choi #define CLK_PCLK_TMU0_APBIF 3 43096bd6224SChanwoo Choi #define CLK_PCLK_PMU_PERIS 4 43196bd6224SChanwoo Choi #define CLK_PCLK_SYSREG_PERIS 5 43296bd6224SChanwoo Choi #define CLK_PCLK_CMU_TOP_APBIF 6 43396bd6224SChanwoo Choi #define CLK_PCLK_WDT_APOLLO 7 43496bd6224SChanwoo Choi #define CLK_PCLK_WDT_ATLAS 8 43596bd6224SChanwoo Choi #define CLK_PCLK_MCT 9 43696bd6224SChanwoo Choi #define CLK_PCLK_HDMI_CEC 10 43756bcf3f3SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIS1P 11 43856bcf3f3SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIS0P 12 43956bcf3f3SChanwoo Choi #define CLK_ACLK_PERISNP_66 13 44056bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC12 14 44156bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC11 15 44256bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC10 16 44356bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC9 17 44456bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC8 18 44556bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC7 19 44656bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC6 20 44756bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC5 21 44856bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC4 22 44956bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC3 23 45056bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC2 24 45156bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC1 25 45256bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC0 26 45356bcf3f3SChanwoo Choi #define CLK_PCLK_SECKEY_APBIF 27 45456bcf3f3SChanwoo Choi #define CLK_PCLK_CHIPID_APBIF 28 45556bcf3f3SChanwoo Choi #define CLK_PCLK_TOPRTC 29 45656bcf3f3SChanwoo Choi #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 45756bcf3f3SChanwoo Choi #define CLK_PCLK_ANTIRBK_CNT_APBIF 31 45856bcf3f3SChanwoo Choi #define CLK_PCLK_OTP_CON_APBIF 32 45956bcf3f3SChanwoo Choi #define CLK_SCLK_ASV_TB 33 46056bcf3f3SChanwoo Choi #define CLK_SCLK_TMU1 34 46156bcf3f3SChanwoo Choi #define CLK_SCLK_TMU0 35 46256bcf3f3SChanwoo Choi #define CLK_SCLK_SECKEY 36 46356bcf3f3SChanwoo Choi #define CLK_SCLK_CHIPID 37 46456bcf3f3SChanwoo Choi #define CLK_SCLK_TOPRTC 38 46556bcf3f3SChanwoo Choi #define CLK_SCLK_CUSTOM_EFUSE 39 46656bcf3f3SChanwoo Choi #define CLK_SCLK_ANTIRBK_CNT 40 46756bcf3f3SChanwoo Choi #define CLK_SCLK_OTP_CON 41 46896bd6224SChanwoo Choi 46956bcf3f3SChanwoo Choi #define PERIS_NR_CLK 42 47096bd6224SChanwoo Choi 47196bd6224SChanwoo Choi /* CMU_FSYS */ 47296bd6224SChanwoo Choi #define CLK_MOUT_ACLK_FSYS_200_USER 1 47396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_USER 2 47496bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_USER 3 47596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_USER 4 47696bd6224SChanwoo Choi 47796bd6224SChanwoo Choi #define CLK_ACLK_PCIE 50 47896bd6224SChanwoo Choi #define CLK_ACLK_PDMA1 51 47996bd6224SChanwoo Choi #define CLK_ACLK_TSI 52 48096bd6224SChanwoo Choi #define CLK_ACLK_MMC2 53 48196bd6224SChanwoo Choi #define CLK_ACLK_MMC1 54 48296bd6224SChanwoo Choi #define CLK_ACLK_MMC0 55 48396bd6224SChanwoo Choi #define CLK_ACLK_UFS 56 48496bd6224SChanwoo Choi #define CLK_ACLK_USBHOST20 57 48596bd6224SChanwoo Choi #define CLK_ACLK_USBHOST30 58 48696bd6224SChanwoo Choi #define CLK_ACLK_USBDRD30 59 48796bd6224SChanwoo Choi #define CLK_ACLK_PDMA0 60 48896bd6224SChanwoo Choi #define CLK_SCLK_MMC2 61 48996bd6224SChanwoo Choi #define CLK_SCLK_MMC1 62 49096bd6224SChanwoo Choi #define CLK_SCLK_MMC0 63 49196bd6224SChanwoo Choi #define CLK_PDMA1 64 49296bd6224SChanwoo Choi #define CLK_PDMA0 65 49396bd6224SChanwoo Choi 49496bd6224SChanwoo Choi #define FSYS_NR_CLK 66 49596bd6224SChanwoo Choi 496a29308daSChanwoo Choi /* CMU_G2D */ 497a29308daSChanwoo Choi #define CLK_MUX_ACLK_G2D_266_USER 1 498a29308daSChanwoo Choi #define CLK_MUX_ACLK_G2D_400_USER 2 499a29308daSChanwoo Choi 500a29308daSChanwoo Choi #define CLK_DIV_PCLK_G2D 3 501a29308daSChanwoo Choi 502a29308daSChanwoo Choi #define CLK_ACLK_SMMU_MDMA1 4 503a29308daSChanwoo Choi #define CLK_ACLK_BTS_MDMA1 5 504a29308daSChanwoo Choi #define CLK_ACLK_BTS_G2D 6 505a29308daSChanwoo Choi #define CLK_ACLK_ALB_G2D 7 506a29308daSChanwoo Choi #define CLK_ACLK_AXIUS_G2DX 8 507a29308daSChanwoo Choi #define CLK_ACLK_ASYNCAXI_SYSX 9 508a29308daSChanwoo Choi #define CLK_ACLK_AHB2APB_G2D1P 10 509a29308daSChanwoo Choi #define CLK_ACLK_AHB2APB_G2D0P 11 510a29308daSChanwoo Choi #define CLK_ACLK_XIU_G2DX 12 511a29308daSChanwoo Choi #define CLK_ACLK_G2DNP_133 13 512a29308daSChanwoo Choi #define CLK_ACLK_G2DND_400 14 513a29308daSChanwoo Choi #define CLK_ACLK_MDMA1 15 514a29308daSChanwoo Choi #define CLK_ACLK_G2D 16 515a29308daSChanwoo Choi #define CLK_ACLK_SMMU_G2D 17 516a29308daSChanwoo Choi #define CLK_PCLK_SMMU_MDMA1 18 517a29308daSChanwoo Choi #define CLK_PCLK_BTS_MDMA1 19 518a29308daSChanwoo Choi #define CLK_PCLK_BTS_G2D 20 519a29308daSChanwoo Choi #define CLK_PCLK_ALB_G2D 21 520a29308daSChanwoo Choi #define CLK_PCLK_ASYNCAXI_SYSX 22 521a29308daSChanwoo Choi #define CLK_PCLK_PMU_G2D 23 522a29308daSChanwoo Choi #define CLK_PCLK_SYSREG_G2D 24 523a29308daSChanwoo Choi #define CLK_PCLK_G2D 25 524a29308daSChanwoo Choi #define CLK_PCLK_SMMU_G2D 26 525a29308daSChanwoo Choi 526a29308daSChanwoo Choi #define G2D_NR_CLK 27 527a29308daSChanwoo Choi 5282a1808a6SChanwoo Choi /* CMU_DISP */ 5292a1808a6SChanwoo Choi #define CLK_FOUT_DISP_PLL 1 5302a1808a6SChanwoo Choi 5312a1808a6SChanwoo Choi #define CLK_MOUT_DISP_PLL 2 5322a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_USER 3 5332a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_USER 4 5342a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSD_USER 5 5352a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6 5362a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_USER 7 5372a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_USER 8 5382a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9 5392a1808a6SChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_USER 10 5402a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11 5412a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12 5422a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13 5432a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14 5442a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15 5452a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16 5462a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM0 17 5472a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK 18 5482a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK 19 5492a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK 20 5502a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_B_DISP 21 5512a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_A_DISP 22 5522a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23 5532a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24 5542a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25 5552a1808a6SChanwoo Choi 5562a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DSIM1_DISP 30 5572a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31 5582a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DSIM0_DISP 32 5592a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33 5602a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_VCLK_DISP 34 5612a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_ECLK_DISP 35 5622a1808a6SChanwoo Choi #define CLK_DIV_PCLK_DISP 36 5632a1808a6SChanwoo Choi 5642a1808a6SChanwoo Choi #define CLK_ACLK_DECON_TV 40 5652a1808a6SChanwoo Choi #define CLK_ACLK_DECON 41 5662a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_TV1X 42 5672a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_TV0X 43 5682a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_DECON1X 44 5692a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_DECON0X 45 5702a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M3 46 5712a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M2 47 5722a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M1 48 5732a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M0 49 5742a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM4 50 5752a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM3 51 5762a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM2 52 5772a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM1 53 5782a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM0 54 5792a1808a6SChanwoo Choi #define CLK_ACLK_AHB2APB_DISPSFR2P 55 5802a1808a6SChanwoo Choi #define CLK_ACLK_AHB2APB_DISPSFR1P 56 5812a1808a6SChanwoo Choi #define CLK_ACLK_AHB2APB_DISPSFR0P 57 5822a1808a6SChanwoo Choi #define CLK_ACLK_AHB_DISPH 58 5832a1808a6SChanwoo Choi #define CLK_ACLK_XIU_TV1X 59 5842a1808a6SChanwoo Choi #define CLK_ACLK_XIU_TV0X 60 5852a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DECON1X 61 5862a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DECON0X 62 5872a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DISP1X 63 5882a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DISPNP_100 64 5892a1808a6SChanwoo Choi #define CLK_ACLK_DISP1ND_333 65 5902a1808a6SChanwoo Choi #define CLK_ACLK_DISP0ND_333 66 5912a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_TV1X 67 5922a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_TV0X 68 5932a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_DECON1X 69 5942a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_DECON0X 70 5952a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M3 71 5962a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M2 72 5972a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M1 73 5982a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M0 74 5992a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM4 75 6002a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM3 76 6012a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM2 77 6022a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM1 78 6032a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM0 79 6042a1808a6SChanwoo Choi #define CLK_PCLK_MIC1 80 6052a1808a6SChanwoo Choi #define CLK_PCLK_PMU_DISP 81 6062a1808a6SChanwoo Choi #define CLK_PCLK_SYSREG_DISP 82 6072a1808a6SChanwoo Choi #define CLK_PCLK_HDMIPHY 83 6082a1808a6SChanwoo Choi #define CLK_PCLK_HDMI 84 6092a1808a6SChanwoo Choi #define CLK_PCLK_MIC0 85 6102a1808a6SChanwoo Choi #define CLK_PCLK_DSIM1 86 6112a1808a6SChanwoo Choi #define CLK_PCLK_DSIM0 87 6122a1808a6SChanwoo Choi #define CLK_PCLK_DECON_TV 88 6132a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89 6142a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90 6152a1808a6SChanwoo Choi #define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91 6162a1808a6SChanwoo Choi #define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92 6172a1808a6SChanwoo Choi #define CLK_SCLK_DSIM1 93 6182a1808a6SChanwoo Choi #define CLK_SCLK_DECON_TV_VCLK 94 6192a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95 6202a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96 6212a1808a6SChanwoo Choi #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97 6222a1808a6SChanwoo Choi #define CLK_PHYCLK_HDMI_PIXEL 98 6232a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK_TO_SMIES 99 6242a1808a6SChanwoo Choi #define CLK_SCLK_FREQ_DET_DISP_PLL 100 6252a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK_TO_DSIM0 101 6262a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK_TO_MIC0 102 6272a1808a6SChanwoo Choi #define CLK_SCLK_DSD 103 6282a1808a6SChanwoo Choi #define CLK_SCLK_HDMI_SPDIF 104 6292a1808a6SChanwoo Choi #define CLK_SCLK_DSIM0 105 6302a1808a6SChanwoo Choi #define CLK_SCLK_DECON_TV_ECLK 106 6312a1808a6SChanwoo Choi #define CLK_SCLK_DECON_VCLK 107 6322a1808a6SChanwoo Choi #define CLK_SCLK_DECON_ECLK 108 6332a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK 109 6342a1808a6SChanwoo Choi #define CLK_SCLK_RGB_TV_VCLK 110 6352a1808a6SChanwoo Choi 6362a1808a6SChanwoo Choi #define DISP_NR_CLK 111 6372a1808a6SChanwoo Choi 6382e997c03SChanwoo Choi /* CMU_AUD */ 6392e997c03SChanwoo Choi #define CLK_MOUT_AUD_PLL_USER 1 6402e997c03SChanwoo Choi #define CLK_MOUT_SCLK_AUD_PCM 2 6412e997c03SChanwoo Choi #define CLK_MOUT_SCLK_AUD_I2S 3 6422e997c03SChanwoo Choi 6432e997c03SChanwoo Choi #define CLK_DIV_ATCLK_AUD 4 6442e997c03SChanwoo Choi #define CLK_DIV_PCLK_DBG_AUD 5 6452e997c03SChanwoo Choi #define CLK_DIV_ACLK_AUD 6 6462e997c03SChanwoo Choi #define CLK_DIV_AUD_CA5 7 6472e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_SLIMBUS 8 6482e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_UART 9 6492e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_PCM 10 6502e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_I2S 11 6512e997c03SChanwoo Choi 6522e997c03SChanwoo Choi #define CLK_ACLK_INTR_CTRL 12 6532e997c03SChanwoo Choi #define CLK_ACLK_AXIDS2_LPASSP 13 6542e997c03SChanwoo Choi #define CLK_ACLK_AXIDS1_LPASSP 14 6552e997c03SChanwoo Choi #define CLK_ACLK_AXI2APB1_LPASSP 15 6562e997c03SChanwoo Choi #define CLK_ACLK_AXI2APH_LPASSP 16 6572e997c03SChanwoo Choi #define CLK_ACLK_SMMU_LPASSX 17 6582e997c03SChanwoo Choi #define CLK_ACLK_AXIDS0_LPASSP 18 6592e997c03SChanwoo Choi #define CLK_ACLK_AXI2APB0_LPASSP 19 6602e997c03SChanwoo Choi #define CLK_ACLK_XIU_LPASSX 20 6612e997c03SChanwoo Choi #define CLK_ACLK_AUDNP_133 21 6622e997c03SChanwoo Choi #define CLK_ACLK_AUDND_133 22 6632e997c03SChanwoo Choi #define CLK_ACLK_SRAMC 23 6642e997c03SChanwoo Choi #define CLK_ACLK_DMAC 24 6652e997c03SChanwoo Choi #define CLK_PCLK_WDT1 25 6662e997c03SChanwoo Choi #define CLK_PCLK_WDT0 26 6672e997c03SChanwoo Choi #define CLK_PCLK_SFR1 27 6682e997c03SChanwoo Choi #define CLK_PCLK_SMMU_LPASSX 28 6692e997c03SChanwoo Choi #define CLK_PCLK_GPIO_AUD 29 6702e997c03SChanwoo Choi #define CLK_PCLK_PMU_AUD 30 6712e997c03SChanwoo Choi #define CLK_PCLK_SYSREG_AUD 31 6722e997c03SChanwoo Choi #define CLK_PCLK_AUD_SLIMBUS 32 6732e997c03SChanwoo Choi #define CLK_PCLK_AUD_UART 33 6742e997c03SChanwoo Choi #define CLK_PCLK_AUD_PCM 34 6752e997c03SChanwoo Choi #define CLK_PCLK_AUD_I2S 35 6762e997c03SChanwoo Choi #define CLK_PCLK_TIMER 36 6772e997c03SChanwoo Choi #define CLK_PCLK_SFR0_CTRL 37 6782e997c03SChanwoo Choi #define CLK_ATCLK_AUD 38 6792e997c03SChanwoo Choi #define CLK_PCLK_DBG_AUD 39 6802e997c03SChanwoo Choi #define CLK_SCLK_AUD_CA5 40 6812e997c03SChanwoo Choi #define CLK_SCLK_JTAG_TCK 41 6822e997c03SChanwoo Choi #define CLK_SCLK_SLIMBUS_CLKIN 42 6832e997c03SChanwoo Choi #define CLK_SCLK_AUD_SLIMBUS 43 6842e997c03SChanwoo Choi #define CLK_SCLK_AUD_UART 44 6852e997c03SChanwoo Choi #define CLK_SCLK_AUD_PCM 45 6862e997c03SChanwoo Choi #define CLK_SCLK_I2S_BCLK 46 6872e997c03SChanwoo Choi #define CLK_SCLK_AUD_I2S 47 6882e997c03SChanwoo Choi 6892e997c03SChanwoo Choi #define AUD_NR_CLK 48 6902e997c03SChanwoo Choi 6915785d6e6SChanwoo Choi /* CMU_BUS{0|1|2} */ 6925785d6e6SChanwoo Choi #define CLK_DIV_PCLK_BUS_133 1 6935785d6e6SChanwoo Choi 6945785d6e6SChanwoo Choi #define CLK_ACLK_AHB2APB_BUSP 2 6955785d6e6SChanwoo Choi #define CLK_ACLK_BUSNP_133 3 6965785d6e6SChanwoo Choi #define CLK_ACLK_BUSND_400 4 6975785d6e6SChanwoo Choi #define CLK_PCLK_BUSSRVND_133 5 6985785d6e6SChanwoo Choi #define CLK_PCLK_PMU_BUS 6 6995785d6e6SChanwoo Choi #define CLK_PCLK_SYSREG_BUS 7 7005785d6e6SChanwoo Choi 7015785d6e6SChanwoo Choi #define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */ 7025785d6e6SChanwoo Choi #define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ 7035785d6e6SChanwoo Choi #define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ 7045785d6e6SChanwoo Choi 7055785d6e6SChanwoo Choi #define BUSx_NR_CLK 11 7065785d6e6SChanwoo Choi 70796bd6224SChanwoo Choi #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 708