196bd6224SChanwoo Choi /*
296bd6224SChanwoo Choi  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
396bd6224SChanwoo Choi  * Author: Chanwoo Choi <cw00.choi@samsung.com>
496bd6224SChanwoo Choi  *
596bd6224SChanwoo Choi  * This program is free software; you can redistribute it and/or modify
696bd6224SChanwoo Choi  * it under the terms of the GNU General Public License version 2 as
796bd6224SChanwoo Choi  * published by the Free Software Foundation.
896bd6224SChanwoo Choi  */
996bd6224SChanwoo Choi 
1096bd6224SChanwoo Choi #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H
1196bd6224SChanwoo Choi #define _DT_BINDINGS_CLOCK_EXYNOS5433_H
1296bd6224SChanwoo Choi 
1396bd6224SChanwoo Choi /* CMU_TOP */
1496bd6224SChanwoo Choi #define CLK_FOUT_ISP_PLL		1
1596bd6224SChanwoo Choi #define CLK_FOUT_AUD_PLL		2
1696bd6224SChanwoo Choi 
1796bd6224SChanwoo Choi #define CLK_MOUT_AUD_PLL		10
1896bd6224SChanwoo Choi #define CLK_MOUT_ISP_PLL		11
1996bd6224SChanwoo Choi #define CLK_MOUT_AUD_PLL_USER_T		12
2096bd6224SChanwoo Choi #define CLK_MOUT_MPHY_PLL_USER		13
2196bd6224SChanwoo Choi #define CLK_MOUT_MFC_PLL_USER		14
2296bd6224SChanwoo Choi #define CLK_MOUT_BUS_PLL_USER		15
2396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_HEVC_400		16
2496bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_333		17
2596bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_B	18
2696bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_A	19
2796bd6224SChanwoo Choi #define CLK_MOUT_ACLK_ISP_DIS_400	20
2896bd6224SChanwoo Choi #define CLK_MOUT_ACLK_ISP_400		21
2996bd6224SChanwoo Choi #define CLK_MOUT_ACLK_BUS0_400		22
3096bd6224SChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_B	23
3196bd6224SChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_A	24
3296bd6224SChanwoo Choi #define CLK_MOUT_ACLK_GSCL_333		25
3396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_G2D_400_B		26
3496bd6224SChanwoo Choi #define CLK_MOUT_ACLK_G2D_400_A		27
3596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_C		28
3696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_B		29
3796bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_A		30
3896bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_B		31
3996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_A		32
4096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_B		33
4196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_A		34
4296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_D		35
4396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_C		36
4496bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_B		37
4596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_A		38
4696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI4		39
4796bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI3		40
4896bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART2		41
4996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART1		42
5096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART0		43
5196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI2		44
5296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI1		45
5396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI0		46
5423236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_C		47
5523236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_B		48
5623236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_A		49
5723236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR2	50
5823236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR1	51
5923236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR0	52
6023236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_UART		53
6123236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI1		54
6223236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI0		55
6323236496SChanwoo Choi #define CLK_MOUT_SCLK_PCIE_100		56
6423236496SChanwoo Choi #define CLK_MOUT_SCLK_UFSUNIPRO		57
6523236496SChanwoo Choi #define CLK_MOUT_SCLK_USBHOST30		58
6623236496SChanwoo Choi #define CLK_MOUT_SCLK_USBDRD30		59
6723236496SChanwoo Choi #define CLK_MOUT_SCLK_SLIMBUS		60
6823236496SChanwoo Choi #define CLK_MOUT_SCLK_SPDIF		61
6923236496SChanwoo Choi #define CLK_MOUT_SCLK_AUDIO1		62
7023236496SChanwoo Choi #define CLK_MOUT_SCLK_AUDIO0		63
712a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_HDMI_SPDIF	64
7296bd6224SChanwoo Choi 
7396bd6224SChanwoo Choi #define CLK_DIV_ACLK_FSYS_200		100
7496bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_SSSX_266	101
7596bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_200		102
7696bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_266		103
7796bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIC_66_B		104
7896bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIC_66_A		105
7996bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIS_66_B		106
8096bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIS_66_A		107
8196bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC1_B		108
8296bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC1_A		109
8396bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC0_B		110
8496bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC0_A		111
8596bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC2_B		112
8696bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC2_A		113
8796bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI1_B		114
8896bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI1_A		115
8996bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI0_B		116
9096bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI0_A		117
9196bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI2_B		118
9296bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI2_A		119
9396bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART2		120
9496bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART1		121
9596bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART0		122
9696bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI4_B		123
9796bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI4_A		124
9896bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI3_B		125
9996bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI3_A		126
10023236496SChanwoo Choi #define CLK_DIV_SCLK_I2S1		127
10123236496SChanwoo Choi #define CLK_DIV_SCLK_PCM1		128
10223236496SChanwoo Choi #define CLK_DIV_SCLK_AUDIO1		129
10323236496SChanwoo Choi #define CLK_DIV_SCLK_AUDIO0		130
104a29308daSChanwoo Choi #define CLK_DIV_ACLK_GSCL_111		131
105a29308daSChanwoo Choi #define CLK_DIV_ACLK_GSCL_333		132
106a29308daSChanwoo Choi #define CLK_DIV_ACLK_HEVC_400		133
107a29308daSChanwoo Choi #define CLK_DIV_ACLK_MFC_400		134
108a29308daSChanwoo Choi #define CLK_DIV_ACLK_G2D_266		135
109a29308daSChanwoo Choi #define CLK_DIV_ACLK_G2D_400		136
1105785d6e6SChanwoo Choi #define CLK_DIV_ACLK_G3D_400		137
1115785d6e6SChanwoo Choi #define CLK_DIV_ACLK_BUS0_400		138
1125785d6e6SChanwoo Choi #define CLK_DIV_ACLK_BUS1_400		139
1134b801355SChanwoo Choi #define CLK_DIV_SCLK_PCIE_100		140
1144b801355SChanwoo Choi #define CLK_DIV_SCLK_USBHOST30		141
1154b801355SChanwoo Choi #define CLK_DIV_SCLK_UFSUNIPRO		142
1164b801355SChanwoo Choi #define CLK_DIV_SCLK_USBDRD30		143
11796bd6224SChanwoo Choi 
11896bd6224SChanwoo Choi #define CLK_ACLK_PERIC_66		200
11996bd6224SChanwoo Choi #define CLK_ACLK_PERIS_66		201
12096bd6224SChanwoo Choi #define CLK_ACLK_FSYS_200		202
12196bd6224SChanwoo Choi #define CLK_SCLK_MMC2_FSYS		203
12296bd6224SChanwoo Choi #define CLK_SCLK_MMC1_FSYS		204
12396bd6224SChanwoo Choi #define CLK_SCLK_MMC0_FSYS		205
12496bd6224SChanwoo Choi #define CLK_SCLK_SPI4_PERIC		206
12596bd6224SChanwoo Choi #define CLK_SCLK_SPI3_PERIC		207
12696bd6224SChanwoo Choi #define CLK_SCLK_UART2_PERIC		208
12796bd6224SChanwoo Choi #define CLK_SCLK_UART1_PERIC		209
12896bd6224SChanwoo Choi #define CLK_SCLK_UART0_PERIC		210
12996bd6224SChanwoo Choi #define CLK_SCLK_SPI2_PERIC		211
13096bd6224SChanwoo Choi #define CLK_SCLK_SPI1_PERIC		212
13196bd6224SChanwoo Choi #define CLK_SCLK_SPI0_PERIC		213
13223236496SChanwoo Choi #define CLK_SCLK_SPDIF_PERIC		214
13323236496SChanwoo Choi #define CLK_SCLK_I2S1_PERIC		215
13423236496SChanwoo Choi #define CLK_SCLK_PCM1_PERIC		216
13523236496SChanwoo Choi #define CLK_SCLK_SLIMBUS		217
13623236496SChanwoo Choi #define CLK_SCLK_AUDIO1			218
13723236496SChanwoo Choi #define CLK_SCLK_AUDIO0			219
138a29308daSChanwoo Choi #define CLK_ACLK_G2D_266		220
139a29308daSChanwoo Choi #define CLK_ACLK_G2D_400		221
1405785d6e6SChanwoo Choi #define CLK_ACLK_G3D_400		222
1415785d6e6SChanwoo Choi #define CLK_ACLK_IMEM_SSX_266		223
1425785d6e6SChanwoo Choi #define CLK_ACLK_BUS0_400		224
1435785d6e6SChanwoo Choi #define CLK_ACLK_BUS1_400		225
1445785d6e6SChanwoo Choi #define CLK_ACLK_IMEM_200		226
1455785d6e6SChanwoo Choi #define CLK_ACLK_IMEM_266		227
1464b801355SChanwoo Choi #define CLK_SCLK_PCIE_100_FSYS		228
1474b801355SChanwoo Choi #define CLK_SCLK_UFSUNIPRO_FSYS		229
1484b801355SChanwoo Choi #define CLK_SCLK_USBHOST30_FSYS		230
1494b801355SChanwoo Choi #define CLK_SCLK_USBDRD30_FSYS		231
15096bd6224SChanwoo Choi 
1514b801355SChanwoo Choi #define TOP_NR_CLK			232
15296bd6224SChanwoo Choi 
15396bd6224SChanwoo Choi /* CMU_CPIF */
15496bd6224SChanwoo Choi #define CLK_FOUT_MPHY_PLL		1
15596bd6224SChanwoo Choi 
15696bd6224SChanwoo Choi #define CLK_MOUT_MPHY_PLL		2
15796bd6224SChanwoo Choi 
15896bd6224SChanwoo Choi #define CLK_DIV_SCLK_MPHY		10
15996bd6224SChanwoo Choi 
16096bd6224SChanwoo Choi #define CLK_SCLK_MPHY_PLL		11
16196bd6224SChanwoo Choi #define CLK_SCLK_UFS_MPHY		11
16296bd6224SChanwoo Choi 
16396bd6224SChanwoo Choi #define CPIF_NR_CLK			12
16496bd6224SChanwoo Choi 
16596bd6224SChanwoo Choi /* CMU_MIF */
16696bd6224SChanwoo Choi #define CLK_FOUT_MEM0_PLL		1
16796bd6224SChanwoo Choi #define CLK_FOUT_MEM1_PLL		2
16896bd6224SChanwoo Choi #define CLK_FOUT_BUS_PLL		3
16996bd6224SChanwoo Choi #define CLK_FOUT_MFC_PLL		4
17006d2f9dfSChanwoo Choi #define CLK_DOUT_MFC_PLL		5
17106d2f9dfSChanwoo Choi #define CLK_DOUT_BUS_PLL		6
17206d2f9dfSChanwoo Choi #define CLK_DOUT_MEM1_PLL		7
17306d2f9dfSChanwoo Choi #define CLK_DOUT_MEM0_PLL		8
17496bd6224SChanwoo Choi 
17506d2f9dfSChanwoo Choi #define CLK_MOUT_MFC_PLL_DIV2		10
17606d2f9dfSChanwoo Choi #define CLK_MOUT_BUS_PLL_DIV2		11
17706d2f9dfSChanwoo Choi #define CLK_MOUT_MEM1_PLL_DIV2		12
17806d2f9dfSChanwoo Choi #define CLK_MOUT_MEM0_PLL_DIV2		13
17906d2f9dfSChanwoo Choi #define CLK_MOUT_MFC_PLL		14
18006d2f9dfSChanwoo Choi #define CLK_MOUT_BUS_PLL		15
18106d2f9dfSChanwoo Choi #define CLK_MOUT_MEM1_PLL		16
18206d2f9dfSChanwoo Choi #define CLK_MOUT_MEM0_PLL		17
18306d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_C		18
18406d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_B		19
18506d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_A		20
18606d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_C		21
18706d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_B		22
18806d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_A		23
18906d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_MIFNM_200		24
19006d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_MIFNM_400		25
19106d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_B	26
19206d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_A	27
19306d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_C	28
19406d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_B	29
19506d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_A	30
19606d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_C	31
19706d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_B	32
19806d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_A	33
19906d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_C	34
20006d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_B	35
20106d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_A	36
20206d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_C		37
20306d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_B		38
20406d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_A		39
20506d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_C		40
20606d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_B		41
20706d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_A		42
20806d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_C	46
20906d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_B	47
21006d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_A	48
21106d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_C		49
21206d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_B		50
21306d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_A		51
21406d2f9dfSChanwoo Choi 
21506d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_HPM_MIF		55
21606d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DREX1		56
21706d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DREX0		57
21806d2f9dfSChanwoo Choi #define CLK_DIV_CLK2XPHY		58
21906d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_266		59
22006d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIFND_133		60
22106d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_133		61
22206d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIFNM_200		62
22306d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_200		63
22406d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_400		64
22506d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_BUS2_400		65
22606d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DISP_333		66
22706d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_CPIF_200		67
22806d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSIM1		68
22906d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_VCLK	69
23006d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSIM0		70
23106d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSD		71
23206d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_ECLK	72
23306d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_VCLK		73
23406d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_ECLK		74
23506d2f9dfSChanwoo Choi #define CLK_DIV_MIF_PRE			75
23606d2f9dfSChanwoo Choi 
23706d2f9dfSChanwoo Choi #define CLK_CLK2X_PHY1			80
23806d2f9dfSChanwoo Choi #define CLK_CLK2X_PHY0			81
23906d2f9dfSChanwoo Choi #define CLK_CLKM_PHY1			82
24006d2f9dfSChanwoo Choi #define CLK_CLKM_PHY0			83
24106d2f9dfSChanwoo Choi #define CLK_RCLK_DREX1			84
24206d2f9dfSChanwoo Choi #define CLK_RCLK_DREX0			85
24306d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_TZ		86
24406d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_TZ		87
24506d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_PEREV		88
24606d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_PEREV		89
24706d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_MEMIF		90
24806d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_MEMIF		91
24906d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_SCH		92
25006d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_SCH		93
25106d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_BUSIF		94
25206d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_BUSIF		95
25306d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_BUSIF_RD		96
25406d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_BUSIF_RD		97
25506d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1			98
25606d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0			99
25706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX	100
25806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF	101
25906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF	102
26006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_MIF_IMEM	103
26106d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI	104
26206d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI	105
26306d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_CP1		106
26406d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_CP1		107
26506d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_CP0		108
26606d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_CP0		109
26706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_3	110
26806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_3	111
26906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_1	112
27006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_1	113
27106d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_0	114
27206d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_0	115
27306d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_3	116
27406d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_3	117
27506d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_1	118
27606d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_1	119
27706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_0	120
27806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_0	121
27906d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF2P		122
28006d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF1P		123
28106d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF0P		124
28206d2f9dfSChanwoo Choi #define CLK_ACLK_IXIU_CCI		125
28306d2f9dfSChanwoo Choi #define CLK_ACLK_XIU_MIFSFRX		126
28406d2f9dfSChanwoo Choi #define CLK_ACLK_MIFNP_133		127
28506d2f9dfSChanwoo Choi #define CLK_ACLK_MIFNM_200		128
28606d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_133		129
28706d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_400		130
28806d2f9dfSChanwoo Choi #define CLK_ACLK_CCI			131
28906d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_266		132
29006d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S3		133
29106d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S1		134
29206d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S0		135
29306d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S3		136
29406d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S1		137
29506d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S0		138
29606d2f9dfSChanwoo Choi #define CLK_ACLK_BTS_APOLLO		139
29706d2f9dfSChanwoo Choi #define CLK_ACLK_BTS_ATLAS		140
29806d2f9dfSChanwoo Choi #define CLK_ACLK_ACE_SEL_APOLL		141
29906d2f9dfSChanwoo Choi #define CLK_ACLK_ACE_SEL_ATLAS		142
30006d2f9dfSChanwoo Choi #define CLK_ACLK_AXIDS_CCI_MIFSFRX	143
30106d2f9dfSChanwoo Choi #define CLK_ACLK_AXIUS_ATLAS_CCI	144
30206d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDNS_CCI		145
30306d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDN_CCI		146
30406d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDN_NOC_D	147
30506d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCACEM_APOLLO_CCI	148
30606d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCACEM_ATLAS_CCI	149
30706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS	150
30806d2f9dfSChanwoo Choi #define CLK_ACLK_BUS2_400		151
30906d2f9dfSChanwoo Choi #define CLK_ACLK_DISP_333		152
31006d2f9dfSChanwoo Choi #define CLK_ACLK_CPIF_200		153
31106d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S3		154
31206d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S1		155
31306d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S0		156
31406d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S3		157
31506d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S1		158
31606d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S0		159
31706d2f9dfSChanwoo Choi #define CLK_PCLK_BTS_APOLLO		160
31806d2f9dfSChanwoo Choi #define CLK_PCLK_BTS_ATLAS		161
31906d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_NOC_P_CCI	162
32006d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_CP1		163
32106d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_CP0		164
32206d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_3	165
32306d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_1	166
32406d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_0	167
32506d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_3	168
32606d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_1	169
32706d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_0	170
32806d2f9dfSChanwoo Choi #define CLK_PCLK_MIFSRVND_133		171
32906d2f9dfSChanwoo Choi #define CLK_PCLK_PMU_MIF		172
33006d2f9dfSChanwoo Choi #define CLK_PCLK_SYSREG_MIF		173
33106d2f9dfSChanwoo Choi #define CLK_PCLK_GPIO_ALIVE		174
33206d2f9dfSChanwoo Choi #define CLK_PCLK_ABB			175
33306d2f9dfSChanwoo Choi #define CLK_PCLK_PMU_APBIF		176
33406d2f9dfSChanwoo Choi #define CLK_PCLK_DDR_PHY1		177
33506d2f9dfSChanwoo Choi #define CLK_PCLK_DREX1			178
33606d2f9dfSChanwoo Choi #define CLK_PCLK_DDR_PHY0		179
33706d2f9dfSChanwoo Choi #define CLK_PCLK_DREX0			180
33806d2f9dfSChanwoo Choi #define CLK_PCLK_DREX0_TZ		181
33906d2f9dfSChanwoo Choi #define CLK_PCLK_DREX1_TZ		182
34006d2f9dfSChanwoo Choi #define CLK_PCLK_MONOTONIC_CNT		183
34106d2f9dfSChanwoo Choi #define CLK_PCLK_RTC			184
34206d2f9dfSChanwoo Choi #define CLK_SCLK_DSIM1_DISP		185
34306d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_TV_VCLK_DISP	186
34406d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_BUS_PLL	187
34506d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MFC_PLL	188
34606d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MEM0_PLL	189
34706d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MEM1_PLL	190
34806d2f9dfSChanwoo Choi #define CLK_SCLK_DSIM0_DISP		191
34906d2f9dfSChanwoo Choi #define CLK_SCLK_DSD_DISP		192
35006d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_TV_ECLK_DISP	193
35106d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_VCLK_DISP	194
35206d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_ECLK_DISP	195
35306d2f9dfSChanwoo Choi #define CLK_SCLK_HPM_MIF		196
35406d2f9dfSChanwoo Choi #define CLK_SCLK_MFC_PLL		197
35506d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL		198
35606d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL_APOLLO		199
35706d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL_ATLAS		200
3582a1808a6SChanwoo Choi #define CLK_SCLK_HDMI_SPDIF_DISP	201
35906d2f9dfSChanwoo Choi 
3602a1808a6SChanwoo Choi #define MIF_NR_CLK			202
36196bd6224SChanwoo Choi 
36296bd6224SChanwoo Choi /* CMU_PERIC */
36396bd6224SChanwoo Choi #define CLK_PCLK_SPI2			1
36496bd6224SChanwoo Choi #define CLK_PCLK_SPI1			2
36596bd6224SChanwoo Choi #define CLK_PCLK_SPI0			3
36696bd6224SChanwoo Choi #define CLK_PCLK_UART2			4
36796bd6224SChanwoo Choi #define CLK_PCLK_UART1			5
36896bd6224SChanwoo Choi #define CLK_PCLK_UART0			6
36996bd6224SChanwoo Choi #define CLK_PCLK_HSI2C3			7
37096bd6224SChanwoo Choi #define CLK_PCLK_HSI2C2			8
37196bd6224SChanwoo Choi #define CLK_PCLK_HSI2C1			9
37296bd6224SChanwoo Choi #define CLK_PCLK_HSI2C0			10
37396bd6224SChanwoo Choi #define CLK_PCLK_I2C7			11
37496bd6224SChanwoo Choi #define CLK_PCLK_I2C6			12
37596bd6224SChanwoo Choi #define CLK_PCLK_I2C5			13
37696bd6224SChanwoo Choi #define CLK_PCLK_I2C4			14
37796bd6224SChanwoo Choi #define CLK_PCLK_I2C3			15
37896bd6224SChanwoo Choi #define CLK_PCLK_I2C2			16
37996bd6224SChanwoo Choi #define CLK_PCLK_I2C1			17
38096bd6224SChanwoo Choi #define CLK_PCLK_I2C0			18
38196bd6224SChanwoo Choi #define CLK_PCLK_SPI4			19
38296bd6224SChanwoo Choi #define CLK_PCLK_SPI3			20
38396bd6224SChanwoo Choi #define CLK_PCLK_HSI2C11		21
38496bd6224SChanwoo Choi #define CLK_PCLK_HSI2C10		22
38596bd6224SChanwoo Choi #define CLK_PCLK_HSI2C9			23
38696bd6224SChanwoo Choi #define CLK_PCLK_HSI2C8			24
38796bd6224SChanwoo Choi #define CLK_PCLK_HSI2C7			25
38896bd6224SChanwoo Choi #define CLK_PCLK_HSI2C6			26
38996bd6224SChanwoo Choi #define CLK_PCLK_HSI2C5			27
39096bd6224SChanwoo Choi #define CLK_PCLK_HSI2C4			28
39196bd6224SChanwoo Choi #define CLK_SCLK_SPI4			29
39296bd6224SChanwoo Choi #define CLK_SCLK_SPI3			30
39396bd6224SChanwoo Choi #define CLK_SCLK_SPI2			31
39496bd6224SChanwoo Choi #define CLK_SCLK_SPI1			32
39596bd6224SChanwoo Choi #define CLK_SCLK_SPI0			33
39696bd6224SChanwoo Choi #define CLK_SCLK_UART2			34
39796bd6224SChanwoo Choi #define CLK_SCLK_UART1			35
39896bd6224SChanwoo Choi #define CLK_SCLK_UART0			36
399d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC2P	37
400d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC1P	38
401d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC0P	39
402d0f5de66SChanwoo Choi #define CLK_ACLK_PERICNP_66		40
403d0f5de66SChanwoo Choi #define CLK_PCLK_SCI			41
404d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_FINGER		42
405d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_ESE		43
406d0f5de66SChanwoo Choi #define CLK_PCLK_PWM			44
407d0f5de66SChanwoo Choi #define CLK_PCLK_SPDIF			45
408d0f5de66SChanwoo Choi #define CLK_PCLK_PCM1			46
409d0f5de66SChanwoo Choi #define CLK_PCLK_I2S1			47
410d0f5de66SChanwoo Choi #define CLK_PCLK_ADCIF			48
411d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_TOUCH		49
412d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_NFC		50
413d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_PERIC		51
414d0f5de66SChanwoo Choi #define CLK_PCLK_PMU_PERIC		52
415d0f5de66SChanwoo Choi #define CLK_PCLK_SYSREG_PERIC		53
416d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI4		54
417d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI3		55
418d0f5de66SChanwoo Choi #define CLK_SCLK_SCI			56
419d0f5de66SChanwoo Choi #define CLK_SCLK_SC_IN			57
420d0f5de66SChanwoo Choi #define CLK_SCLK_PWM			58
421d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI2		59
422d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI1		60
423d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI0		61
424d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_I2S1_BCLK	62
425d0f5de66SChanwoo Choi #define CLK_SCLK_SPDIF			63
426d0f5de66SChanwoo Choi #define CLK_SCLK_PCM1			64
427d0f5de66SChanwoo Choi #define CLK_SCLK_I2S1			65
42896bd6224SChanwoo Choi 
429d0f5de66SChanwoo Choi #define CLK_DIV_SCLK_SCI		70
430d0f5de66SChanwoo Choi #define CLK_DIV_SCLK_SC_IN		71
431d0f5de66SChanwoo Choi 
432d0f5de66SChanwoo Choi #define PERIC_NR_CLK			72
43396bd6224SChanwoo Choi 
43496bd6224SChanwoo Choi /* CMU_PERIS */
43596bd6224SChanwoo Choi #define CLK_PCLK_HPM_APBIF		1
43696bd6224SChanwoo Choi #define CLK_PCLK_TMU1_APBIF		2
43796bd6224SChanwoo Choi #define CLK_PCLK_TMU0_APBIF		3
43896bd6224SChanwoo Choi #define CLK_PCLK_PMU_PERIS		4
43996bd6224SChanwoo Choi #define CLK_PCLK_SYSREG_PERIS		5
44096bd6224SChanwoo Choi #define CLK_PCLK_CMU_TOP_APBIF		6
44196bd6224SChanwoo Choi #define CLK_PCLK_WDT_APOLLO		7
44296bd6224SChanwoo Choi #define CLK_PCLK_WDT_ATLAS		8
44396bd6224SChanwoo Choi #define CLK_PCLK_MCT			9
44496bd6224SChanwoo Choi #define CLK_PCLK_HDMI_CEC		10
44556bcf3f3SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIS1P	11
44656bcf3f3SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIS0P	12
44756bcf3f3SChanwoo Choi #define CLK_ACLK_PERISNP_66		13
44856bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC12			14
44956bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC11			15
45056bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC10			16
45156bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC9			17
45256bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC8			18
45356bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC7			19
45456bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC6			20
45556bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC5			21
45656bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC4			22
45756bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC3			23
45856bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC2			24
45956bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC1			25
46056bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC0			26
46156bcf3f3SChanwoo Choi #define CLK_PCLK_SECKEY_APBIF		27
46256bcf3f3SChanwoo Choi #define CLK_PCLK_CHIPID_APBIF		28
46356bcf3f3SChanwoo Choi #define CLK_PCLK_TOPRTC			29
46456bcf3f3SChanwoo Choi #define CLK_PCLK_CUSTOM_EFUSE_APBIF	30
46556bcf3f3SChanwoo Choi #define CLK_PCLK_ANTIRBK_CNT_APBIF	31
46656bcf3f3SChanwoo Choi #define CLK_PCLK_OTP_CON_APBIF		32
46756bcf3f3SChanwoo Choi #define CLK_SCLK_ASV_TB			33
46856bcf3f3SChanwoo Choi #define CLK_SCLK_TMU1			34
46956bcf3f3SChanwoo Choi #define CLK_SCLK_TMU0			35
47056bcf3f3SChanwoo Choi #define CLK_SCLK_SECKEY			36
47156bcf3f3SChanwoo Choi #define CLK_SCLK_CHIPID			37
47256bcf3f3SChanwoo Choi #define CLK_SCLK_TOPRTC			38
47356bcf3f3SChanwoo Choi #define CLK_SCLK_CUSTOM_EFUSE		39
47456bcf3f3SChanwoo Choi #define CLK_SCLK_ANTIRBK_CNT		40
47556bcf3f3SChanwoo Choi #define CLK_SCLK_OTP_CON		41
47696bd6224SChanwoo Choi 
47756bcf3f3SChanwoo Choi #define PERIS_NR_CLK			42
47896bd6224SChanwoo Choi 
47996bd6224SChanwoo Choi /* CMU_FSYS */
48096bd6224SChanwoo Choi #define CLK_MOUT_ACLK_FSYS_200_USER	1
48196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_USER		2
48296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_USER		3
48396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_USER		4
4844b801355SChanwoo Choi #define CLK_MOUT_SCLK_UFS_MPHY_USER	5
4854b801355SChanwoo Choi #define CLK_MOUT_SCLK_PCIE_100_USER	6
4864b801355SChanwoo Choi #define CLK_MOUT_SCLK_UFSUNIPRO_USER	7
4874b801355SChanwoo Choi #define CLK_MOUT_SCLK_USBHOST30_USER	8
4884b801355SChanwoo Choi #define CLK_MOUT_SCLK_USBDRD30_USER	9
4894b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER	10
4904b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER		11
4914b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER		12
4924b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER		13
4934b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER		14
4944b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER		15
4954b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER		16
4964b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER		17
4974b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER			18
4984b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER			19
4994b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER			20
5004b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER			21
5014b801355SChanwoo Choi #define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER			22
5024b801355SChanwoo Choi #define CLK_MOUT_SCLK_MPHY					23
5034b801355SChanwoo Choi 
5044b801355SChanwoo Choi #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY			25
5054b801355SChanwoo Choi #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY		26
5064b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY		27
5074b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY		28
5084b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY			29
5094b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY			30
5104b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY			31
5114b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY			32
5124b801355SChanwoo Choi #define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY				33
5134b801355SChanwoo Choi #define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY				34
5144b801355SChanwoo Choi #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY				35
5154b801355SChanwoo Choi #define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY				36
5164b801355SChanwoo Choi #define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY				37
51796bd6224SChanwoo Choi 
51896bd6224SChanwoo Choi #define CLK_ACLK_PCIE			50
51996bd6224SChanwoo Choi #define CLK_ACLK_PDMA1			51
52096bd6224SChanwoo Choi #define CLK_ACLK_TSI			52
52196bd6224SChanwoo Choi #define CLK_ACLK_MMC2			53
52296bd6224SChanwoo Choi #define CLK_ACLK_MMC1			54
52396bd6224SChanwoo Choi #define CLK_ACLK_MMC0			55
52496bd6224SChanwoo Choi #define CLK_ACLK_UFS			56
52596bd6224SChanwoo Choi #define CLK_ACLK_USBHOST20		57
52696bd6224SChanwoo Choi #define CLK_ACLK_USBHOST30		58
52796bd6224SChanwoo Choi #define CLK_ACLK_USBDRD30		59
52896bd6224SChanwoo Choi #define CLK_ACLK_PDMA0			60
52996bd6224SChanwoo Choi #define CLK_SCLK_MMC2			61
53096bd6224SChanwoo Choi #define CLK_SCLK_MMC1			62
53196bd6224SChanwoo Choi #define CLK_SCLK_MMC0			63
53296bd6224SChanwoo Choi #define CLK_PDMA1			64
53396bd6224SChanwoo Choi #define CLK_PDMA0			65
5344b801355SChanwoo Choi #define CLK_ACLK_XIU_FSYSPX		66
5354b801355SChanwoo Choi #define CLK_ACLK_AHB_USBLINKH1		67
5364b801355SChanwoo Choi #define CLK_ACLK_SMMU_PDMA1		68
5374b801355SChanwoo Choi #define CLK_ACLK_BTS_PCIE		69
5384b801355SChanwoo Choi #define CLK_ACLK_AXIUS_PDMA1		70
5394b801355SChanwoo Choi #define CLK_ACLK_SMMU_PDMA0		71
5404b801355SChanwoo Choi #define CLK_ACLK_BTS_UFS		72
5414b801355SChanwoo Choi #define CLK_ACLK_BTS_USBHOST30		73
5424b801355SChanwoo Choi #define CLK_ACLK_BTS_USBDRD30		74
5434b801355SChanwoo Choi #define CLK_ACLK_AXIUS_PDMA0		75
5444b801355SChanwoo Choi #define CLK_ACLK_AXIUS_USBHS		76
5454b801355SChanwoo Choi #define CLK_ACLK_AXIUS_FSYSSX		77
5464b801355SChanwoo Choi #define CLK_ACLK_AHB2APB_FSYSP		78
5474b801355SChanwoo Choi #define CLK_ACLK_AHB2AXI_USBHS		79
5484b801355SChanwoo Choi #define CLK_ACLK_AHB_USBLINKH0		80
5494b801355SChanwoo Choi #define CLK_ACLK_AHB_USBHS		81
5504b801355SChanwoo Choi #define CLK_ACLK_AHB_FSYSH		82
5514b801355SChanwoo Choi #define CLK_ACLK_XIU_FSYSX		83
5524b801355SChanwoo Choi #define CLK_ACLK_XIU_FSYSSX		84
5534b801355SChanwoo Choi #define CLK_ACLK_FSYSNP_200		85
5544b801355SChanwoo Choi #define CLK_ACLK_FSYSND_200		86
5554b801355SChanwoo Choi #define CLK_PCLK_PCIE_CTRL		87
5564b801355SChanwoo Choi #define CLK_PCLK_SMMU_PDMA1		88
5574b801355SChanwoo Choi #define CLK_PCLK_PCIE_PHY		89
5584b801355SChanwoo Choi #define CLK_PCLK_BTS_PCIE		90
5594b801355SChanwoo Choi #define CLK_PCLK_SMMU_PDMA0		91
5604b801355SChanwoo Choi #define CLK_PCLK_BTS_UFS		92
5614b801355SChanwoo Choi #define CLK_PCLK_BTS_USBHOST30		93
5624b801355SChanwoo Choi #define CLK_PCLK_BTS_USBDRD30		94
5634b801355SChanwoo Choi #define CLK_PCLK_GPIO_FSYS		95
5644b801355SChanwoo Choi #define CLK_PCLK_PMU_FSYS		96
5654b801355SChanwoo Choi #define CLK_PCLK_SYSREG_FSYS		97
5664b801355SChanwoo Choi #define CLK_SCLK_PCIE_100		98
5674b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK	99
5684b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK	100
5694b801355SChanwoo Choi #define CLK_PHYCLK_UFS_RX1_SYMBOL		101
5704b801355SChanwoo Choi #define CLK_PHYCLK_UFS_RX0_SYMBOL		102
5714b801355SChanwoo Choi #define CLK_PHYCLK_UFS_TX1_SYMBOL		103
5724b801355SChanwoo Choi #define CLK_PHYCLK_UFS_TX0_SYMBOL		104
5734b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_HSIC1		105
5744b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI	106
5754b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK	107
5764b801355SChanwoo Choi #define CLK_PHYCLK_USBHOST20_PHY_FREECLK	108
5774b801355SChanwoo Choi #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK	109
5784b801355SChanwoo Choi #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK	110
5794b801355SChanwoo Choi #define CLK_SCLK_MPHY			111
5804b801355SChanwoo Choi #define CLK_SCLK_UFSUNIPRO		112
5814b801355SChanwoo Choi #define CLK_SCLK_USBHOST30		113
5824b801355SChanwoo Choi #define CLK_SCLK_USBDRD30		114
58396bd6224SChanwoo Choi 
5844b801355SChanwoo Choi #define FSYS_NR_CLK			115
58596bd6224SChanwoo Choi 
586a29308daSChanwoo Choi /* CMU_G2D */
587a29308daSChanwoo Choi #define CLK_MUX_ACLK_G2D_266_USER	1
588a29308daSChanwoo Choi #define CLK_MUX_ACLK_G2D_400_USER	2
589a29308daSChanwoo Choi 
590a29308daSChanwoo Choi #define CLK_DIV_PCLK_G2D		3
591a29308daSChanwoo Choi 
592a29308daSChanwoo Choi #define CLK_ACLK_SMMU_MDMA1		4
593a29308daSChanwoo Choi #define CLK_ACLK_BTS_MDMA1		5
594a29308daSChanwoo Choi #define CLK_ACLK_BTS_G2D		6
595a29308daSChanwoo Choi #define CLK_ACLK_ALB_G2D		7
596a29308daSChanwoo Choi #define CLK_ACLK_AXIUS_G2DX		8
597a29308daSChanwoo Choi #define CLK_ACLK_ASYNCAXI_SYSX		9
598a29308daSChanwoo Choi #define CLK_ACLK_AHB2APB_G2D1P		10
599a29308daSChanwoo Choi #define CLK_ACLK_AHB2APB_G2D0P		11
600a29308daSChanwoo Choi #define CLK_ACLK_XIU_G2DX		12
601a29308daSChanwoo Choi #define CLK_ACLK_G2DNP_133		13
602a29308daSChanwoo Choi #define CLK_ACLK_G2DND_400		14
603a29308daSChanwoo Choi #define CLK_ACLK_MDMA1			15
604a29308daSChanwoo Choi #define CLK_ACLK_G2D			16
605a29308daSChanwoo Choi #define CLK_ACLK_SMMU_G2D		17
606a29308daSChanwoo Choi #define CLK_PCLK_SMMU_MDMA1		18
607a29308daSChanwoo Choi #define CLK_PCLK_BTS_MDMA1		19
608a29308daSChanwoo Choi #define CLK_PCLK_BTS_G2D		20
609a29308daSChanwoo Choi #define CLK_PCLK_ALB_G2D		21
610a29308daSChanwoo Choi #define CLK_PCLK_ASYNCAXI_SYSX		22
611a29308daSChanwoo Choi #define CLK_PCLK_PMU_G2D		23
612a29308daSChanwoo Choi #define CLK_PCLK_SYSREG_G2D		24
613a29308daSChanwoo Choi #define CLK_PCLK_G2D			25
614a29308daSChanwoo Choi #define CLK_PCLK_SMMU_G2D		26
615a29308daSChanwoo Choi 
616a29308daSChanwoo Choi #define G2D_NR_CLK			27
617a29308daSChanwoo Choi 
6182a1808a6SChanwoo Choi /* CMU_DISP */
6192a1808a6SChanwoo Choi #define CLK_FOUT_DISP_PLL				1
6202a1808a6SChanwoo Choi 
6212a1808a6SChanwoo Choi #define CLK_MOUT_DISP_PLL				2
6222a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_USER			3
6232a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_USER			4
6242a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSD_USER				5
6252a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_USER		6
6262a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_USER			7
6272a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_USER			8
6282a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_USER		9
6292a1808a6SChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_USER			10
6302a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER	11
6312a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER	12
6322a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER	13
6332a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER	14
6342a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER		15
6352a1808a6SChanwoo Choi #define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER		16
6362a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM0				17
6372a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK			18
6382a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK			19
6392a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK			20
6402a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_B_DISP			21
6412a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_A_DISP			22
6422a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP		23
6432a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP		24
6442a1808a6SChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP		25
6452a1808a6SChanwoo Choi 
6462a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DSIM1_DISP				30
6472a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_VCLK_DISP			31
6482a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DSIM0_DISP				32
6492a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_ECLK_DISP			33
6502a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_VCLK_DISP			34
6512a1808a6SChanwoo Choi #define CLK_DIV_SCLK_DECON_ECLK_DISP			35
6522a1808a6SChanwoo Choi #define CLK_DIV_PCLK_DISP				36
6532a1808a6SChanwoo Choi 
6542a1808a6SChanwoo Choi #define CLK_ACLK_DECON_TV				40
6552a1808a6SChanwoo Choi #define CLK_ACLK_DECON					41
6562a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_TV1X				42
6572a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_TV0X				43
6582a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_DECON1X				44
6592a1808a6SChanwoo Choi #define CLK_ACLK_SMMU_DECON0X				45
6602a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M3			46
6612a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M2			47
6622a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M1			48
6632a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_TV_M0			49
6642a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM4				50
6652a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM3				51
6662a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM2				52
6672a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM1				53
6682a1808a6SChanwoo Choi #define CLK_ACLK_BTS_DECON_NM0				54
6692a1808a6SChanwoo Choi #define CLK_ACLK_AHB2APB_DISPSFR2P			55
6702a1808a6SChanwoo Choi #define CLK_ACLK_AHB2APB_DISPSFR1P			56
6712a1808a6SChanwoo Choi #define CLK_ACLK_AHB2APB_DISPSFR0P			57
6722a1808a6SChanwoo Choi #define CLK_ACLK_AHB_DISPH				58
6732a1808a6SChanwoo Choi #define CLK_ACLK_XIU_TV1X				59
6742a1808a6SChanwoo Choi #define CLK_ACLK_XIU_TV0X				60
6752a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DECON1X				61
6762a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DECON0X				62
6772a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DISP1X				63
6782a1808a6SChanwoo Choi #define CLK_ACLK_XIU_DISPNP_100				64
6792a1808a6SChanwoo Choi #define CLK_ACLK_DISP1ND_333				65
6802a1808a6SChanwoo Choi #define CLK_ACLK_DISP0ND_333				66
6812a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_TV1X				67
6822a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_TV0X				68
6832a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_DECON1X				69
6842a1808a6SChanwoo Choi #define CLK_PCLK_SMMU_DECON0X				70
6852a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M3			71
6862a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M2			72
6872a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M1			73
6882a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECON_TV_M0			74
6892a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM4				75
6902a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM3				76
6912a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM2				77
6922a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM1				78
6932a1808a6SChanwoo Choi #define CLK_PCLK_BTS_DECONM0				79
6942a1808a6SChanwoo Choi #define CLK_PCLK_MIC1					80
6952a1808a6SChanwoo Choi #define CLK_PCLK_PMU_DISP				81
6962a1808a6SChanwoo Choi #define CLK_PCLK_SYSREG_DISP				82
6972a1808a6SChanwoo Choi #define CLK_PCLK_HDMIPHY				83
6982a1808a6SChanwoo Choi #define CLK_PCLK_HDMI					84
6992a1808a6SChanwoo Choi #define CLK_PCLK_MIC0					85
7002a1808a6SChanwoo Choi #define CLK_PCLK_DSIM1					86
7012a1808a6SChanwoo Choi #define CLK_PCLK_DSIM0					87
7022a1808a6SChanwoo Choi #define CLK_PCLK_DECON_TV				88
7032a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8			89
7042a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0			90
7052a1808a6SChanwoo Choi #define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1			91
7062a1808a6SChanwoo Choi #define CLK_SCLK_RGB_TV_VCLK_TO_MIC1			92
7072a1808a6SChanwoo Choi #define CLK_SCLK_DSIM1					93
7082a1808a6SChanwoo Choi #define CLK_SCLK_DECON_TV_VCLK				94
7092a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8			95
7102a1808a6SChanwoo Choi #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0			96
7112a1808a6SChanwoo Choi #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO			97
7122a1808a6SChanwoo Choi #define CLK_PHYCLK_HDMI_PIXEL				98
7132a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK_TO_SMIES			99
7142a1808a6SChanwoo Choi #define CLK_SCLK_FREQ_DET_DISP_PLL			100
7152a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK_TO_DSIM0			101
7162a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK_TO_MIC0			102
7172a1808a6SChanwoo Choi #define CLK_SCLK_DSD					103
7182a1808a6SChanwoo Choi #define CLK_SCLK_HDMI_SPDIF				104
7192a1808a6SChanwoo Choi #define CLK_SCLK_DSIM0					105
7202a1808a6SChanwoo Choi #define CLK_SCLK_DECON_TV_ECLK				106
7212a1808a6SChanwoo Choi #define CLK_SCLK_DECON_VCLK				107
7222a1808a6SChanwoo Choi #define CLK_SCLK_DECON_ECLK				108
7232a1808a6SChanwoo Choi #define CLK_SCLK_RGB_VCLK				109
7242a1808a6SChanwoo Choi #define CLK_SCLK_RGB_TV_VCLK				110
7252a1808a6SChanwoo Choi 
7262a1808a6SChanwoo Choi #define DISP_NR_CLK					111
7272a1808a6SChanwoo Choi 
7282e997c03SChanwoo Choi /* CMU_AUD */
7292e997c03SChanwoo Choi #define CLK_MOUT_AUD_PLL_USER				1
7302e997c03SChanwoo Choi #define CLK_MOUT_SCLK_AUD_PCM				2
7312e997c03SChanwoo Choi #define CLK_MOUT_SCLK_AUD_I2S				3
7322e997c03SChanwoo Choi 
7332e997c03SChanwoo Choi #define CLK_DIV_ATCLK_AUD				4
7342e997c03SChanwoo Choi #define CLK_DIV_PCLK_DBG_AUD				5
7352e997c03SChanwoo Choi #define CLK_DIV_ACLK_AUD				6
7362e997c03SChanwoo Choi #define CLK_DIV_AUD_CA5					7
7372e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_SLIMBUS			8
7382e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_UART				9
7392e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_PCM				10
7402e997c03SChanwoo Choi #define CLK_DIV_SCLK_AUD_I2S				11
7412e997c03SChanwoo Choi 
7422e997c03SChanwoo Choi #define CLK_ACLK_INTR_CTRL				12
7432e997c03SChanwoo Choi #define CLK_ACLK_AXIDS2_LPASSP				13
7442e997c03SChanwoo Choi #define CLK_ACLK_AXIDS1_LPASSP				14
7452e997c03SChanwoo Choi #define CLK_ACLK_AXI2APB1_LPASSP			15
7462e997c03SChanwoo Choi #define CLK_ACLK_AXI2APH_LPASSP				16
7472e997c03SChanwoo Choi #define CLK_ACLK_SMMU_LPASSX				17
7482e997c03SChanwoo Choi #define CLK_ACLK_AXIDS0_LPASSP				18
7492e997c03SChanwoo Choi #define CLK_ACLK_AXI2APB0_LPASSP			19
7502e997c03SChanwoo Choi #define CLK_ACLK_XIU_LPASSX				20
7512e997c03SChanwoo Choi #define CLK_ACLK_AUDNP_133				21
7522e997c03SChanwoo Choi #define CLK_ACLK_AUDND_133				22
7532e997c03SChanwoo Choi #define CLK_ACLK_SRAMC					23
7542e997c03SChanwoo Choi #define CLK_ACLK_DMAC					24
7552e997c03SChanwoo Choi #define CLK_PCLK_WDT1					25
7562e997c03SChanwoo Choi #define CLK_PCLK_WDT0					26
7572e997c03SChanwoo Choi #define CLK_PCLK_SFR1					27
7582e997c03SChanwoo Choi #define CLK_PCLK_SMMU_LPASSX				28
7592e997c03SChanwoo Choi #define CLK_PCLK_GPIO_AUD				29
7602e997c03SChanwoo Choi #define CLK_PCLK_PMU_AUD				30
7612e997c03SChanwoo Choi #define CLK_PCLK_SYSREG_AUD				31
7622e997c03SChanwoo Choi #define CLK_PCLK_AUD_SLIMBUS				32
7632e997c03SChanwoo Choi #define CLK_PCLK_AUD_UART				33
7642e997c03SChanwoo Choi #define CLK_PCLK_AUD_PCM				34
7652e997c03SChanwoo Choi #define CLK_PCLK_AUD_I2S				35
7662e997c03SChanwoo Choi #define CLK_PCLK_TIMER					36
7672e997c03SChanwoo Choi #define CLK_PCLK_SFR0_CTRL				37
7682e997c03SChanwoo Choi #define CLK_ATCLK_AUD					38
7692e997c03SChanwoo Choi #define CLK_PCLK_DBG_AUD				39
7702e997c03SChanwoo Choi #define CLK_SCLK_AUD_CA5				40
7712e997c03SChanwoo Choi #define CLK_SCLK_JTAG_TCK				41
7722e997c03SChanwoo Choi #define CLK_SCLK_SLIMBUS_CLKIN				42
7732e997c03SChanwoo Choi #define CLK_SCLK_AUD_SLIMBUS				43
7742e997c03SChanwoo Choi #define CLK_SCLK_AUD_UART				44
7752e997c03SChanwoo Choi #define CLK_SCLK_AUD_PCM				45
7762e997c03SChanwoo Choi #define CLK_SCLK_I2S_BCLK				46
7772e997c03SChanwoo Choi #define CLK_SCLK_AUD_I2S				47
7782e997c03SChanwoo Choi 
7792e997c03SChanwoo Choi #define AUD_NR_CLK					48
7802e997c03SChanwoo Choi 
7815785d6e6SChanwoo Choi /* CMU_BUS{0|1|2} */
7825785d6e6SChanwoo Choi #define CLK_DIV_PCLK_BUS_133				1
7835785d6e6SChanwoo Choi 
7845785d6e6SChanwoo Choi #define CLK_ACLK_AHB2APB_BUSP				2
7855785d6e6SChanwoo Choi #define CLK_ACLK_BUSNP_133				3
7865785d6e6SChanwoo Choi #define CLK_ACLK_BUSND_400				4
7875785d6e6SChanwoo Choi #define CLK_PCLK_BUSSRVND_133				5
7885785d6e6SChanwoo Choi #define CLK_PCLK_PMU_BUS				6
7895785d6e6SChanwoo Choi #define CLK_PCLK_SYSREG_BUS				7
7905785d6e6SChanwoo Choi 
7915785d6e6SChanwoo Choi #define CLK_MOUT_ACLK_BUS2_400_USER			8  /* Only CMU_BUS2 */
7925785d6e6SChanwoo Choi #define CLK_ACLK_BUS2BEND_400				9  /* Only CMU_BUS2 */
7935785d6e6SChanwoo Choi #define CLK_ACLK_BUS2RTND_400				10 /* Only CMU_BUS2 */
7945785d6e6SChanwoo Choi 
7955785d6e6SChanwoo Choi #define BUSx_NR_CLK					11
7965785d6e6SChanwoo Choi 
797453e519eSChanwoo Choi /* CMU_G3D */
798453e519eSChanwoo Choi #define CLK_FOUT_G3D_PLL				1
799453e519eSChanwoo Choi 
800453e519eSChanwoo Choi #define CLK_MOUT_ACLK_G3D_400				2
801453e519eSChanwoo Choi #define CLK_MOUT_G3D_PLL				3
802453e519eSChanwoo Choi 
803453e519eSChanwoo Choi #define CLK_DIV_SCLK_HPM_G3D				4
804453e519eSChanwoo Choi #define CLK_DIV_PCLK_G3D				5
805453e519eSChanwoo Choi #define CLK_DIV_ACLK_G3D				6
806453e519eSChanwoo Choi #define CLK_ACLK_BTS_G3D1				7
807453e519eSChanwoo Choi #define CLK_ACLK_BTS_G3D0				8
808453e519eSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_G3D				9
809453e519eSChanwoo Choi #define CLK_ACLK_ASYNCAPBM_G3D				10
810453e519eSChanwoo Choi #define CLK_ACLK_AHB2APB_G3DP				11
811453e519eSChanwoo Choi #define CLK_ACLK_G3DNP_150				12
812453e519eSChanwoo Choi #define CLK_ACLK_G3DND_600				13
813453e519eSChanwoo Choi #define CLK_ACLK_G3D					14
814453e519eSChanwoo Choi #define CLK_PCLK_BTS_G3D1				15
815453e519eSChanwoo Choi #define CLK_PCLK_BTS_G3D0				16
816453e519eSChanwoo Choi #define CLK_PCLK_PMU_G3D				17
817453e519eSChanwoo Choi #define CLK_PCLK_SYSREG_G3D				18
818453e519eSChanwoo Choi #define CLK_SCLK_HPM_G3D				19
819453e519eSChanwoo Choi 
820453e519eSChanwoo Choi #define G3D_NR_CLK					20
821453e519eSChanwoo Choi 
82296bd6224SChanwoo Choi #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
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