196bd6224SChanwoo Choi /* 296bd6224SChanwoo Choi * Copyright (c) 2014 Samsung Electronics Co., Ltd. 396bd6224SChanwoo Choi * Author: Chanwoo Choi <cw00.choi@samsung.com> 496bd6224SChanwoo Choi * 596bd6224SChanwoo Choi * This program is free software; you can redistribute it and/or modify 696bd6224SChanwoo Choi * it under the terms of the GNU General Public License version 2 as 796bd6224SChanwoo Choi * published by the Free Software Foundation. 896bd6224SChanwoo Choi */ 996bd6224SChanwoo Choi 1096bd6224SChanwoo Choi #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 1196bd6224SChanwoo Choi #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 1296bd6224SChanwoo Choi 1396bd6224SChanwoo Choi /* CMU_TOP */ 1496bd6224SChanwoo Choi #define CLK_FOUT_ISP_PLL 1 1596bd6224SChanwoo Choi #define CLK_FOUT_AUD_PLL 2 1696bd6224SChanwoo Choi 1796bd6224SChanwoo Choi #define CLK_MOUT_AUD_PLL 10 1896bd6224SChanwoo Choi #define CLK_MOUT_ISP_PLL 11 1996bd6224SChanwoo Choi #define CLK_MOUT_AUD_PLL_USER_T 12 2096bd6224SChanwoo Choi #define CLK_MOUT_MPHY_PLL_USER 13 2196bd6224SChanwoo Choi #define CLK_MOUT_MFC_PLL_USER 14 2296bd6224SChanwoo Choi #define CLK_MOUT_BUS_PLL_USER 15 2396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_HEVC_400 16 2496bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_333 17 2596bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_B 18 2696bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_A 19 2796bd6224SChanwoo Choi #define CLK_MOUT_ACLK_ISP_DIS_400 20 2896bd6224SChanwoo Choi #define CLK_MOUT_ACLK_ISP_400 21 2996bd6224SChanwoo Choi #define CLK_MOUT_ACLK_BUS0_400 22 3096bd6224SChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_B 23 3196bd6224SChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_A 24 3296bd6224SChanwoo Choi #define CLK_MOUT_ACLK_GSCL_333 25 3396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_G2D_400_B 26 3496bd6224SChanwoo Choi #define CLK_MOUT_ACLK_G2D_400_A 27 3596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_C 28 3696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_B 29 3796bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_A 30 3896bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_B 31 3996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_A 32 4096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_B 33 4196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_A 34 4296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_D 35 4396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_C 36 4496bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_B 37 4596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_A 38 4696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI4 39 4796bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI3 40 4896bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART2 41 4996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART1 42 5096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART0 43 5196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI2 44 5296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI1 45 5396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI0 46 5423236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_C 47 5523236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_B 48 5623236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_A 49 5723236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR2 50 5823236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR1 51 5923236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR0 52 6023236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_UART 53 6123236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI1 54 6223236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI0 55 6323236496SChanwoo Choi #define CLK_MOUT_SCLK_PCIE_100 56 6423236496SChanwoo Choi #define CLK_MOUT_SCLK_UFSUNIPRO 57 6523236496SChanwoo Choi #define CLK_MOUT_SCLK_USBHOST30 58 6623236496SChanwoo Choi #define CLK_MOUT_SCLK_USBDRD30 59 6723236496SChanwoo Choi #define CLK_MOUT_SCLK_SLIMBUS 60 6823236496SChanwoo Choi #define CLK_MOUT_SCLK_SPDIF 61 6923236496SChanwoo Choi #define CLK_MOUT_SCLK_AUDIO1 62 7023236496SChanwoo Choi #define CLK_MOUT_SCLK_AUDIO0 63 7196bd6224SChanwoo Choi 7296bd6224SChanwoo Choi #define CLK_DIV_ACLK_FSYS_200 100 7396bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_SSSX_266 101 7496bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_200 102 7596bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_266 103 7696bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIC_66_B 104 7796bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIC_66_A 105 7896bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIS_66_B 106 7996bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIS_66_A 107 8096bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC1_B 108 8196bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC1_A 109 8296bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC0_B 110 8396bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC0_A 111 8496bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC2_B 112 8596bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC2_A 113 8696bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI1_B 114 8796bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI1_A 115 8896bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI0_B 116 8996bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI0_A 117 9096bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI2_B 118 9196bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI2_A 119 9296bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART2 120 9396bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART1 121 9496bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART0 122 9596bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI4_B 123 9696bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI4_A 124 9796bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI3_B 125 9896bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI3_A 126 9923236496SChanwoo Choi #define CLK_DIV_SCLK_I2S1 127 10023236496SChanwoo Choi #define CLK_DIV_SCLK_PCM1 128 10123236496SChanwoo Choi #define CLK_DIV_SCLK_AUDIO1 129 10223236496SChanwoo Choi #define CLK_DIV_SCLK_AUDIO0 130 10396bd6224SChanwoo Choi 10496bd6224SChanwoo Choi #define CLK_ACLK_PERIC_66 200 10596bd6224SChanwoo Choi #define CLK_ACLK_PERIS_66 201 10696bd6224SChanwoo Choi #define CLK_ACLK_FSYS_200 202 10796bd6224SChanwoo Choi #define CLK_SCLK_MMC2_FSYS 203 10896bd6224SChanwoo Choi #define CLK_SCLK_MMC1_FSYS 204 10996bd6224SChanwoo Choi #define CLK_SCLK_MMC0_FSYS 205 11096bd6224SChanwoo Choi #define CLK_SCLK_SPI4_PERIC 206 11196bd6224SChanwoo Choi #define CLK_SCLK_SPI3_PERIC 207 11296bd6224SChanwoo Choi #define CLK_SCLK_UART2_PERIC 208 11396bd6224SChanwoo Choi #define CLK_SCLK_UART1_PERIC 209 11496bd6224SChanwoo Choi #define CLK_SCLK_UART0_PERIC 210 11596bd6224SChanwoo Choi #define CLK_SCLK_SPI2_PERIC 211 11696bd6224SChanwoo Choi #define CLK_SCLK_SPI1_PERIC 212 11796bd6224SChanwoo Choi #define CLK_SCLK_SPI0_PERIC 213 11823236496SChanwoo Choi #define CLK_SCLK_SPDIF_PERIC 214 11923236496SChanwoo Choi #define CLK_SCLK_I2S1_PERIC 215 12023236496SChanwoo Choi #define CLK_SCLK_PCM1_PERIC 216 12123236496SChanwoo Choi #define CLK_SCLK_SLIMBUS 217 12223236496SChanwoo Choi #define CLK_SCLK_AUDIO1 218 12323236496SChanwoo Choi #define CLK_SCLK_AUDIO0 219 12496bd6224SChanwoo Choi 12523236496SChanwoo Choi #define TOP_NR_CLK 220 12696bd6224SChanwoo Choi 12796bd6224SChanwoo Choi /* CMU_CPIF */ 12896bd6224SChanwoo Choi #define CLK_FOUT_MPHY_PLL 1 12996bd6224SChanwoo Choi 13096bd6224SChanwoo Choi #define CLK_MOUT_MPHY_PLL 2 13196bd6224SChanwoo Choi 13296bd6224SChanwoo Choi #define CLK_DIV_SCLK_MPHY 10 13396bd6224SChanwoo Choi 13496bd6224SChanwoo Choi #define CLK_SCLK_MPHY_PLL 11 13596bd6224SChanwoo Choi #define CLK_SCLK_UFS_MPHY 11 13696bd6224SChanwoo Choi 13796bd6224SChanwoo Choi #define CPIF_NR_CLK 12 13896bd6224SChanwoo Choi 13996bd6224SChanwoo Choi /* CMU_MIF */ 14096bd6224SChanwoo Choi #define CLK_FOUT_MEM0_PLL 1 14196bd6224SChanwoo Choi #define CLK_FOUT_MEM1_PLL 2 14296bd6224SChanwoo Choi #define CLK_FOUT_BUS_PLL 3 14396bd6224SChanwoo Choi #define CLK_FOUT_MFC_PLL 4 14496bd6224SChanwoo Choi 14596bd6224SChanwoo Choi #define MIF_NR_CLK 5 14696bd6224SChanwoo Choi 14796bd6224SChanwoo Choi /* CMU_PERIC */ 14896bd6224SChanwoo Choi #define CLK_PCLK_SPI2 1 14996bd6224SChanwoo Choi #define CLK_PCLK_SPI1 2 15096bd6224SChanwoo Choi #define CLK_PCLK_SPI0 3 15196bd6224SChanwoo Choi #define CLK_PCLK_UART2 4 15296bd6224SChanwoo Choi #define CLK_PCLK_UART1 5 15396bd6224SChanwoo Choi #define CLK_PCLK_UART0 6 15496bd6224SChanwoo Choi #define CLK_PCLK_HSI2C3 7 15596bd6224SChanwoo Choi #define CLK_PCLK_HSI2C2 8 15696bd6224SChanwoo Choi #define CLK_PCLK_HSI2C1 9 15796bd6224SChanwoo Choi #define CLK_PCLK_HSI2C0 10 15896bd6224SChanwoo Choi #define CLK_PCLK_I2C7 11 15996bd6224SChanwoo Choi #define CLK_PCLK_I2C6 12 16096bd6224SChanwoo Choi #define CLK_PCLK_I2C5 13 16196bd6224SChanwoo Choi #define CLK_PCLK_I2C4 14 16296bd6224SChanwoo Choi #define CLK_PCLK_I2C3 15 16396bd6224SChanwoo Choi #define CLK_PCLK_I2C2 16 16496bd6224SChanwoo Choi #define CLK_PCLK_I2C1 17 16596bd6224SChanwoo Choi #define CLK_PCLK_I2C0 18 16696bd6224SChanwoo Choi #define CLK_PCLK_SPI4 19 16796bd6224SChanwoo Choi #define CLK_PCLK_SPI3 20 16896bd6224SChanwoo Choi #define CLK_PCLK_HSI2C11 21 16996bd6224SChanwoo Choi #define CLK_PCLK_HSI2C10 22 17096bd6224SChanwoo Choi #define CLK_PCLK_HSI2C9 23 17196bd6224SChanwoo Choi #define CLK_PCLK_HSI2C8 24 17296bd6224SChanwoo Choi #define CLK_PCLK_HSI2C7 25 17396bd6224SChanwoo Choi #define CLK_PCLK_HSI2C6 26 17496bd6224SChanwoo Choi #define CLK_PCLK_HSI2C5 27 17596bd6224SChanwoo Choi #define CLK_PCLK_HSI2C4 28 17696bd6224SChanwoo Choi #define CLK_SCLK_SPI4 29 17796bd6224SChanwoo Choi #define CLK_SCLK_SPI3 30 17896bd6224SChanwoo Choi #define CLK_SCLK_SPI2 31 17996bd6224SChanwoo Choi #define CLK_SCLK_SPI1 32 18096bd6224SChanwoo Choi #define CLK_SCLK_SPI0 33 18196bd6224SChanwoo Choi #define CLK_SCLK_UART2 34 18296bd6224SChanwoo Choi #define CLK_SCLK_UART1 35 18396bd6224SChanwoo Choi #define CLK_SCLK_UART0 36 18496bd6224SChanwoo Choi 18596bd6224SChanwoo Choi #define PERIC_NR_CLK 37 18696bd6224SChanwoo Choi 18796bd6224SChanwoo Choi /* CMU_PERIS */ 18896bd6224SChanwoo Choi #define CLK_PCLK_HPM_APBIF 1 18996bd6224SChanwoo Choi #define CLK_PCLK_TMU1_APBIF 2 19096bd6224SChanwoo Choi #define CLK_PCLK_TMU0_APBIF 3 19196bd6224SChanwoo Choi #define CLK_PCLK_PMU_PERIS 4 19296bd6224SChanwoo Choi #define CLK_PCLK_SYSREG_PERIS 5 19396bd6224SChanwoo Choi #define CLK_PCLK_CMU_TOP_APBIF 6 19496bd6224SChanwoo Choi #define CLK_PCLK_WDT_APOLLO 7 19596bd6224SChanwoo Choi #define CLK_PCLK_WDT_ATLAS 8 19696bd6224SChanwoo Choi #define CLK_PCLK_MCT 9 19796bd6224SChanwoo Choi #define CLK_PCLK_HDMI_CEC 10 19896bd6224SChanwoo Choi 19996bd6224SChanwoo Choi #define PERIS_NR_CLK 11 20096bd6224SChanwoo Choi 20196bd6224SChanwoo Choi /* CMU_FSYS */ 20296bd6224SChanwoo Choi #define CLK_MOUT_ACLK_FSYS_200_USER 1 20396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_USER 2 20496bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_USER 3 20596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_USER 4 20696bd6224SChanwoo Choi 20796bd6224SChanwoo Choi #define CLK_ACLK_PCIE 50 20896bd6224SChanwoo Choi #define CLK_ACLK_PDMA1 51 20996bd6224SChanwoo Choi #define CLK_ACLK_TSI 52 21096bd6224SChanwoo Choi #define CLK_ACLK_MMC2 53 21196bd6224SChanwoo Choi #define CLK_ACLK_MMC1 54 21296bd6224SChanwoo Choi #define CLK_ACLK_MMC0 55 21396bd6224SChanwoo Choi #define CLK_ACLK_UFS 56 21496bd6224SChanwoo Choi #define CLK_ACLK_USBHOST20 57 21596bd6224SChanwoo Choi #define CLK_ACLK_USBHOST30 58 21696bd6224SChanwoo Choi #define CLK_ACLK_USBDRD30 59 21796bd6224SChanwoo Choi #define CLK_ACLK_PDMA0 60 21896bd6224SChanwoo Choi #define CLK_SCLK_MMC2 61 21996bd6224SChanwoo Choi #define CLK_SCLK_MMC1 62 22096bd6224SChanwoo Choi #define CLK_SCLK_MMC0 63 22196bd6224SChanwoo Choi #define CLK_PDMA1 64 22296bd6224SChanwoo Choi #define CLK_PDMA0 65 22396bd6224SChanwoo Choi 22496bd6224SChanwoo Choi #define FSYS_NR_CLK 66 22596bd6224SChanwoo Choi 22696bd6224SChanwoo Choi #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 227