196bd6224SChanwoo Choi /* 296bd6224SChanwoo Choi * Copyright (c) 2014 Samsung Electronics Co., Ltd. 396bd6224SChanwoo Choi * Author: Chanwoo Choi <cw00.choi@samsung.com> 496bd6224SChanwoo Choi * 596bd6224SChanwoo Choi * This program is free software; you can redistribute it and/or modify 696bd6224SChanwoo Choi * it under the terms of the GNU General Public License version 2 as 796bd6224SChanwoo Choi * published by the Free Software Foundation. 896bd6224SChanwoo Choi */ 996bd6224SChanwoo Choi 1096bd6224SChanwoo Choi #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 1196bd6224SChanwoo Choi #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 1296bd6224SChanwoo Choi 1396bd6224SChanwoo Choi /* CMU_TOP */ 1496bd6224SChanwoo Choi #define CLK_FOUT_ISP_PLL 1 1596bd6224SChanwoo Choi #define CLK_FOUT_AUD_PLL 2 1696bd6224SChanwoo Choi 1796bd6224SChanwoo Choi #define CLK_MOUT_AUD_PLL 10 1896bd6224SChanwoo Choi #define CLK_MOUT_ISP_PLL 11 1996bd6224SChanwoo Choi #define CLK_MOUT_AUD_PLL_USER_T 12 2096bd6224SChanwoo Choi #define CLK_MOUT_MPHY_PLL_USER 13 2196bd6224SChanwoo Choi #define CLK_MOUT_MFC_PLL_USER 14 2296bd6224SChanwoo Choi #define CLK_MOUT_BUS_PLL_USER 15 2396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_HEVC_400 16 2496bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_333 17 2596bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_B 18 2696bd6224SChanwoo Choi #define CLK_MOUT_ACLK_CAM1_552_A 19 2796bd6224SChanwoo Choi #define CLK_MOUT_ACLK_ISP_DIS_400 20 2896bd6224SChanwoo Choi #define CLK_MOUT_ACLK_ISP_400 21 2996bd6224SChanwoo Choi #define CLK_MOUT_ACLK_BUS0_400 22 3096bd6224SChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_B 23 3196bd6224SChanwoo Choi #define CLK_MOUT_ACLK_MSCL_400_A 24 3296bd6224SChanwoo Choi #define CLK_MOUT_ACLK_GSCL_333 25 3396bd6224SChanwoo Choi #define CLK_MOUT_ACLK_G2D_400_B 26 3496bd6224SChanwoo Choi #define CLK_MOUT_ACLK_G2D_400_A 27 3596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_C 28 3696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_B 29 3796bd6224SChanwoo Choi #define CLK_MOUT_SCLK_JPEG_A 30 3896bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_B 31 3996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_A 32 4096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_B 33 4196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_A 34 4296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_D 35 4396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_C 36 4496bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_B 37 4596bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_A 38 4696bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI4 39 4796bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI3 40 4896bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART2 41 4996bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART1 42 5096bd6224SChanwoo Choi #define CLK_MOUT_SCLK_UART0 43 5196bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI2 44 5296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI1 45 5396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_SPI0 46 5423236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_C 47 5523236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_B 48 5623236496SChanwoo Choi #define CLK_MOUT_ACLK_MFC_400_A 49 5723236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR2 50 5823236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR1 51 5923236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SENSOR0 52 6023236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_UART 53 6123236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI1 54 6223236496SChanwoo Choi #define CLK_MOUT_SCLK_ISP_SPI0 55 6323236496SChanwoo Choi #define CLK_MOUT_SCLK_PCIE_100 56 6423236496SChanwoo Choi #define CLK_MOUT_SCLK_UFSUNIPRO 57 6523236496SChanwoo Choi #define CLK_MOUT_SCLK_USBHOST30 58 6623236496SChanwoo Choi #define CLK_MOUT_SCLK_USBDRD30 59 6723236496SChanwoo Choi #define CLK_MOUT_SCLK_SLIMBUS 60 6823236496SChanwoo Choi #define CLK_MOUT_SCLK_SPDIF 61 6923236496SChanwoo Choi #define CLK_MOUT_SCLK_AUDIO1 62 7023236496SChanwoo Choi #define CLK_MOUT_SCLK_AUDIO0 63 7196bd6224SChanwoo Choi 7296bd6224SChanwoo Choi #define CLK_DIV_ACLK_FSYS_200 100 7396bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_SSSX_266 101 7496bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_200 102 7596bd6224SChanwoo Choi #define CLK_DIV_ACLK_IMEM_266 103 7696bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIC_66_B 104 7796bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIC_66_A 105 7896bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIS_66_B 106 7996bd6224SChanwoo Choi #define CLK_DIV_ACLK_PERIS_66_A 107 8096bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC1_B 108 8196bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC1_A 109 8296bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC0_B 110 8396bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC0_A 111 8496bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC2_B 112 8596bd6224SChanwoo Choi #define CLK_DIV_SCLK_MMC2_A 113 8696bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI1_B 114 8796bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI1_A 115 8896bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI0_B 116 8996bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI0_A 117 9096bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI2_B 118 9196bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI2_A 119 9296bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART2 120 9396bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART1 121 9496bd6224SChanwoo Choi #define CLK_DIV_SCLK_UART0 122 9596bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI4_B 123 9696bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI4_A 124 9796bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI3_B 125 9896bd6224SChanwoo Choi #define CLK_DIV_SCLK_SPI3_A 126 9923236496SChanwoo Choi #define CLK_DIV_SCLK_I2S1 127 10023236496SChanwoo Choi #define CLK_DIV_SCLK_PCM1 128 10123236496SChanwoo Choi #define CLK_DIV_SCLK_AUDIO1 129 10223236496SChanwoo Choi #define CLK_DIV_SCLK_AUDIO0 130 103a29308daSChanwoo Choi #define CLK_DIV_ACLK_GSCL_111 131 104a29308daSChanwoo Choi #define CLK_DIV_ACLK_GSCL_333 132 105a29308daSChanwoo Choi #define CLK_DIV_ACLK_HEVC_400 133 106a29308daSChanwoo Choi #define CLK_DIV_ACLK_MFC_400 134 107a29308daSChanwoo Choi #define CLK_DIV_ACLK_G2D_266 135 108a29308daSChanwoo Choi #define CLK_DIV_ACLK_G2D_400 136 10996bd6224SChanwoo Choi 11096bd6224SChanwoo Choi #define CLK_ACLK_PERIC_66 200 11196bd6224SChanwoo Choi #define CLK_ACLK_PERIS_66 201 11296bd6224SChanwoo Choi #define CLK_ACLK_FSYS_200 202 11396bd6224SChanwoo Choi #define CLK_SCLK_MMC2_FSYS 203 11496bd6224SChanwoo Choi #define CLK_SCLK_MMC1_FSYS 204 11596bd6224SChanwoo Choi #define CLK_SCLK_MMC0_FSYS 205 11696bd6224SChanwoo Choi #define CLK_SCLK_SPI4_PERIC 206 11796bd6224SChanwoo Choi #define CLK_SCLK_SPI3_PERIC 207 11896bd6224SChanwoo Choi #define CLK_SCLK_UART2_PERIC 208 11996bd6224SChanwoo Choi #define CLK_SCLK_UART1_PERIC 209 12096bd6224SChanwoo Choi #define CLK_SCLK_UART0_PERIC 210 12196bd6224SChanwoo Choi #define CLK_SCLK_SPI2_PERIC 211 12296bd6224SChanwoo Choi #define CLK_SCLK_SPI1_PERIC 212 12396bd6224SChanwoo Choi #define CLK_SCLK_SPI0_PERIC 213 12423236496SChanwoo Choi #define CLK_SCLK_SPDIF_PERIC 214 12523236496SChanwoo Choi #define CLK_SCLK_I2S1_PERIC 215 12623236496SChanwoo Choi #define CLK_SCLK_PCM1_PERIC 216 12723236496SChanwoo Choi #define CLK_SCLK_SLIMBUS 217 12823236496SChanwoo Choi #define CLK_SCLK_AUDIO1 218 12923236496SChanwoo Choi #define CLK_SCLK_AUDIO0 219 130a29308daSChanwoo Choi #define CLK_ACLK_G2D_266 220 131a29308daSChanwoo Choi #define CLK_ACLK_G2D_400 221 13296bd6224SChanwoo Choi 133a29308daSChanwoo Choi #define TOP_NR_CLK 222 13496bd6224SChanwoo Choi 13596bd6224SChanwoo Choi /* CMU_CPIF */ 13696bd6224SChanwoo Choi #define CLK_FOUT_MPHY_PLL 1 13796bd6224SChanwoo Choi 13896bd6224SChanwoo Choi #define CLK_MOUT_MPHY_PLL 2 13996bd6224SChanwoo Choi 14096bd6224SChanwoo Choi #define CLK_DIV_SCLK_MPHY 10 14196bd6224SChanwoo Choi 14296bd6224SChanwoo Choi #define CLK_SCLK_MPHY_PLL 11 14396bd6224SChanwoo Choi #define CLK_SCLK_UFS_MPHY 11 14496bd6224SChanwoo Choi 14596bd6224SChanwoo Choi #define CPIF_NR_CLK 12 14696bd6224SChanwoo Choi 14796bd6224SChanwoo Choi /* CMU_MIF */ 14896bd6224SChanwoo Choi #define CLK_FOUT_MEM0_PLL 1 14996bd6224SChanwoo Choi #define CLK_FOUT_MEM1_PLL 2 15096bd6224SChanwoo Choi #define CLK_FOUT_BUS_PLL 3 15196bd6224SChanwoo Choi #define CLK_FOUT_MFC_PLL 4 15206d2f9dfSChanwoo Choi #define CLK_DOUT_MFC_PLL 5 15306d2f9dfSChanwoo Choi #define CLK_DOUT_BUS_PLL 6 15406d2f9dfSChanwoo Choi #define CLK_DOUT_MEM1_PLL 7 15506d2f9dfSChanwoo Choi #define CLK_DOUT_MEM0_PLL 8 15696bd6224SChanwoo Choi 15706d2f9dfSChanwoo Choi #define CLK_MOUT_MFC_PLL_DIV2 10 15806d2f9dfSChanwoo Choi #define CLK_MOUT_BUS_PLL_DIV2 11 15906d2f9dfSChanwoo Choi #define CLK_MOUT_MEM1_PLL_DIV2 12 16006d2f9dfSChanwoo Choi #define CLK_MOUT_MEM0_PLL_DIV2 13 16106d2f9dfSChanwoo Choi #define CLK_MOUT_MFC_PLL 14 16206d2f9dfSChanwoo Choi #define CLK_MOUT_BUS_PLL 15 16306d2f9dfSChanwoo Choi #define CLK_MOUT_MEM1_PLL 16 16406d2f9dfSChanwoo Choi #define CLK_MOUT_MEM0_PLL 17 16506d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_C 18 16606d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_B 19 16706d2f9dfSChanwoo Choi #define CLK_MOUT_CLK2X_PHY_A 20 16806d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_C 21 16906d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_B 22 17006d2f9dfSChanwoo Choi #define CLK_MOUT_CLKM_PHY_A 23 17106d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_MIFNM_200 24 17206d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_MIFNM_400 25 17306d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_B 26 17406d2f9dfSChanwoo Choi #define CLK_MOUT_ACLK_DISP_333_A 27 17506d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_C 28 17606d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_B 29 17706d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_VCLK_A 30 17806d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_C 31 17906d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_B 32 18006d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_ECLK_A 33 18106d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34 18206d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35 18306d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36 18406d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_C 37 18506d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_B 38 18606d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSD_A 39 18706d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_C 40 18806d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_B 41 18906d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM0_A 42 19006d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46 19106d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47 19206d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48 19306d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_C 49 19406d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_B 50 19506d2f9dfSChanwoo Choi #define CLK_MOUT_SCLK_DSIM1_A 51 19606d2f9dfSChanwoo Choi 19706d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_HPM_MIF 55 19806d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DREX1 56 19906d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DREX0 57 20006d2f9dfSChanwoo Choi #define CLK_DIV_CLK2XPHY 58 20106d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_266 59 20206d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIFND_133 60 20306d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_133 61 20406d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIFNM_200 62 20506d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_200 63 20606d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_MIF_400 64 20706d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_BUS2_400 65 20806d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_DISP_333 66 20906d2f9dfSChanwoo Choi #define CLK_DIV_ACLK_CPIF_200 67 21006d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSIM1 68 21106d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_VCLK 69 21206d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSIM0 70 21306d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DSD 71 21406d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_TV_ECLK 72 21506d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_VCLK 73 21606d2f9dfSChanwoo Choi #define CLK_DIV_SCLK_DECON_ECLK 74 21706d2f9dfSChanwoo Choi #define CLK_DIV_MIF_PRE 75 21806d2f9dfSChanwoo Choi 21906d2f9dfSChanwoo Choi #define CLK_CLK2X_PHY1 80 22006d2f9dfSChanwoo Choi #define CLK_CLK2X_PHY0 81 22106d2f9dfSChanwoo Choi #define CLK_CLKM_PHY1 82 22206d2f9dfSChanwoo Choi #define CLK_CLKM_PHY0 83 22306d2f9dfSChanwoo Choi #define CLK_RCLK_DREX1 84 22406d2f9dfSChanwoo Choi #define CLK_RCLK_DREX0 85 22506d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_TZ 86 22606d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_TZ 87 22706d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_PEREV 88 22806d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_PEREV 89 22906d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_MEMIF 90 23006d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_MEMIF 91 23106d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_SCH 92 23206d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_SCH 93 23306d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_BUSIF 94 23406d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_BUSIF 95 23506d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1_BUSIF_RD 96 23606d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0_BUSIF_RD 97 23706d2f9dfSChanwoo Choi #define CLK_ACLK_DREX1 98 23806d2f9dfSChanwoo Choi #define CLK_ACLK_DREX0 99 23906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100 24006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101 24106d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102 24206d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103 24306d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104 24406d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105 24506d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_CP1 106 24606d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_CP1 107 24706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_CP0 108 24806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_CP0 109 24906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_3 110 25006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_3 111 25106d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_1 112 25206d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_1 113 25306d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX1_0 114 25406d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX1_0 115 25506d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_3 116 25606d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_3 117 25706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_1 118 25806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_1 119 25906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIS_DREX0_0 120 26006d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAXIM_DREX0_0 121 26106d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF2P 122 26206d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF1P 123 26306d2f9dfSChanwoo Choi #define CLK_ACLK_AHB2APB_MIF0P 124 26406d2f9dfSChanwoo Choi #define CLK_ACLK_IXIU_CCI 125 26506d2f9dfSChanwoo Choi #define CLK_ACLK_XIU_MIFSFRX 126 26606d2f9dfSChanwoo Choi #define CLK_ACLK_MIFNP_133 127 26706d2f9dfSChanwoo Choi #define CLK_ACLK_MIFNM_200 128 26806d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_133 129 26906d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_400 130 27006d2f9dfSChanwoo Choi #define CLK_ACLK_CCI 131 27106d2f9dfSChanwoo Choi #define CLK_ACLK_MIFND_266 132 27206d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S3 133 27306d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S1 134 27406d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX1S0 135 27506d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S3 136 27606d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S1 137 27706d2f9dfSChanwoo Choi #define CLK_ACLK_PPMU_DREX0S0 138 27806d2f9dfSChanwoo Choi #define CLK_ACLK_BTS_APOLLO 139 27906d2f9dfSChanwoo Choi #define CLK_ACLK_BTS_ATLAS 140 28006d2f9dfSChanwoo Choi #define CLK_ACLK_ACE_SEL_APOLL 141 28106d2f9dfSChanwoo Choi #define CLK_ACLK_ACE_SEL_ATLAS 142 28206d2f9dfSChanwoo Choi #define CLK_ACLK_AXIDS_CCI_MIFSFRX 143 28306d2f9dfSChanwoo Choi #define CLK_ACLK_AXIUS_ATLAS_CCI 144 28406d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDNS_CCI 145 28506d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDN_CCI 146 28606d2f9dfSChanwoo Choi #define CLK_ACLK_AXISYNCDN_NOC_D 147 28706d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148 28806d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149 28906d2f9dfSChanwoo Choi #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150 29006d2f9dfSChanwoo Choi #define CLK_ACLK_BUS2_400 151 29106d2f9dfSChanwoo Choi #define CLK_ACLK_DISP_333 152 29206d2f9dfSChanwoo Choi #define CLK_ACLK_CPIF_200 153 29306d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S3 154 29406d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S1 155 29506d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX1S0 156 29606d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S3 157 29706d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S1 158 29806d2f9dfSChanwoo Choi #define CLK_PCLK_PPMU_DREX0S0 159 29906d2f9dfSChanwoo Choi #define CLK_PCLK_BTS_APOLLO 160 30006d2f9dfSChanwoo Choi #define CLK_PCLK_BTS_ATLAS 161 30106d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162 30206d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_CP1 163 30306d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_CP0 164 30406d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_3 165 30506d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_1 166 30606d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX1_0 167 30706d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_3 168 30806d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_1 169 30906d2f9dfSChanwoo Choi #define CLK_PCLK_ASYNCAXI_DREX0_0 170 31006d2f9dfSChanwoo Choi #define CLK_PCLK_MIFSRVND_133 171 31106d2f9dfSChanwoo Choi #define CLK_PCLK_PMU_MIF 172 31206d2f9dfSChanwoo Choi #define CLK_PCLK_SYSREG_MIF 173 31306d2f9dfSChanwoo Choi #define CLK_PCLK_GPIO_ALIVE 174 31406d2f9dfSChanwoo Choi #define CLK_PCLK_ABB 175 31506d2f9dfSChanwoo Choi #define CLK_PCLK_PMU_APBIF 176 31606d2f9dfSChanwoo Choi #define CLK_PCLK_DDR_PHY1 177 31706d2f9dfSChanwoo Choi #define CLK_PCLK_DREX1 178 31806d2f9dfSChanwoo Choi #define CLK_PCLK_DDR_PHY0 179 31906d2f9dfSChanwoo Choi #define CLK_PCLK_DREX0 180 32006d2f9dfSChanwoo Choi #define CLK_PCLK_DREX0_TZ 181 32106d2f9dfSChanwoo Choi #define CLK_PCLK_DREX1_TZ 182 32206d2f9dfSChanwoo Choi #define CLK_PCLK_MONOTONIC_CNT 183 32306d2f9dfSChanwoo Choi #define CLK_PCLK_RTC 184 32406d2f9dfSChanwoo Choi #define CLK_SCLK_DSIM1_DISP 185 32506d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_TV_VCLK_DISP 186 32606d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_BUS_PLL 187 32706d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MFC_PLL 188 32806d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MEM0_PLL 189 32906d2f9dfSChanwoo Choi #define CLK_SCLK_FREQ_DET_MEM1_PLL 190 33006d2f9dfSChanwoo Choi #define CLK_SCLK_DSIM0_DISP 191 33106d2f9dfSChanwoo Choi #define CLK_SCLK_DSD_DISP 192 33206d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_TV_ECLK_DISP 193 33306d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_VCLK_DISP 194 33406d2f9dfSChanwoo Choi #define CLK_SCLK_DECON_ECLK_DISP 195 33506d2f9dfSChanwoo Choi #define CLK_SCLK_HPM_MIF 196 33606d2f9dfSChanwoo Choi #define CLK_SCLK_MFC_PLL 197 33706d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL 198 33806d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL_APOLLO 199 33906d2f9dfSChanwoo Choi #define CLK_SCLK_BUS_PLL_ATLAS 200 34006d2f9dfSChanwoo Choi 34106d2f9dfSChanwoo Choi #define MIF_NR_CLK 201 34296bd6224SChanwoo Choi 34396bd6224SChanwoo Choi /* CMU_PERIC */ 34496bd6224SChanwoo Choi #define CLK_PCLK_SPI2 1 34596bd6224SChanwoo Choi #define CLK_PCLK_SPI1 2 34696bd6224SChanwoo Choi #define CLK_PCLK_SPI0 3 34796bd6224SChanwoo Choi #define CLK_PCLK_UART2 4 34896bd6224SChanwoo Choi #define CLK_PCLK_UART1 5 34996bd6224SChanwoo Choi #define CLK_PCLK_UART0 6 35096bd6224SChanwoo Choi #define CLK_PCLK_HSI2C3 7 35196bd6224SChanwoo Choi #define CLK_PCLK_HSI2C2 8 35296bd6224SChanwoo Choi #define CLK_PCLK_HSI2C1 9 35396bd6224SChanwoo Choi #define CLK_PCLK_HSI2C0 10 35496bd6224SChanwoo Choi #define CLK_PCLK_I2C7 11 35596bd6224SChanwoo Choi #define CLK_PCLK_I2C6 12 35696bd6224SChanwoo Choi #define CLK_PCLK_I2C5 13 35796bd6224SChanwoo Choi #define CLK_PCLK_I2C4 14 35896bd6224SChanwoo Choi #define CLK_PCLK_I2C3 15 35996bd6224SChanwoo Choi #define CLK_PCLK_I2C2 16 36096bd6224SChanwoo Choi #define CLK_PCLK_I2C1 17 36196bd6224SChanwoo Choi #define CLK_PCLK_I2C0 18 36296bd6224SChanwoo Choi #define CLK_PCLK_SPI4 19 36396bd6224SChanwoo Choi #define CLK_PCLK_SPI3 20 36496bd6224SChanwoo Choi #define CLK_PCLK_HSI2C11 21 36596bd6224SChanwoo Choi #define CLK_PCLK_HSI2C10 22 36696bd6224SChanwoo Choi #define CLK_PCLK_HSI2C9 23 36796bd6224SChanwoo Choi #define CLK_PCLK_HSI2C8 24 36896bd6224SChanwoo Choi #define CLK_PCLK_HSI2C7 25 36996bd6224SChanwoo Choi #define CLK_PCLK_HSI2C6 26 37096bd6224SChanwoo Choi #define CLK_PCLK_HSI2C5 27 37196bd6224SChanwoo Choi #define CLK_PCLK_HSI2C4 28 37296bd6224SChanwoo Choi #define CLK_SCLK_SPI4 29 37396bd6224SChanwoo Choi #define CLK_SCLK_SPI3 30 37496bd6224SChanwoo Choi #define CLK_SCLK_SPI2 31 37596bd6224SChanwoo Choi #define CLK_SCLK_SPI1 32 37696bd6224SChanwoo Choi #define CLK_SCLK_SPI0 33 37796bd6224SChanwoo Choi #define CLK_SCLK_UART2 34 37896bd6224SChanwoo Choi #define CLK_SCLK_UART1 35 37996bd6224SChanwoo Choi #define CLK_SCLK_UART0 36 380d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC2P 37 381d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC1P 38 382d0f5de66SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIC0P 39 383d0f5de66SChanwoo Choi #define CLK_ACLK_PERICNP_66 40 384d0f5de66SChanwoo Choi #define CLK_PCLK_SCI 41 385d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_FINGER 42 386d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_ESE 43 387d0f5de66SChanwoo Choi #define CLK_PCLK_PWM 44 388d0f5de66SChanwoo Choi #define CLK_PCLK_SPDIF 45 389d0f5de66SChanwoo Choi #define CLK_PCLK_PCM1 46 390d0f5de66SChanwoo Choi #define CLK_PCLK_I2S1 47 391d0f5de66SChanwoo Choi #define CLK_PCLK_ADCIF 48 392d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_TOUCH 49 393d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_NFC 50 394d0f5de66SChanwoo Choi #define CLK_PCLK_GPIO_PERIC 51 395d0f5de66SChanwoo Choi #define CLK_PCLK_PMU_PERIC 52 396d0f5de66SChanwoo Choi #define CLK_PCLK_SYSREG_PERIC 53 397d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI4 54 398d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI3 55 399d0f5de66SChanwoo Choi #define CLK_SCLK_SCI 56 400d0f5de66SChanwoo Choi #define CLK_SCLK_SC_IN 57 401d0f5de66SChanwoo Choi #define CLK_SCLK_PWM 58 402d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI2 59 403d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI1 60 404d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_SPI0 61 405d0f5de66SChanwoo Choi #define CLK_SCLK_IOCLK_I2S1_BCLK 62 406d0f5de66SChanwoo Choi #define CLK_SCLK_SPDIF 63 407d0f5de66SChanwoo Choi #define CLK_SCLK_PCM1 64 408d0f5de66SChanwoo Choi #define CLK_SCLK_I2S1 65 40996bd6224SChanwoo Choi 410d0f5de66SChanwoo Choi #define CLK_DIV_SCLK_SCI 70 411d0f5de66SChanwoo Choi #define CLK_DIV_SCLK_SC_IN 71 412d0f5de66SChanwoo Choi 413d0f5de66SChanwoo Choi #define PERIC_NR_CLK 72 41496bd6224SChanwoo Choi 41596bd6224SChanwoo Choi /* CMU_PERIS */ 41696bd6224SChanwoo Choi #define CLK_PCLK_HPM_APBIF 1 41796bd6224SChanwoo Choi #define CLK_PCLK_TMU1_APBIF 2 41896bd6224SChanwoo Choi #define CLK_PCLK_TMU0_APBIF 3 41996bd6224SChanwoo Choi #define CLK_PCLK_PMU_PERIS 4 42096bd6224SChanwoo Choi #define CLK_PCLK_SYSREG_PERIS 5 42196bd6224SChanwoo Choi #define CLK_PCLK_CMU_TOP_APBIF 6 42296bd6224SChanwoo Choi #define CLK_PCLK_WDT_APOLLO 7 42396bd6224SChanwoo Choi #define CLK_PCLK_WDT_ATLAS 8 42496bd6224SChanwoo Choi #define CLK_PCLK_MCT 9 42596bd6224SChanwoo Choi #define CLK_PCLK_HDMI_CEC 10 42656bcf3f3SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIS1P 11 42756bcf3f3SChanwoo Choi #define CLK_ACLK_AHB2APB_PERIS0P 12 42856bcf3f3SChanwoo Choi #define CLK_ACLK_PERISNP_66 13 42956bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC12 14 43056bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC11 15 43156bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC10 16 43256bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC9 17 43356bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC8 18 43456bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC7 19 43556bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC6 20 43656bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC5 21 43756bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC4 22 43856bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC3 23 43956bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC2 24 44056bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC1 25 44156bcf3f3SChanwoo Choi #define CLK_PCLK_TZPC0 26 44256bcf3f3SChanwoo Choi #define CLK_PCLK_SECKEY_APBIF 27 44356bcf3f3SChanwoo Choi #define CLK_PCLK_CHIPID_APBIF 28 44456bcf3f3SChanwoo Choi #define CLK_PCLK_TOPRTC 29 44556bcf3f3SChanwoo Choi #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 44656bcf3f3SChanwoo Choi #define CLK_PCLK_ANTIRBK_CNT_APBIF 31 44756bcf3f3SChanwoo Choi #define CLK_PCLK_OTP_CON_APBIF 32 44856bcf3f3SChanwoo Choi #define CLK_SCLK_ASV_TB 33 44956bcf3f3SChanwoo Choi #define CLK_SCLK_TMU1 34 45056bcf3f3SChanwoo Choi #define CLK_SCLK_TMU0 35 45156bcf3f3SChanwoo Choi #define CLK_SCLK_SECKEY 36 45256bcf3f3SChanwoo Choi #define CLK_SCLK_CHIPID 37 45356bcf3f3SChanwoo Choi #define CLK_SCLK_TOPRTC 38 45456bcf3f3SChanwoo Choi #define CLK_SCLK_CUSTOM_EFUSE 39 45556bcf3f3SChanwoo Choi #define CLK_SCLK_ANTIRBK_CNT 40 45656bcf3f3SChanwoo Choi #define CLK_SCLK_OTP_CON 41 45796bd6224SChanwoo Choi 45856bcf3f3SChanwoo Choi #define PERIS_NR_CLK 42 45996bd6224SChanwoo Choi 46096bd6224SChanwoo Choi /* CMU_FSYS */ 46196bd6224SChanwoo Choi #define CLK_MOUT_ACLK_FSYS_200_USER 1 46296bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC2_USER 2 46396bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC1_USER 3 46496bd6224SChanwoo Choi #define CLK_MOUT_SCLK_MMC0_USER 4 46596bd6224SChanwoo Choi 46696bd6224SChanwoo Choi #define CLK_ACLK_PCIE 50 46796bd6224SChanwoo Choi #define CLK_ACLK_PDMA1 51 46896bd6224SChanwoo Choi #define CLK_ACLK_TSI 52 46996bd6224SChanwoo Choi #define CLK_ACLK_MMC2 53 47096bd6224SChanwoo Choi #define CLK_ACLK_MMC1 54 47196bd6224SChanwoo Choi #define CLK_ACLK_MMC0 55 47296bd6224SChanwoo Choi #define CLK_ACLK_UFS 56 47396bd6224SChanwoo Choi #define CLK_ACLK_USBHOST20 57 47496bd6224SChanwoo Choi #define CLK_ACLK_USBHOST30 58 47596bd6224SChanwoo Choi #define CLK_ACLK_USBDRD30 59 47696bd6224SChanwoo Choi #define CLK_ACLK_PDMA0 60 47796bd6224SChanwoo Choi #define CLK_SCLK_MMC2 61 47896bd6224SChanwoo Choi #define CLK_SCLK_MMC1 62 47996bd6224SChanwoo Choi #define CLK_SCLK_MMC0 63 48096bd6224SChanwoo Choi #define CLK_PDMA1 64 48196bd6224SChanwoo Choi #define CLK_PDMA0 65 48296bd6224SChanwoo Choi 48396bd6224SChanwoo Choi #define FSYS_NR_CLK 66 48496bd6224SChanwoo Choi 485a29308daSChanwoo Choi /* CMU_G2D */ 486a29308daSChanwoo Choi #define CLK_MUX_ACLK_G2D_266_USER 1 487a29308daSChanwoo Choi #define CLK_MUX_ACLK_G2D_400_USER 2 488a29308daSChanwoo Choi 489a29308daSChanwoo Choi #define CLK_DIV_PCLK_G2D 3 490a29308daSChanwoo Choi 491a29308daSChanwoo Choi #define CLK_ACLK_SMMU_MDMA1 4 492a29308daSChanwoo Choi #define CLK_ACLK_BTS_MDMA1 5 493a29308daSChanwoo Choi #define CLK_ACLK_BTS_G2D 6 494a29308daSChanwoo Choi #define CLK_ACLK_ALB_G2D 7 495a29308daSChanwoo Choi #define CLK_ACLK_AXIUS_G2DX 8 496a29308daSChanwoo Choi #define CLK_ACLK_ASYNCAXI_SYSX 9 497a29308daSChanwoo Choi #define CLK_ACLK_AHB2APB_G2D1P 10 498a29308daSChanwoo Choi #define CLK_ACLK_AHB2APB_G2D0P 11 499a29308daSChanwoo Choi #define CLK_ACLK_XIU_G2DX 12 500a29308daSChanwoo Choi #define CLK_ACLK_G2DNP_133 13 501a29308daSChanwoo Choi #define CLK_ACLK_G2DND_400 14 502a29308daSChanwoo Choi #define CLK_ACLK_MDMA1 15 503a29308daSChanwoo Choi #define CLK_ACLK_G2D 16 504a29308daSChanwoo Choi #define CLK_ACLK_SMMU_G2D 17 505a29308daSChanwoo Choi #define CLK_PCLK_SMMU_MDMA1 18 506a29308daSChanwoo Choi #define CLK_PCLK_BTS_MDMA1 19 507a29308daSChanwoo Choi #define CLK_PCLK_BTS_G2D 20 508a29308daSChanwoo Choi #define CLK_PCLK_ALB_G2D 21 509a29308daSChanwoo Choi #define CLK_PCLK_ASYNCAXI_SYSX 22 510a29308daSChanwoo Choi #define CLK_PCLK_PMU_G2D 23 511a29308daSChanwoo Choi #define CLK_PCLK_SYSREG_G2D 24 512a29308daSChanwoo Choi #define CLK_PCLK_G2D 25 513a29308daSChanwoo Choi #define CLK_PCLK_SMMU_G2D 26 514a29308daSChanwoo Choi 515a29308daSChanwoo Choi #define G2D_NR_CLK 27 516a29308daSChanwoo Choi 51796bd6224SChanwoo Choi #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 518