1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Author: Andrzej Haja <a.hajda@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Device Tree binding constants for Exynos5420 clock controller. 10 */ 11 12 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H 13 #define _DT_BINDINGS_CLOCK_EXYNOS_5420_H 14 15 /* core clocks */ 16 #define CLK_FIN_PLL 1 17 #define CLK_FOUT_APLL 2 18 #define CLK_FOUT_CPLL 3 19 #define CLK_FOUT_DPLL 4 20 #define CLK_FOUT_EPLL 5 21 #define CLK_FOUT_RPLL 6 22 #define CLK_FOUT_IPLL 7 23 #define CLK_FOUT_SPLL 8 24 #define CLK_FOUT_VPLL 9 25 #define CLK_FOUT_MPLL 10 26 #define CLK_FOUT_BPLL 11 27 #define CLK_FOUT_KPLL 12 28 29 /* gate for special clocks (sclk) */ 30 #define CLK_SCLK_UART0 128 31 #define CLK_SCLK_UART1 129 32 #define CLK_SCLK_UART2 130 33 #define CLK_SCLK_UART3 131 34 #define CLK_SCLK_MMC0 132 35 #define CLK_SCLK_MMC1 133 36 #define CLK_SCLK_MMC2 134 37 #define CLK_SCLK_SPI0 135 38 #define CLK_SCLK_SPI1 136 39 #define CLK_SCLK_SPI2 137 40 #define CLK_SCLK_I2S1 138 41 #define CLK_SCLK_I2S2 139 42 #define CLK_SCLK_PCM1 140 43 #define CLK_SCLK_PCM2 141 44 #define CLK_SCLK_SPDIF 142 45 #define CLK_SCLK_HDMI 143 46 #define CLK_SCLK_PIXEL 144 47 #define CLK_SCLK_DP1 145 48 #define CLK_SCLK_MIPI1 146 49 #define CLK_SCLK_FIMD1 147 50 #define CLK_SCLK_MAUDIO0 148 51 #define CLK_SCLK_MAUPCM0 149 52 #define CLK_SCLK_USBD300 150 53 #define CLK_SCLK_USBD301 151 54 #define CLK_SCLK_USBPHY300 152 55 #define CLK_SCLK_USBPHY301 153 56 #define CLK_SCLK_UNIPRO 154 57 #define CLK_SCLK_PWM 155 58 #define CLK_SCLK_GSCL_WA 156 59 #define CLK_SCLK_GSCL_WB 157 60 #define CLK_SCLK_HDMIPHY 158 61 #define CLK_MAU_EPLL 159 62 #define CLK_SCLK_HSIC_12M 160 63 #define CLK_SCLK_MPHY_IXTAL24 161 64 65 /* gate clocks */ 66 #define CLK_ACLK66_PERIC 256 67 #define CLK_UART0 257 68 #define CLK_UART1 258 69 #define CLK_UART2 259 70 #define CLK_UART3 260 71 #define CLK_I2C0 261 72 #define CLK_I2C1 262 73 #define CLK_I2C2 263 74 #define CLK_I2C3 264 75 #define CLK_USI0 265 76 #define CLK_USI1 266 77 #define CLK_USI2 267 78 #define CLK_USI3 268 79 #define CLK_I2C_HDMI 269 80 #define CLK_TSADC 270 81 #define CLK_SPI0 271 82 #define CLK_SPI1 272 83 #define CLK_SPI2 273 84 #define CLK_KEYIF 274 85 #define CLK_I2S1 275 86 #define CLK_I2S2 276 87 #define CLK_PCM1 277 88 #define CLK_PCM2 278 89 #define CLK_PWM 279 90 #define CLK_SPDIF 280 91 #define CLK_USI4 281 92 #define CLK_USI5 282 93 #define CLK_USI6 283 94 #define CLK_ACLK66_PSGEN 300 95 #define CLK_CHIPID 301 96 #define CLK_SYSREG 302 97 #define CLK_TZPC0 303 98 #define CLK_TZPC1 304 99 #define CLK_TZPC2 305 100 #define CLK_TZPC3 306 101 #define CLK_TZPC4 307 102 #define CLK_TZPC5 308 103 #define CLK_TZPC6 309 104 #define CLK_TZPC7 310 105 #define CLK_TZPC8 311 106 #define CLK_TZPC9 312 107 #define CLK_HDMI_CEC 313 108 #define CLK_SECKEY 314 109 #define CLK_MCT 315 110 #define CLK_WDT 316 111 #define CLK_RTC 317 112 #define CLK_TMU 318 113 #define CLK_TMU_GPU 319 114 #define CLK_PCLK66_GPIO 330 115 #define CLK_ACLK200_FSYS2 350 116 #define CLK_MMC0 351 117 #define CLK_MMC1 352 118 #define CLK_MMC2 353 119 #define CLK_SROMC 354 120 #define CLK_UFS 355 121 #define CLK_ACLK200_FSYS 360 122 #define CLK_TSI 361 123 #define CLK_PDMA0 362 124 #define CLK_PDMA1 363 125 #define CLK_RTIC 364 126 #define CLK_USBH20 365 127 #define CLK_USBD300 366 128 #define CLK_USBD301 367 129 #define CLK_ACLK400_MSCL 380 130 #define CLK_MSCL0 381 131 #define CLK_MSCL1 382 132 #define CLK_MSCL2 383 133 #define CLK_SMMU_MSCL0 384 134 #define CLK_SMMU_MSCL1 385 135 #define CLK_SMMU_MSCL2 386 136 #define CLK_ACLK333 400 137 #define CLK_MFC 401 138 #define CLK_SMMU_MFCL 402 139 #define CLK_SMMU_MFCR 403 140 #define CLK_ACLK200_DISP1 410 141 #define CLK_DSIM1 411 142 #define CLK_DP1 412 143 #define CLK_HDMI 413 144 #define CLK_ACLK300_DISP1 420 145 #define CLK_FIMD1 421 146 #define CLK_SMMU_FIMD1M0 422 147 #define CLK_SMMU_FIMD1M1 423 148 #define CLK_ACLK166 430 149 #define CLK_MIXER 431 150 #define CLK_ACLK266 440 151 #define CLK_ROTATOR 441 152 #define CLK_MDMA1 442 153 #define CLK_SMMU_ROTATOR 443 154 #define CLK_SMMU_MDMA1 444 155 #define CLK_ACLK300_JPEG 450 156 #define CLK_JPEG 451 157 #define CLK_JPEG2 452 158 #define CLK_SMMU_JPEG 453 159 #define CLK_SMMU_JPEG2 454 160 #define CLK_ACLK300_GSCL 460 161 #define CLK_SMMU_GSCL0 461 162 #define CLK_SMMU_GSCL1 462 163 #define CLK_GSCL_WA 463 164 #define CLK_GSCL_WB 464 165 #define CLK_GSCL0 465 166 #define CLK_GSCL1 466 167 #define CLK_FIMC_3AA 467 168 #define CLK_ACLK266_G2D 470 169 #define CLK_SSS 471 170 #define CLK_SLIM_SSS 472 171 #define CLK_MDMA0 473 172 #define CLK_ACLK333_G2D 480 173 #define CLK_G2D 481 174 #define CLK_ACLK333_432_GSCL 490 175 #define CLK_SMMU_3AA 491 176 #define CLK_SMMU_FIMCL0 492 177 #define CLK_SMMU_FIMCL1 493 178 #define CLK_SMMU_FIMCL3 494 179 #define CLK_FIMC_LITE3 495 180 #define CLK_FIMC_LITE0 496 181 #define CLK_FIMC_LITE1 497 182 #define CLK_ACLK_G3D 500 183 #define CLK_G3D 501 184 #define CLK_SMMU_MIXER 502 185 #define CLK_SMMU_G2D 503 186 #define CLK_SMMU_MDMA0 504 187 #define CLK_MC 505 188 #define CLK_TOP_RTC 506 189 #define CLK_SCLK_UART_ISP 510 190 #define CLK_SCLK_SPI0_ISP 511 191 #define CLK_SCLK_SPI1_ISP 512 192 #define CLK_SCLK_PWM_ISP 513 193 #define CLK_SCLK_ISP_SENSOR0 514 194 #define CLK_SCLK_ISP_SENSOR1 515 195 #define CLK_SCLK_ISP_SENSOR2 516 196 #define CLK_ACLK432_SCALER 517 197 #define CLK_ACLK432_CAM 518 198 #define CLK_ACLK_FL1550_CAM 519 199 #define CLK_ACLK550_CAM 520 200 201 /* mux clocks */ 202 #define CLK_MOUT_HDMI 640 203 #define CLK_MOUT_G3D 641 204 #define CLK_MOUT_VPLL 642 205 #define CLK_MOUT_MAUDIO0 643 206 #define CLK_MOUT_USER_ACLK333 644 207 #define CLK_MOUT_SW_ACLK333 645 208 209 /* divider clocks */ 210 #define CLK_DOUT_PIXEL 768 211 212 /* must be greater than maximal clock id */ 213 #define CLK_NR_CLKS 769 214 215 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ 216