1cd9102e9SKrzysztof Kozlowski /* SPDX-License-Identifier: GPL-2.0 */ 25a989cf6SRahul Sharma /* 35a989cf6SRahul Sharma * Copyright (c) 2014 Samsung Electronics Co., Ltd. 45a989cf6SRahul Sharma * Author: Rahul Sharma <rahul.sharma@samsung.com> 55a989cf6SRahul Sharma * 65a989cf6SRahul Sharma * Provides Constants for Exynos5260 clocks. 75a989cf6SRahul Sharma */ 85a989cf6SRahul Sharma 95a989cf6SRahul Sharma #ifndef _DT_BINDINGS_CLK_EXYNOS5260_H 105a989cf6SRahul Sharma #define _DT_BINDINGS_CLK_EXYNOS5260_H 115a989cf6SRahul Sharma 125a989cf6SRahul Sharma /* Clock names: <cmu><type><IP> */ 135a989cf6SRahul Sharma 145a989cf6SRahul Sharma /* List Of Clocks For CMU_TOP */ 155a989cf6SRahul Sharma 165a989cf6SRahul Sharma #define TOP_FOUT_DISP_PLL 1 175a989cf6SRahul Sharma #define TOP_FOUT_AUD_PLL 2 185a989cf6SRahul Sharma #define TOP_MOUT_AUDTOP_PLL_USER 3 195a989cf6SRahul Sharma #define TOP_MOUT_AUD_PLL 4 205a989cf6SRahul Sharma #define TOP_MOUT_DISP_PLL 5 215a989cf6SRahul Sharma #define TOP_MOUT_BUSTOP_PLL_USER 6 225a989cf6SRahul Sharma #define TOP_MOUT_MEMTOP_PLL_USER 7 235a989cf6SRahul Sharma #define TOP_MOUT_MEDIATOP_PLL_USER 8 245a989cf6SRahul Sharma #define TOP_MOUT_DISP_DISP_333 9 255a989cf6SRahul Sharma #define TOP_MOUT_ACLK_DISP_333 10 265a989cf6SRahul Sharma #define TOP_MOUT_DISP_DISP_222 11 275a989cf6SRahul Sharma #define TOP_MOUT_ACLK_DISP_222 12 285a989cf6SRahul Sharma #define TOP_MOUT_DISP_MEDIA_PIXEL 13 295a989cf6SRahul Sharma #define TOP_MOUT_FIMD1 14 305a989cf6SRahul Sharma #define TOP_MOUT_SCLK_PERI_SPI0_CLK 15 315a989cf6SRahul Sharma #define TOP_MOUT_SCLK_PERI_SPI1_CLK 16 325a989cf6SRahul Sharma #define TOP_MOUT_SCLK_PERI_SPI2_CLK 17 335a989cf6SRahul Sharma #define TOP_MOUT_SCLK_PERI_UART0_UCLK 18 345a989cf6SRahul Sharma #define TOP_MOUT_SCLK_PERI_UART2_UCLK 19 355a989cf6SRahul Sharma #define TOP_MOUT_SCLK_PERI_UART1_UCLK 20 365a989cf6SRahul Sharma #define TOP_MOUT_BUS4_BUSTOP_100 21 375a989cf6SRahul Sharma #define TOP_MOUT_BUS4_BUSTOP_400 22 385a989cf6SRahul Sharma #define TOP_MOUT_BUS3_BUSTOP_100 23 395a989cf6SRahul Sharma #define TOP_MOUT_BUS3_BUSTOP_400 24 405a989cf6SRahul Sharma #define TOP_MOUT_BUS2_BUSTOP_400 25 415a989cf6SRahul Sharma #define TOP_MOUT_BUS2_BUSTOP_100 26 425a989cf6SRahul Sharma #define TOP_MOUT_BUS1_BUSTOP_100 27 435a989cf6SRahul Sharma #define TOP_MOUT_BUS1_BUSTOP_400 28 445a989cf6SRahul Sharma #define TOP_MOUT_SCLK_FSYS_USB 29 455a989cf6SRahul Sharma #define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A 30 465a989cf6SRahul Sharma #define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A 31 475a989cf6SRahul Sharma #define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A 32 485a989cf6SRahul Sharma #define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B 33 495a989cf6SRahul Sharma #define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B 34 505a989cf6SRahul Sharma #define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B 35 515a989cf6SRahul Sharma #define TOP_MOUT_ACLK_ISP1_266 36 525a989cf6SRahul Sharma #define TOP_MOUT_ISP1_MEDIA_266 37 535a989cf6SRahul Sharma #define TOP_MOUT_ACLK_ISP1_400 38 545a989cf6SRahul Sharma #define TOP_MOUT_ISP1_MEDIA_400 39 555a989cf6SRahul Sharma #define TOP_MOUT_SCLK_ISP1_SPI0 40 565a989cf6SRahul Sharma #define TOP_MOUT_SCLK_ISP1_SPI1 41 575a989cf6SRahul Sharma #define TOP_MOUT_SCLK_ISP1_UART 42 585a989cf6SRahul Sharma #define TOP_MOUT_SCLK_ISP1_SENSOR2 43 595a989cf6SRahul Sharma #define TOP_MOUT_SCLK_ISP1_SENSOR1 44 605a989cf6SRahul Sharma #define TOP_MOUT_SCLK_ISP1_SENSOR0 45 615a989cf6SRahul Sharma #define TOP_MOUT_ACLK_MFC_333 46 625a989cf6SRahul Sharma #define TOP_MOUT_MFC_BUSTOP_333 47 635a989cf6SRahul Sharma #define TOP_MOUT_ACLK_G2D_333 48 645a989cf6SRahul Sharma #define TOP_MOUT_G2D_BUSTOP_333 49 655a989cf6SRahul Sharma #define TOP_MOUT_ACLK_GSCL_FIMC 50 665a989cf6SRahul Sharma #define TOP_MOUT_GSCL_BUSTOP_FIMC 51 675a989cf6SRahul Sharma #define TOP_MOUT_ACLK_GSCL_333 52 685a989cf6SRahul Sharma #define TOP_MOUT_GSCL_BUSTOP_333 53 695a989cf6SRahul Sharma #define TOP_MOUT_ACLK_GSCL_400 54 705a989cf6SRahul Sharma #define TOP_MOUT_M2M_MEDIATOP_400 55 715a989cf6SRahul Sharma #define TOP_DOUT_ACLK_MFC_333 56 725a989cf6SRahul Sharma #define TOP_DOUT_ACLK_G2D_333 57 735a989cf6SRahul Sharma #define TOP_DOUT_SCLK_ISP1_SENSOR2_A 58 745a989cf6SRahul Sharma #define TOP_DOUT_SCLK_ISP1_SENSOR1_A 59 755a989cf6SRahul Sharma #define TOP_DOUT_SCLK_ISP1_SENSOR0_A 60 765a989cf6SRahul Sharma #define TOP_DOUT_ACLK_GSCL_FIMC 61 775a989cf6SRahul Sharma #define TOP_DOUT_ACLK_GSCL_400 62 785a989cf6SRahul Sharma #define TOP_DOUT_ACLK_GSCL_333 63 795a989cf6SRahul Sharma #define TOP_DOUT_SCLK_ISP1_SPI0_B 64 805a989cf6SRahul Sharma #define TOP_DOUT_SCLK_ISP1_SPI0_A 65 815a989cf6SRahul Sharma #define TOP_DOUT_ACLK_ISP1_400 66 825a989cf6SRahul Sharma #define TOP_DOUT_ACLK_ISP1_266 67 835a989cf6SRahul Sharma #define TOP_DOUT_SCLK_ISP1_UART 68 845a989cf6SRahul Sharma #define TOP_DOUT_SCLK_ISP1_SPI1_B 69 855a989cf6SRahul Sharma #define TOP_DOUT_SCLK_ISP1_SPI1_A 70 865a989cf6SRahul Sharma #define TOP_DOUT_SCLK_ISP1_SENSOR2_B 71 875a989cf6SRahul Sharma #define TOP_DOUT_SCLK_ISP1_SENSOR1_B 72 885a989cf6SRahul Sharma #define TOP_DOUT_SCLK_ISP1_SENSOR0_B 73 895a989cf6SRahul Sharma #define TOP_DOUTTOP__SCLK_HPM_TARGETCLK 74 905a989cf6SRahul Sharma #define TOP_DOUT_SCLK_DISP_PIXEL 75 915a989cf6SRahul Sharma #define TOP_DOUT_ACLK_DISP_222 76 925a989cf6SRahul Sharma #define TOP_DOUT_ACLK_DISP_333 77 935a989cf6SRahul Sharma #define TOP_DOUT_ACLK_BUS4_100 78 945a989cf6SRahul Sharma #define TOP_DOUT_ACLK_BUS4_400 79 955a989cf6SRahul Sharma #define TOP_DOUT_ACLK_BUS3_100 80 965a989cf6SRahul Sharma #define TOP_DOUT_ACLK_BUS3_400 81 975a989cf6SRahul Sharma #define TOP_DOUT_ACLK_BUS2_100 82 985a989cf6SRahul Sharma #define TOP_DOUT_ACLK_BUS2_400 83 995a989cf6SRahul Sharma #define TOP_DOUT_ACLK_BUS1_100 84 1005a989cf6SRahul Sharma #define TOP_DOUT_ACLK_BUS1_400 85 1015a989cf6SRahul Sharma #define TOP_DOUT_SCLK_PERI_SPI1_B 86 1025a989cf6SRahul Sharma #define TOP_DOUT_SCLK_PERI_SPI1_A 87 1035a989cf6SRahul Sharma #define TOP_DOUT_SCLK_PERI_SPI0_B 88 1045a989cf6SRahul Sharma #define TOP_DOUT_SCLK_PERI_SPI0_A 89 1055a989cf6SRahul Sharma #define TOP_DOUT_SCLK_PERI_UART0 90 1065a989cf6SRahul Sharma #define TOP_DOUT_SCLK_PERI_UART2 91 1075a989cf6SRahul Sharma #define TOP_DOUT_SCLK_PERI_UART1 92 1085a989cf6SRahul Sharma #define TOP_DOUT_SCLK_PERI_SPI2_B 93 1095a989cf6SRahul Sharma #define TOP_DOUT_SCLK_PERI_SPI2_A 94 1105a989cf6SRahul Sharma #define TOP_DOUT_ACLK_PERI_AUD 95 1115a989cf6SRahul Sharma #define TOP_DOUT_ACLK_PERI_66 96 1125a989cf6SRahul Sharma #define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B 97 1135a989cf6SRahul Sharma #define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A 98 1145a989cf6SRahul Sharma #define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK 99 1155a989cf6SRahul Sharma #define TOP_DOUT_ACLK_FSYS_200 100 1165a989cf6SRahul Sharma #define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B 101 1175a989cf6SRahul Sharma #define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A 102 1185a989cf6SRahul Sharma #define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B 103 1195a989cf6SRahul Sharma #define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A 104 1205a989cf6SRahul Sharma #define TOP_SCLK_FIMD1 105 1215a989cf6SRahul Sharma #define TOP_SCLK_MMC2 106 1225a989cf6SRahul Sharma #define TOP_SCLK_MMC1 107 1235a989cf6SRahul Sharma #define TOP_SCLK_MMC0 108 1245a989cf6SRahul Sharma #define PHYCLK_DPTX_PHY_CH3_TXD_CLK 109 1255a989cf6SRahul Sharma #define PHYCLK_DPTX_PHY_CH2_TXD_CLK 110 1265a989cf6SRahul Sharma #define PHYCLK_DPTX_PHY_CH1_TXD_CLK 111 1275a989cf6SRahul Sharma #define PHYCLK_DPTX_PHY_CH0_TXD_CLK 112 1285a989cf6SRahul Sharma #define phyclk_hdmi_phy_tmds_clko 113 1295a989cf6SRahul Sharma #define PHYCLK_HDMI_PHY_PIXEL_CLKO 114 1305a989cf6SRahul Sharma #define PHYCLK_HDMI_LINK_O_TMDS_CLKHI 115 1315a989cf6SRahul Sharma #define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS 116 1325a989cf6SRahul Sharma #define PHYCLK_DPTX_PHY_O_REF_CLK_24M 117 1335a989cf6SRahul Sharma #define PHYCLK_DPTX_PHY_CLK_DIV2 118 1345a989cf6SRahul Sharma #define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0 119 1355a989cf6SRahul Sharma #define PHYCLK_USBHOST20_PHY_PHYCLOCK 120 1365a989cf6SRahul Sharma #define PHYCLK_USBHOST20_PHY_FREECLK 121 1375a989cf6SRahul Sharma #define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122 1385a989cf6SRahul Sharma #define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123 1395a989cf6SRahul Sharma #define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124 1405a989cf6SRahul Sharma 1415a989cf6SRahul Sharma /* List Of Clocks For CMU_EGL */ 1425a989cf6SRahul Sharma 1435a989cf6SRahul Sharma #define EGL_FOUT_EGL_PLL 1 1445a989cf6SRahul Sharma #define EGL_FOUT_EGL_DPLL 2 1455a989cf6SRahul Sharma #define EGL_MOUT_EGL_B 3 1465a989cf6SRahul Sharma #define EGL_MOUT_EGL_PLL 4 1475a989cf6SRahul Sharma #define EGL_DOUT_EGL_PLL 5 1485a989cf6SRahul Sharma #define EGL_DOUT_EGL_PCLK_DBG 6 1495a989cf6SRahul Sharma #define EGL_DOUT_EGL_ATCLK 7 1505a989cf6SRahul Sharma #define EGL_DOUT_PCLK_EGL 8 1515a989cf6SRahul Sharma #define EGL_DOUT_ACLK_EGL 9 1525a989cf6SRahul Sharma #define EGL_DOUT_EGL2 10 1535a989cf6SRahul Sharma #define EGL_DOUT_EGL1 11 1545a989cf6SRahul Sharma 1555a989cf6SRahul Sharma /* List Of Clocks For CMU_KFC */ 1565a989cf6SRahul Sharma 1575a989cf6SRahul Sharma #define KFC_FOUT_KFC_PLL 1 1585a989cf6SRahul Sharma #define KFC_MOUT_KFC_PLL 2 1595a989cf6SRahul Sharma #define KFC_MOUT_KFC 3 1605a989cf6SRahul Sharma #define KFC_DOUT_KFC_PLL 4 1615a989cf6SRahul Sharma #define KFC_DOUT_PCLK_KFC 5 1625a989cf6SRahul Sharma #define KFC_DOUT_ACLK_KFC 6 1635a989cf6SRahul Sharma #define KFC_DOUT_KFC_PCLK_DBG 7 1645a989cf6SRahul Sharma #define KFC_DOUT_KFC_ATCLK 8 1655a989cf6SRahul Sharma #define KFC_DOUT_KFC2 9 1665a989cf6SRahul Sharma #define KFC_DOUT_KFC1 10 1675a989cf6SRahul Sharma 1685a989cf6SRahul Sharma /* List Of Clocks For CMU_MIF */ 1695a989cf6SRahul Sharma 1705a989cf6SRahul Sharma #define MIF_FOUT_MEM_PLL 1 1715a989cf6SRahul Sharma #define MIF_FOUT_MEDIA_PLL 2 1725a989cf6SRahul Sharma #define MIF_FOUT_BUS_PLL 3 1735a989cf6SRahul Sharma #define MIF_MOUT_CLK2X_PHY 4 1745a989cf6SRahul Sharma #define MIF_MOUT_MIF_DREX2X 5 1755a989cf6SRahul Sharma #define MIF_MOUT_CLKM_PHY 6 1765a989cf6SRahul Sharma #define MIF_MOUT_MIF_DREX 7 1775a989cf6SRahul Sharma #define MIF_MOUT_MEDIA_PLL 8 1785a989cf6SRahul Sharma #define MIF_MOUT_BUS_PLL 9 1795a989cf6SRahul Sharma #define MIF_MOUT_MEM_PLL 10 1805a989cf6SRahul Sharma #define MIF_DOUT_ACLK_BUS_100 11 1815a989cf6SRahul Sharma #define MIF_DOUT_ACLK_BUS_200 12 1825a989cf6SRahul Sharma #define MIF_DOUT_ACLK_MIF_466 13 1835a989cf6SRahul Sharma #define MIF_DOUT_CLK2X_PHY 14 1845a989cf6SRahul Sharma #define MIF_DOUT_CLKM_PHY 15 1855a989cf6SRahul Sharma #define MIF_DOUT_BUS_PLL 16 1865a989cf6SRahul Sharma #define MIF_DOUT_MEM_PLL 17 1875a989cf6SRahul Sharma #define MIF_DOUT_MEDIA_PLL 18 1885a989cf6SRahul Sharma #define MIF_CLK_LPDDR3PHY_WRAP1 19 1895a989cf6SRahul Sharma #define MIF_CLK_LPDDR3PHY_WRAP0 20 1905a989cf6SRahul Sharma #define MIF_CLK_MONOCNT 21 1915a989cf6SRahul Sharma #define MIF_CLK_MIF_RTC 22 1925a989cf6SRahul Sharma #define MIF_CLK_DREX1 23 1935a989cf6SRahul Sharma #define MIF_CLK_DREX0 24 1945a989cf6SRahul Sharma #define MIF_CLK_INTMEM 25 1955a989cf6SRahul Sharma #define MIF_SCLK_LPDDR3PHY_WRAP_U1 26 1965a989cf6SRahul Sharma #define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 1975a989cf6SRahul Sharma 1985a989cf6SRahul Sharma /* List Of Clocks For CMU_G3D */ 1995a989cf6SRahul Sharma 2005a989cf6SRahul Sharma #define G3D_FOUT_G3D_PLL 1 2015a989cf6SRahul Sharma #define G3D_MOUT_G3D_PLL 2 2025a989cf6SRahul Sharma #define G3D_DOUT_PCLK_G3D 3 2035a989cf6SRahul Sharma #define G3D_DOUT_ACLK_G3D 4 2045a989cf6SRahul Sharma #define G3D_CLK_G3D_HPM 5 2055a989cf6SRahul Sharma #define G3D_CLK_G3D 6 2065a989cf6SRahul Sharma 2075a989cf6SRahul Sharma /* List Of Clocks For CMU_AUD */ 2085a989cf6SRahul Sharma 2095a989cf6SRahul Sharma #define AUD_MOUT_SCLK_AUD_PCM 1 2105a989cf6SRahul Sharma #define AUD_MOUT_SCLK_AUD_I2S 2 2115a989cf6SRahul Sharma #define AUD_MOUT_AUD_PLL_USER 3 2125a989cf6SRahul Sharma #define AUD_DOUT_ACLK_AUD_131 4 2135a989cf6SRahul Sharma #define AUD_DOUT_SCLK_AUD_UART 5 2145a989cf6SRahul Sharma #define AUD_DOUT_SCLK_AUD_PCM 6 2155a989cf6SRahul Sharma #define AUD_DOUT_SCLK_AUD_I2S 7 2165a989cf6SRahul Sharma #define AUD_CLK_AUD_UART 8 2175a989cf6SRahul Sharma #define AUD_CLK_PCM 9 2185a989cf6SRahul Sharma #define AUD_CLK_I2S 10 2195a989cf6SRahul Sharma #define AUD_CLK_DMAC 11 2205a989cf6SRahul Sharma #define AUD_CLK_SRAMC 12 2215a989cf6SRahul Sharma #define AUD_SCLK_AUD_UART 13 2225a989cf6SRahul Sharma #define AUD_SCLK_PCM 14 2235a989cf6SRahul Sharma #define AUD_SCLK_I2S 15 2245a989cf6SRahul Sharma 2255a989cf6SRahul Sharma /* List Of Clocks For CMU_MFC */ 2265a989cf6SRahul Sharma 2275a989cf6SRahul Sharma #define MFC_MOUT_ACLK_MFC_333_USER 1 2285a989cf6SRahul Sharma #define MFC_DOUT_PCLK_MFC_83 2 2295a989cf6SRahul Sharma #define MFC_CLK_MFC 3 2305a989cf6SRahul Sharma #define MFC_CLK_SMMU2_MFCM1 4 2315a989cf6SRahul Sharma #define MFC_CLK_SMMU2_MFCM0 5 2325a989cf6SRahul Sharma 2335a989cf6SRahul Sharma /* List Of Clocks For CMU_GSCL */ 2345a989cf6SRahul Sharma 2355a989cf6SRahul Sharma #define GSCL_MOUT_ACLK_CSIS 1 2365a989cf6SRahul Sharma #define GSCL_MOUT_ACLK_GSCL_FIMC_USER 2 2375a989cf6SRahul Sharma #define GSCL_MOUT_ACLK_M2M_400_USER 3 2385a989cf6SRahul Sharma #define GSCL_MOUT_ACLK_GSCL_333_USER 4 2395a989cf6SRahul Sharma #define GSCL_DOUT_ACLK_CSIS_200 5 2405a989cf6SRahul Sharma #define GSCL_DOUT_PCLK_M2M_100 6 2415a989cf6SRahul Sharma #define GSCL_CLK_PIXEL_GSCL1 7 2425a989cf6SRahul Sharma #define GSCL_CLK_PIXEL_GSCL0 8 2435a989cf6SRahul Sharma #define GSCL_CLK_MSCL1 9 2445a989cf6SRahul Sharma #define GSCL_CLK_MSCL0 10 2455a989cf6SRahul Sharma #define GSCL_CLK_GSCL1 11 2465a989cf6SRahul Sharma #define GSCL_CLK_GSCL0 12 2475a989cf6SRahul Sharma #define GSCL_CLK_FIMC_LITE_D 13 2485a989cf6SRahul Sharma #define GSCL_CLK_FIMC_LITE_B 14 2495a989cf6SRahul Sharma #define GSCL_CLK_FIMC_LITE_A 15 2505a989cf6SRahul Sharma #define GSCL_CLK_CSIS1 16 2515a989cf6SRahul Sharma #define GSCL_CLK_CSIS0 17 2525a989cf6SRahul Sharma #define GSCL_CLK_SMMU3_LITE_D 18 2535a989cf6SRahul Sharma #define GSCL_CLK_SMMU3_LITE_B 19 2545a989cf6SRahul Sharma #define GSCL_CLK_SMMU3_LITE_A 20 2555a989cf6SRahul Sharma #define GSCL_CLK_SMMU3_GSCL0 21 2565a989cf6SRahul Sharma #define GSCL_CLK_SMMU3_GSCL1 22 2575a989cf6SRahul Sharma #define GSCL_CLK_SMMU3_MSCL0 23 2585a989cf6SRahul Sharma #define GSCL_CLK_SMMU3_MSCL1 24 2595a989cf6SRahul Sharma #define GSCL_SCLK_CSIS1_WRAP 25 2605a989cf6SRahul Sharma #define GSCL_SCLK_CSIS0_WRAP 26 2615a989cf6SRahul Sharma 2625a989cf6SRahul Sharma /* List Of Clocks For CMU_FSYS */ 2635a989cf6SRahul Sharma 2645a989cf6SRahul Sharma #define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER 1 2655a989cf6SRahul Sharma #define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER 2 2665a989cf6SRahul Sharma #define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER 3 2675a989cf6SRahul Sharma #define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER 4 2685a989cf6SRahul Sharma #define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER 5 2695a989cf6SRahul Sharma #define FSYS_CLK_TSI 6 2705a989cf6SRahul Sharma #define FSYS_CLK_USBLINK 7 2715a989cf6SRahul Sharma #define FSYS_CLK_USBHOST20 8 2725a989cf6SRahul Sharma #define FSYS_CLK_USBDRD30 9 2735a989cf6SRahul Sharma #define FSYS_CLK_SROMC 10 2745a989cf6SRahul Sharma #define FSYS_CLK_PDMA 11 2755a989cf6SRahul Sharma #define FSYS_CLK_MMC2 12 2765a989cf6SRahul Sharma #define FSYS_CLK_MMC1 13 2775a989cf6SRahul Sharma #define FSYS_CLK_MMC0 14 2785a989cf6SRahul Sharma #define FSYS_CLK_RTIC 15 2795a989cf6SRahul Sharma #define FSYS_CLK_SMMU_RTIC 16 2805a989cf6SRahul Sharma #define FSYS_PHYCLK_USBDRD30 17 2815a989cf6SRahul Sharma #define FSYS_PHYCLK_USBHOST20 18 2825a989cf6SRahul Sharma 2835a989cf6SRahul Sharma /* List Of Clocks For CMU_PERI */ 2845a989cf6SRahul Sharma 2855a989cf6SRahul Sharma #define PERI_MOUT_SCLK_SPDIF 1 2865a989cf6SRahul Sharma #define PERI_MOUT_SCLK_I2SCOD 2 2875a989cf6SRahul Sharma #define PERI_MOUT_SCLK_PCM 3 2885a989cf6SRahul Sharma #define PERI_DOUT_I2S 4 2895a989cf6SRahul Sharma #define PERI_DOUT_PCM 5 2905a989cf6SRahul Sharma #define PERI_CLK_WDT_KFC 6 2915a989cf6SRahul Sharma #define PERI_CLK_WDT_EGL 7 2925a989cf6SRahul Sharma #define PERI_CLK_HSIC3 8 2935a989cf6SRahul Sharma #define PERI_CLK_HSIC2 9 2945a989cf6SRahul Sharma #define PERI_CLK_HSIC1 10 2955a989cf6SRahul Sharma #define PERI_CLK_HSIC0 11 2965a989cf6SRahul Sharma #define PERI_CLK_PCM 12 2975a989cf6SRahul Sharma #define PERI_CLK_MCT 13 2985a989cf6SRahul Sharma #define PERI_CLK_I2S 14 2995a989cf6SRahul Sharma #define PERI_CLK_I2CHDMI 15 3005a989cf6SRahul Sharma #define PERI_CLK_I2C7 16 3015a989cf6SRahul Sharma #define PERI_CLK_I2C6 17 3025a989cf6SRahul Sharma #define PERI_CLK_I2C5 18 3035a989cf6SRahul Sharma #define PERI_CLK_I2C4 19 3045a989cf6SRahul Sharma #define PERI_CLK_I2C9 20 3055a989cf6SRahul Sharma #define PERI_CLK_I2C8 21 3065a989cf6SRahul Sharma #define PERI_CLK_I2C11 22 3075a989cf6SRahul Sharma #define PERI_CLK_I2C10 23 3085a989cf6SRahul Sharma #define PERI_CLK_HDMICEC 24 3095a989cf6SRahul Sharma #define PERI_CLK_EFUSE_WRITER 25 3105a989cf6SRahul Sharma #define PERI_CLK_ABB 26 3115a989cf6SRahul Sharma #define PERI_CLK_UART2 27 3125a989cf6SRahul Sharma #define PERI_CLK_UART1 28 3135a989cf6SRahul Sharma #define PERI_CLK_UART0 29 3145a989cf6SRahul Sharma #define PERI_CLK_ADC 30 3155a989cf6SRahul Sharma #define PERI_CLK_TMU4 31 3165a989cf6SRahul Sharma #define PERI_CLK_TMU3 32 3175a989cf6SRahul Sharma #define PERI_CLK_TMU2 33 3185a989cf6SRahul Sharma #define PERI_CLK_TMU1 34 3195a989cf6SRahul Sharma #define PERI_CLK_TMU0 35 3205a989cf6SRahul Sharma #define PERI_CLK_SPI2 36 3215a989cf6SRahul Sharma #define PERI_CLK_SPI1 37 3225a989cf6SRahul Sharma #define PERI_CLK_SPI0 38 3235a989cf6SRahul Sharma #define PERI_CLK_SPDIF 39 3245a989cf6SRahul Sharma #define PERI_CLK_PWM 40 3255a989cf6SRahul Sharma #define PERI_CLK_UART4 41 3265a989cf6SRahul Sharma #define PERI_CLK_CHIPID 42 3275a989cf6SRahul Sharma #define PERI_CLK_PROVKEY0 43 3285a989cf6SRahul Sharma #define PERI_CLK_PROVKEY1 44 3295a989cf6SRahul Sharma #define PERI_CLK_SECKEY 45 3305a989cf6SRahul Sharma #define PERI_CLK_TOP_RTC 46 3315a989cf6SRahul Sharma #define PERI_CLK_TZPC10 47 3325a989cf6SRahul Sharma #define PERI_CLK_TZPC9 48 3335a989cf6SRahul Sharma #define PERI_CLK_TZPC8 49 3345a989cf6SRahul Sharma #define PERI_CLK_TZPC7 50 3355a989cf6SRahul Sharma #define PERI_CLK_TZPC6 51 3365a989cf6SRahul Sharma #define PERI_CLK_TZPC5 52 3375a989cf6SRahul Sharma #define PERI_CLK_TZPC4 53 3385a989cf6SRahul Sharma #define PERI_CLK_TZPC3 54 3395a989cf6SRahul Sharma #define PERI_CLK_TZPC2 55 3405a989cf6SRahul Sharma #define PERI_CLK_TZPC1 56 3415a989cf6SRahul Sharma #define PERI_CLK_TZPC0 57 3425a989cf6SRahul Sharma #define PERI_SCLK_UART2 58 3435a989cf6SRahul Sharma #define PERI_SCLK_UART1 59 3445a989cf6SRahul Sharma #define PERI_SCLK_UART0 60 3455a989cf6SRahul Sharma #define PERI_SCLK_SPI2 61 3465a989cf6SRahul Sharma #define PERI_SCLK_SPI1 62 3475a989cf6SRahul Sharma #define PERI_SCLK_SPI0 63 3485a989cf6SRahul Sharma #define PERI_SCLK_SPDIF 64 3495a989cf6SRahul Sharma #define PERI_SCLK_I2S 65 3505a989cf6SRahul Sharma #define PERI_SCLK_PCM1 66 3515a989cf6SRahul Sharma 3525a989cf6SRahul Sharma /* List Of Clocks For CMU_DISP */ 3535a989cf6SRahul Sharma 3545a989cf6SRahul Sharma #define DISP_MOUT_SCLK_HDMI_SPDIF 1 3555a989cf6SRahul Sharma #define DISP_MOUT_SCLK_HDMI_PIXEL 2 3565a989cf6SRahul Sharma #define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER 3 3575a989cf6SRahul Sharma #define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER 4 3585a989cf6SRahul Sharma #define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER 5 3595a989cf6SRahul Sharma #define DISP_MOUT_HDMI_PHY_PIXEL 6 3605a989cf6SRahul Sharma #define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER 7 3615a989cf6SRahul Sharma #define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS 8 3625a989cf6SRahul Sharma #define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER 9 3635a989cf6SRahul Sharma #define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER 10 3645a989cf6SRahul Sharma #define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER 11 3655a989cf6SRahul Sharma #define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER 12 3665a989cf6SRahul Sharma #define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER 13 3675a989cf6SRahul Sharma #define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER 14 3685a989cf6SRahul Sharma #define DISP_MOUT_ACLK_DISP_222_USER 15 3695a989cf6SRahul Sharma #define DISP_MOUT_SCLK_DISP_PIXEL_USER 16 3705a989cf6SRahul Sharma #define DISP_MOUT_ACLK_DISP_333_USER 17 3715a989cf6SRahul Sharma #define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI 18 3725a989cf6SRahul Sharma #define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL 19 3735a989cf6SRahul Sharma #define DISP_DOUT_PCLK_DISP_111 20 3745a989cf6SRahul Sharma #define DISP_CLK_SMMU_TV 21 3755a989cf6SRahul Sharma #define DISP_CLK_SMMU_FIMD1M1 22 3765a989cf6SRahul Sharma #define DISP_CLK_SMMU_FIMD1M0 23 3775a989cf6SRahul Sharma #define DISP_CLK_PIXEL_MIXER 24 3785a989cf6SRahul Sharma #define DISP_CLK_PIXEL_DISP 25 3795a989cf6SRahul Sharma #define DISP_CLK_MIXER 26 3805a989cf6SRahul Sharma #define DISP_CLK_MIPIPHY 27 3815a989cf6SRahul Sharma #define DISP_CLK_HDMIPHY 28 3825a989cf6SRahul Sharma #define DISP_CLK_HDMI 29 3835a989cf6SRahul Sharma #define DISP_CLK_FIMD1 30 3845a989cf6SRahul Sharma #define DISP_CLK_DSIM1 31 3855a989cf6SRahul Sharma #define DISP_CLK_DPPHY 32 3865a989cf6SRahul Sharma #define DISP_CLK_DP 33 3875a989cf6SRahul Sharma #define DISP_SCLK_PIXEL 34 3885a989cf6SRahul Sharma #define DISP_MOUT_HDMI_PHY_PIXEL_USER 35 3895a989cf6SRahul Sharma 3905a989cf6SRahul Sharma /* List Of Clocks For CMU_G2D */ 3915a989cf6SRahul Sharma 3925a989cf6SRahul Sharma #define G2D_MOUT_ACLK_G2D_333_USER 1 3935a989cf6SRahul Sharma #define G2D_DOUT_PCLK_G2D_83 2 3945a989cf6SRahul Sharma #define G2D_CLK_SMMU3_JPEG 3 3955a989cf6SRahul Sharma #define G2D_CLK_MDMA 4 3965a989cf6SRahul Sharma #define G2D_CLK_JPEG 5 3975a989cf6SRahul Sharma #define G2D_CLK_G2D 6 3985a989cf6SRahul Sharma #define G2D_CLK_SSS 7 3995a989cf6SRahul Sharma #define G2D_CLK_SLIM_SSS 8 4005a989cf6SRahul Sharma #define G2D_CLK_SMMU_SLIM_SSS 9 4015a989cf6SRahul Sharma #define G2D_CLK_SMMU_SSS 10 4025a989cf6SRahul Sharma #define G2D_CLK_SMMU_MDMA 11 4035a989cf6SRahul Sharma #define G2D_CLK_SMMU3_G2D 12 4045a989cf6SRahul Sharma 4055a989cf6SRahul Sharma /* List Of Clocks For CMU_ISP */ 4065a989cf6SRahul Sharma 4075a989cf6SRahul Sharma #define ISP_MOUT_ISP_400_USER 1 4085a989cf6SRahul Sharma #define ISP_MOUT_ISP_266_USER 2 4095a989cf6SRahul Sharma #define ISP_DOUT_SCLK_MPWM 3 4105a989cf6SRahul Sharma #define ISP_DOUT_CA5_PCLKDBG 4 4115a989cf6SRahul Sharma #define ISP_DOUT_CA5_ATCLKIN 5 4125a989cf6SRahul Sharma #define ISP_DOUT_PCLK_ISP_133 6 4135a989cf6SRahul Sharma #define ISP_DOUT_PCLK_ISP_66 7 4145a989cf6SRahul Sharma #define ISP_CLK_GIC 8 4155a989cf6SRahul Sharma #define ISP_CLK_WDT 9 4165a989cf6SRahul Sharma #define ISP_CLK_UART 10 4175a989cf6SRahul Sharma #define ISP_CLK_SPI1 11 4185a989cf6SRahul Sharma #define ISP_CLK_SPI0 12 4195a989cf6SRahul Sharma #define ISP_CLK_SMMU_SCALERP 13 4205a989cf6SRahul Sharma #define ISP_CLK_SMMU_SCALERC 14 4215a989cf6SRahul Sharma #define ISP_CLK_SMMU_ISPCX 15 4225a989cf6SRahul Sharma #define ISP_CLK_SMMU_ISP 16 4235a989cf6SRahul Sharma #define ISP_CLK_SMMU_FD 17 4245a989cf6SRahul Sharma #define ISP_CLK_SMMU_DRC 18 4255a989cf6SRahul Sharma #define ISP_CLK_PWM 19 4265a989cf6SRahul Sharma #define ISP_CLK_MTCADC 20 4275a989cf6SRahul Sharma #define ISP_CLK_MPWM 21 4285a989cf6SRahul Sharma #define ISP_CLK_MCUCTL 22 4295a989cf6SRahul Sharma #define ISP_CLK_I2C1 23 4305a989cf6SRahul Sharma #define ISP_CLK_I2C0 24 4315a989cf6SRahul Sharma #define ISP_CLK_FIMC_SCALERP 25 4325a989cf6SRahul Sharma #define ISP_CLK_FIMC_SCALERC 26 4335a989cf6SRahul Sharma #define ISP_CLK_FIMC 27 4345a989cf6SRahul Sharma #define ISP_CLK_FIMC_FD 28 4355a989cf6SRahul Sharma #define ISP_CLK_FIMC_DRC 29 4365a989cf6SRahul Sharma #define ISP_CLK_CA5 30 4375a989cf6SRahul Sharma #define ISP_SCLK_SPI0_EXT 31 4385a989cf6SRahul Sharma #define ISP_SCLK_SPI1_EXT 32 4395a989cf6SRahul Sharma #define ISP_SCLK_UART_EXT 33 4405a989cf6SRahul Sharma 4415a989cf6SRahul Sharma #endif 442