1b568059bSAndrzej Hajda /* 2b568059bSAndrzej Hajda * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3f65d5189STomasz Figa * Author: Andrzej Hajda <a.hajda@samsung.com> 4b568059bSAndrzej Hajda * 5b568059bSAndrzej Hajda * This program is free software; you can redistribute it and/or modify 6b568059bSAndrzej Hajda * it under the terms of the GNU General Public License version 2 as 7b568059bSAndrzej Hajda * published by the Free Software Foundation. 8b568059bSAndrzej Hajda * 9b568059bSAndrzej Hajda * Device Tree binding constants for Exynos5250 clock controller. 10b568059bSAndrzej Hajda */ 11b568059bSAndrzej Hajda 12b568059bSAndrzej Hajda #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H 13b568059bSAndrzej Hajda #define _DT_BINDINGS_CLOCK_EXYNOS_5250_H 14b568059bSAndrzej Hajda 15b568059bSAndrzej Hajda /* core clocks */ 16b568059bSAndrzej Hajda #define CLK_FIN_PLL 1 17b568059bSAndrzej Hajda #define CLK_FOUT_APLL 2 18b568059bSAndrzej Hajda #define CLK_FOUT_MPLL 3 19b568059bSAndrzej Hajda #define CLK_FOUT_BPLL 4 20b568059bSAndrzej Hajda #define CLK_FOUT_GPLL 5 21b568059bSAndrzej Hajda #define CLK_FOUT_CPLL 6 22b568059bSAndrzej Hajda #define CLK_FOUT_EPLL 7 23b568059bSAndrzej Hajda #define CLK_FOUT_VPLL 8 24b568059bSAndrzej Hajda 25b568059bSAndrzej Hajda /* gate for special clocks (sclk) */ 26b568059bSAndrzej Hajda #define CLK_SCLK_CAM_BAYER 128 27b568059bSAndrzej Hajda #define CLK_SCLK_CAM0 129 28b568059bSAndrzej Hajda #define CLK_SCLK_CAM1 130 29b568059bSAndrzej Hajda #define CLK_SCLK_GSCL_WA 131 30b568059bSAndrzej Hajda #define CLK_SCLK_GSCL_WB 132 31b568059bSAndrzej Hajda #define CLK_SCLK_FIMD1 133 32b568059bSAndrzej Hajda #define CLK_SCLK_MIPI1 134 33b568059bSAndrzej Hajda #define CLK_SCLK_DP 135 34b568059bSAndrzej Hajda #define CLK_SCLK_HDMI 136 35b568059bSAndrzej Hajda #define CLK_SCLK_PIXEL 137 36b568059bSAndrzej Hajda #define CLK_SCLK_AUDIO0 138 37b568059bSAndrzej Hajda #define CLK_SCLK_MMC0 139 38b568059bSAndrzej Hajda #define CLK_SCLK_MMC1 140 39b568059bSAndrzej Hajda #define CLK_SCLK_MMC2 141 40b568059bSAndrzej Hajda #define CLK_SCLK_MMC3 142 41b568059bSAndrzej Hajda #define CLK_SCLK_SATA 143 42b568059bSAndrzej Hajda #define CLK_SCLK_USB3 144 43b568059bSAndrzej Hajda #define CLK_SCLK_JPEG 145 44b568059bSAndrzej Hajda #define CLK_SCLK_UART0 146 45b568059bSAndrzej Hajda #define CLK_SCLK_UART1 147 46b568059bSAndrzej Hajda #define CLK_SCLK_UART2 148 47b568059bSAndrzej Hajda #define CLK_SCLK_UART3 149 48b568059bSAndrzej Hajda #define CLK_SCLK_PWM 150 49b568059bSAndrzej Hajda #define CLK_SCLK_AUDIO1 151 50b568059bSAndrzej Hajda #define CLK_SCLK_AUDIO2 152 51b568059bSAndrzej Hajda #define CLK_SCLK_SPDIF 153 52b568059bSAndrzej Hajda #define CLK_SCLK_SPI0 154 53b568059bSAndrzej Hajda #define CLK_SCLK_SPI1 155 54b568059bSAndrzej Hajda #define CLK_SCLK_SPI2 156 55b568059bSAndrzej Hajda #define CLK_DIV_I2S1 157 56b568059bSAndrzej Hajda #define CLK_DIV_I2S2 158 57b568059bSAndrzej Hajda #define CLK_SCLK_HDMIPHY 159 5835399ddaSAndrew Bresticker #define CLK_DIV_PCM0 160 59b568059bSAndrzej Hajda 60b568059bSAndrzej Hajda /* gate clocks */ 61b568059bSAndrzej Hajda #define CLK_GSCL0 256 62b568059bSAndrzej Hajda #define CLK_GSCL1 257 63b568059bSAndrzej Hajda #define CLK_GSCL2 258 64b568059bSAndrzej Hajda #define CLK_GSCL3 259 65b568059bSAndrzej Hajda #define CLK_GSCL_WA 260 66b568059bSAndrzej Hajda #define CLK_GSCL_WB 261 67b568059bSAndrzej Hajda #define CLK_SMMU_GSCL0 262 68b568059bSAndrzej Hajda #define CLK_SMMU_GSCL1 263 69b568059bSAndrzej Hajda #define CLK_SMMU_GSCL2 264 70b568059bSAndrzej Hajda #define CLK_SMMU_GSCL3 265 71b568059bSAndrzej Hajda #define CLK_MFC 266 72b568059bSAndrzej Hajda #define CLK_SMMU_MFCL 267 73b568059bSAndrzej Hajda #define CLK_SMMU_MFCR 268 74b568059bSAndrzej Hajda #define CLK_ROTATOR 269 75b568059bSAndrzej Hajda #define CLK_JPEG 270 76b568059bSAndrzej Hajda #define CLK_MDMA1 271 77b568059bSAndrzej Hajda #define CLK_SMMU_ROTATOR 272 78b568059bSAndrzej Hajda #define CLK_SMMU_JPEG 273 79b568059bSAndrzej Hajda #define CLK_SMMU_MDMA1 274 80b568059bSAndrzej Hajda #define CLK_PDMA0 275 81b568059bSAndrzej Hajda #define CLK_PDMA1 276 82b568059bSAndrzej Hajda #define CLK_SATA 277 83b568059bSAndrzej Hajda #define CLK_USBOTG 278 84b568059bSAndrzej Hajda #define CLK_MIPI_HSI 279 85b568059bSAndrzej Hajda #define CLK_SDMMC0 280 86b568059bSAndrzej Hajda #define CLK_SDMMC1 281 87b568059bSAndrzej Hajda #define CLK_SDMMC2 282 88b568059bSAndrzej Hajda #define CLK_SDMMC3 283 89b568059bSAndrzej Hajda #define CLK_SROMC 284 90b568059bSAndrzej Hajda #define CLK_USB2 285 91b568059bSAndrzej Hajda #define CLK_USB3 286 92b568059bSAndrzej Hajda #define CLK_SATA_PHYCTRL 287 93b568059bSAndrzej Hajda #define CLK_SATA_PHYI2C 288 94b568059bSAndrzej Hajda #define CLK_UART0 289 95b568059bSAndrzej Hajda #define CLK_UART1 290 96b568059bSAndrzej Hajda #define CLK_UART2 291 97b568059bSAndrzej Hajda #define CLK_UART3 292 98b568059bSAndrzej Hajda #define CLK_UART4 293 99b568059bSAndrzej Hajda #define CLK_I2C0 294 100b568059bSAndrzej Hajda #define CLK_I2C1 295 101b568059bSAndrzej Hajda #define CLK_I2C2 296 102b568059bSAndrzej Hajda #define CLK_I2C3 297 103b568059bSAndrzej Hajda #define CLK_I2C4 298 104b568059bSAndrzej Hajda #define CLK_I2C5 299 105b568059bSAndrzej Hajda #define CLK_I2C6 300 106b568059bSAndrzej Hajda #define CLK_I2C7 301 107b568059bSAndrzej Hajda #define CLK_I2C_HDMI 302 108b568059bSAndrzej Hajda #define CLK_ADC 303 109b568059bSAndrzej Hajda #define CLK_SPI0 304 110b568059bSAndrzej Hajda #define CLK_SPI1 305 111b568059bSAndrzej Hajda #define CLK_SPI2 306 112b568059bSAndrzej Hajda #define CLK_I2S1 307 113b568059bSAndrzej Hajda #define CLK_I2S2 308 114b568059bSAndrzej Hajda #define CLK_PCM1 309 115b568059bSAndrzej Hajda #define CLK_PCM2 310 116b568059bSAndrzej Hajda #define CLK_PWM 311 117b568059bSAndrzej Hajda #define CLK_SPDIF 312 118b568059bSAndrzej Hajda #define CLK_AC97 313 119b568059bSAndrzej Hajda #define CLK_HSI2C0 314 120b568059bSAndrzej Hajda #define CLK_HSI2C1 315 121b568059bSAndrzej Hajda #define CLK_HSI2C2 316 122b568059bSAndrzej Hajda #define CLK_HSI2C3 317 123b568059bSAndrzej Hajda #define CLK_CHIPID 318 124b568059bSAndrzej Hajda #define CLK_SYSREG 319 125b568059bSAndrzej Hajda #define CLK_PMU 320 126b568059bSAndrzej Hajda #define CLK_CMU_TOP 321 127b568059bSAndrzej Hajda #define CLK_CMU_CORE 322 128b568059bSAndrzej Hajda #define CLK_CMU_MEM 323 129b568059bSAndrzej Hajda #define CLK_TZPC0 324 130b568059bSAndrzej Hajda #define CLK_TZPC1 325 131b568059bSAndrzej Hajda #define CLK_TZPC2 326 132b568059bSAndrzej Hajda #define CLK_TZPC3 327 133b568059bSAndrzej Hajda #define CLK_TZPC4 328 134b568059bSAndrzej Hajda #define CLK_TZPC5 329 135b568059bSAndrzej Hajda #define CLK_TZPC6 330 136b568059bSAndrzej Hajda #define CLK_TZPC7 331 137b568059bSAndrzej Hajda #define CLK_TZPC8 332 138b568059bSAndrzej Hajda #define CLK_TZPC9 333 139b568059bSAndrzej Hajda #define CLK_HDMI_CEC 334 140b568059bSAndrzej Hajda #define CLK_MCT 335 141b568059bSAndrzej Hajda #define CLK_WDT 336 142b568059bSAndrzej Hajda #define CLK_RTC 337 143b568059bSAndrzej Hajda #define CLK_TMU 338 144b568059bSAndrzej Hajda #define CLK_FIMD1 339 145b568059bSAndrzej Hajda #define CLK_MIE1 340 146b568059bSAndrzej Hajda #define CLK_DSIM0 341 147b568059bSAndrzej Hajda #define CLK_DP 342 148b568059bSAndrzej Hajda #define CLK_MIXER 343 149b568059bSAndrzej Hajda #define CLK_HDMI 344 150b568059bSAndrzej Hajda #define CLK_G2D 345 151b568059bSAndrzej Hajda #define CLK_MDMA0 346 152b568059bSAndrzej Hajda #define CLK_SMMU_MDMA0 347 1535b73721bSNaveen Krishna Chatradhi #define CLK_SSS 348 15420b82ae2SArun Kumar K #define CLK_G3D 349 155bfed1074SCho KyongHo #define CLK_SMMU_TV 350 156bfed1074SCho KyongHo #define CLK_SMMU_FIMD1 351 157bfed1074SCho KyongHo #define CLK_SMMU_2D 352 158bfed1074SCho KyongHo #define CLK_SMMU_FIMC_ISP 353 159bfed1074SCho KyongHo #define CLK_SMMU_FIMC_DRC 354 160bfed1074SCho KyongHo #define CLK_SMMU_FIMC_SCC 355 161bfed1074SCho KyongHo #define CLK_SMMU_FIMC_SCP 356 162bfed1074SCho KyongHo #define CLK_SMMU_FIMC_FD 357 163bfed1074SCho KyongHo #define CLK_SMMU_FIMC_MCU 358 164bfed1074SCho KyongHo #define CLK_SMMU_FIMC_ODC 359 165bfed1074SCho KyongHo #define CLK_SMMU_FIMC_DIS0 360 166bfed1074SCho KyongHo #define CLK_SMMU_FIMC_DIS1 361 167bfed1074SCho KyongHo #define CLK_SMMU_FIMC_3DNR 362 168bfed1074SCho KyongHo #define CLK_SMMU_FIMC_LITE0 363 169bfed1074SCho KyongHo #define CLK_SMMU_FIMC_LITE1 364 170bfed1074SCho KyongHo #define CLK_CAMIF_TOP 365 171b568059bSAndrzej Hajda 172b568059bSAndrzej Hajda /* mux clocks */ 173b568059bSAndrzej Hajda #define CLK_MOUT_HDMI 1024 17420b82ae2SArun Kumar K #define CLK_MOUT_GPLL 1025 175b568059bSAndrzej Hajda 176b568059bSAndrzej Hajda /* must be greater than maximal clock id */ 17720b82ae2SArun Kumar K #define CLK_NR_CLKS 1026 178b568059bSAndrzej Hajda 179b568059bSAndrzej Hajda #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ 180