1cd9102e9SKrzysztof Kozlowski /* SPDX-License-Identifier: GPL-2.0 */ 2b568059bSAndrzej Hajda /* 3b568059bSAndrzej Hajda * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4f65d5189STomasz Figa * Author: Andrzej Hajda <a.hajda@samsung.com> 5b568059bSAndrzej Hajda * 6b568059bSAndrzej Hajda * Device Tree binding constants for Exynos5250 clock controller. 7b568059bSAndrzej Hajda */ 8b568059bSAndrzej Hajda 9b568059bSAndrzej Hajda #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H 10b568059bSAndrzej Hajda #define _DT_BINDINGS_CLOCK_EXYNOS_5250_H 11b568059bSAndrzej Hajda 12b568059bSAndrzej Hajda /* core clocks */ 13b568059bSAndrzej Hajda #define CLK_FIN_PLL 1 14b568059bSAndrzej Hajda #define CLK_FOUT_APLL 2 15b568059bSAndrzej Hajda #define CLK_FOUT_MPLL 3 16b568059bSAndrzej Hajda #define CLK_FOUT_BPLL 4 17b568059bSAndrzej Hajda #define CLK_FOUT_GPLL 5 18b568059bSAndrzej Hajda #define CLK_FOUT_CPLL 6 19b568059bSAndrzej Hajda #define CLK_FOUT_EPLL 7 20b568059bSAndrzej Hajda #define CLK_FOUT_VPLL 8 21d7cc4c81SThomas Abraham #define CLK_ARM_CLK 9 22b568059bSAndrzej Hajda 23b568059bSAndrzej Hajda /* gate for special clocks (sclk) */ 24b568059bSAndrzej Hajda #define CLK_SCLK_CAM_BAYER 128 25b568059bSAndrzej Hajda #define CLK_SCLK_CAM0 129 26b568059bSAndrzej Hajda #define CLK_SCLK_CAM1 130 27b568059bSAndrzej Hajda #define CLK_SCLK_GSCL_WA 131 28b568059bSAndrzej Hajda #define CLK_SCLK_GSCL_WB 132 29b568059bSAndrzej Hajda #define CLK_SCLK_FIMD1 133 30b568059bSAndrzej Hajda #define CLK_SCLK_MIPI1 134 31b568059bSAndrzej Hajda #define CLK_SCLK_DP 135 32b568059bSAndrzej Hajda #define CLK_SCLK_HDMI 136 33b568059bSAndrzej Hajda #define CLK_SCLK_PIXEL 137 34b568059bSAndrzej Hajda #define CLK_SCLK_AUDIO0 138 35b568059bSAndrzej Hajda #define CLK_SCLK_MMC0 139 36b568059bSAndrzej Hajda #define CLK_SCLK_MMC1 140 37b568059bSAndrzej Hajda #define CLK_SCLK_MMC2 141 38b568059bSAndrzej Hajda #define CLK_SCLK_MMC3 142 39b568059bSAndrzej Hajda #define CLK_SCLK_SATA 143 40b568059bSAndrzej Hajda #define CLK_SCLK_USB3 144 41b568059bSAndrzej Hajda #define CLK_SCLK_JPEG 145 42b568059bSAndrzej Hajda #define CLK_SCLK_UART0 146 43b568059bSAndrzej Hajda #define CLK_SCLK_UART1 147 44b568059bSAndrzej Hajda #define CLK_SCLK_UART2 148 45b568059bSAndrzej Hajda #define CLK_SCLK_UART3 149 46b568059bSAndrzej Hajda #define CLK_SCLK_PWM 150 47b568059bSAndrzej Hajda #define CLK_SCLK_AUDIO1 151 48b568059bSAndrzej Hajda #define CLK_SCLK_AUDIO2 152 49b568059bSAndrzej Hajda #define CLK_SCLK_SPDIF 153 50b568059bSAndrzej Hajda #define CLK_SCLK_SPI0 154 51b568059bSAndrzej Hajda #define CLK_SCLK_SPI1 155 52b568059bSAndrzej Hajda #define CLK_SCLK_SPI2 156 53b568059bSAndrzej Hajda #define CLK_DIV_I2S1 157 54b568059bSAndrzej Hajda #define CLK_DIV_I2S2 158 55b568059bSAndrzej Hajda #define CLK_SCLK_HDMIPHY 159 5635399ddaSAndrew Bresticker #define CLK_DIV_PCM0 160 57b568059bSAndrzej Hajda 58b568059bSAndrzej Hajda /* gate clocks */ 59b568059bSAndrzej Hajda #define CLK_GSCL0 256 60b568059bSAndrzej Hajda #define CLK_GSCL1 257 61b568059bSAndrzej Hajda #define CLK_GSCL2 258 62b568059bSAndrzej Hajda #define CLK_GSCL3 259 63b568059bSAndrzej Hajda #define CLK_GSCL_WA 260 64b568059bSAndrzej Hajda #define CLK_GSCL_WB 261 65b568059bSAndrzej Hajda #define CLK_SMMU_GSCL0 262 66b568059bSAndrzej Hajda #define CLK_SMMU_GSCL1 263 67b568059bSAndrzej Hajda #define CLK_SMMU_GSCL2 264 68b568059bSAndrzej Hajda #define CLK_SMMU_GSCL3 265 69b568059bSAndrzej Hajda #define CLK_MFC 266 70b568059bSAndrzej Hajda #define CLK_SMMU_MFCL 267 71b568059bSAndrzej Hajda #define CLK_SMMU_MFCR 268 72b568059bSAndrzej Hajda #define CLK_ROTATOR 269 73b568059bSAndrzej Hajda #define CLK_JPEG 270 74b568059bSAndrzej Hajda #define CLK_MDMA1 271 75b568059bSAndrzej Hajda #define CLK_SMMU_ROTATOR 272 76b568059bSAndrzej Hajda #define CLK_SMMU_JPEG 273 77b568059bSAndrzej Hajda #define CLK_SMMU_MDMA1 274 78b568059bSAndrzej Hajda #define CLK_PDMA0 275 79b568059bSAndrzej Hajda #define CLK_PDMA1 276 80b568059bSAndrzej Hajda #define CLK_SATA 277 81b568059bSAndrzej Hajda #define CLK_USBOTG 278 82b568059bSAndrzej Hajda #define CLK_MIPI_HSI 279 83b568059bSAndrzej Hajda #define CLK_SDMMC0 280 84b568059bSAndrzej Hajda #define CLK_SDMMC1 281 85b568059bSAndrzej Hajda #define CLK_SDMMC2 282 86b568059bSAndrzej Hajda #define CLK_SDMMC3 283 87b568059bSAndrzej Hajda #define CLK_SROMC 284 88b568059bSAndrzej Hajda #define CLK_USB2 285 89b568059bSAndrzej Hajda #define CLK_USB3 286 90b568059bSAndrzej Hajda #define CLK_SATA_PHYCTRL 287 91b568059bSAndrzej Hajda #define CLK_SATA_PHYI2C 288 92b568059bSAndrzej Hajda #define CLK_UART0 289 93b568059bSAndrzej Hajda #define CLK_UART1 290 94b568059bSAndrzej Hajda #define CLK_UART2 291 95b568059bSAndrzej Hajda #define CLK_UART3 292 96b568059bSAndrzej Hajda #define CLK_UART4 293 97b568059bSAndrzej Hajda #define CLK_I2C0 294 98b568059bSAndrzej Hajda #define CLK_I2C1 295 99b568059bSAndrzej Hajda #define CLK_I2C2 296 100b568059bSAndrzej Hajda #define CLK_I2C3 297 101b568059bSAndrzej Hajda #define CLK_I2C4 298 102b568059bSAndrzej Hajda #define CLK_I2C5 299 103b568059bSAndrzej Hajda #define CLK_I2C6 300 104b568059bSAndrzej Hajda #define CLK_I2C7 301 105b568059bSAndrzej Hajda #define CLK_I2C_HDMI 302 106b568059bSAndrzej Hajda #define CLK_ADC 303 107b568059bSAndrzej Hajda #define CLK_SPI0 304 108b568059bSAndrzej Hajda #define CLK_SPI1 305 109b568059bSAndrzej Hajda #define CLK_SPI2 306 110b568059bSAndrzej Hajda #define CLK_I2S1 307 111b568059bSAndrzej Hajda #define CLK_I2S2 308 112b568059bSAndrzej Hajda #define CLK_PCM1 309 113b568059bSAndrzej Hajda #define CLK_PCM2 310 114b568059bSAndrzej Hajda #define CLK_PWM 311 115b568059bSAndrzej Hajda #define CLK_SPDIF 312 116b568059bSAndrzej Hajda #define CLK_AC97 313 117b568059bSAndrzej Hajda #define CLK_HSI2C0 314 118b568059bSAndrzej Hajda #define CLK_HSI2C1 315 119b568059bSAndrzej Hajda #define CLK_HSI2C2 316 120b568059bSAndrzej Hajda #define CLK_HSI2C3 317 121b568059bSAndrzej Hajda #define CLK_CHIPID 318 122b568059bSAndrzej Hajda #define CLK_SYSREG 319 123b568059bSAndrzej Hajda #define CLK_PMU 320 124b568059bSAndrzej Hajda #define CLK_CMU_TOP 321 125b568059bSAndrzej Hajda #define CLK_CMU_CORE 322 126b568059bSAndrzej Hajda #define CLK_CMU_MEM 323 127b568059bSAndrzej Hajda #define CLK_TZPC0 324 128b568059bSAndrzej Hajda #define CLK_TZPC1 325 129b568059bSAndrzej Hajda #define CLK_TZPC2 326 130b568059bSAndrzej Hajda #define CLK_TZPC3 327 131b568059bSAndrzej Hajda #define CLK_TZPC4 328 132b568059bSAndrzej Hajda #define CLK_TZPC5 329 133b568059bSAndrzej Hajda #define CLK_TZPC6 330 134b568059bSAndrzej Hajda #define CLK_TZPC7 331 135b568059bSAndrzej Hajda #define CLK_TZPC8 332 136b568059bSAndrzej Hajda #define CLK_TZPC9 333 137b568059bSAndrzej Hajda #define CLK_HDMI_CEC 334 138b568059bSAndrzej Hajda #define CLK_MCT 335 139b568059bSAndrzej Hajda #define CLK_WDT 336 140b568059bSAndrzej Hajda #define CLK_RTC 337 141b568059bSAndrzej Hajda #define CLK_TMU 338 142b568059bSAndrzej Hajda #define CLK_FIMD1 339 143b568059bSAndrzej Hajda #define CLK_MIE1 340 144b568059bSAndrzej Hajda #define CLK_DSIM0 341 145b568059bSAndrzej Hajda #define CLK_DP 342 146b568059bSAndrzej Hajda #define CLK_MIXER 343 147b568059bSAndrzej Hajda #define CLK_HDMI 344 148b568059bSAndrzej Hajda #define CLK_G2D 345 149b568059bSAndrzej Hajda #define CLK_MDMA0 346 150b568059bSAndrzej Hajda #define CLK_SMMU_MDMA0 347 1515b73721bSNaveen Krishna Chatradhi #define CLK_SSS 348 15220b82ae2SArun Kumar K #define CLK_G3D 349 153bfed1074SCho KyongHo #define CLK_SMMU_TV 350 154bfed1074SCho KyongHo #define CLK_SMMU_FIMD1 351 155bfed1074SCho KyongHo #define CLK_SMMU_2D 352 156bfed1074SCho KyongHo #define CLK_SMMU_FIMC_ISP 353 157bfed1074SCho KyongHo #define CLK_SMMU_FIMC_DRC 354 158bfed1074SCho KyongHo #define CLK_SMMU_FIMC_SCC 355 159bfed1074SCho KyongHo #define CLK_SMMU_FIMC_SCP 356 160bfed1074SCho KyongHo #define CLK_SMMU_FIMC_FD 357 161bfed1074SCho KyongHo #define CLK_SMMU_FIMC_MCU 358 162bfed1074SCho KyongHo #define CLK_SMMU_FIMC_ODC 359 163bfed1074SCho KyongHo #define CLK_SMMU_FIMC_DIS0 360 164bfed1074SCho KyongHo #define CLK_SMMU_FIMC_DIS1 361 165bfed1074SCho KyongHo #define CLK_SMMU_FIMC_3DNR 362 166bfed1074SCho KyongHo #define CLK_SMMU_FIMC_LITE0 363 167bfed1074SCho KyongHo #define CLK_SMMU_FIMC_LITE1 364 168bfed1074SCho KyongHo #define CLK_CAMIF_TOP 365 169b568059bSAndrzej Hajda 170b568059bSAndrzej Hajda /* mux clocks */ 171b568059bSAndrzej Hajda #define CLK_MOUT_HDMI 1024 17220b82ae2SArun Kumar K #define CLK_MOUT_GPLL 1025 173b4dc272bSTomeu Vizoso #define CLK_MOUT_ACLK200_DISP1_SUB 1026 174b4dc272bSTomeu Vizoso #define CLK_MOUT_ACLK300_DISP1_SUB 1027 175f493602dSSylwester Nawrocki #define CLK_MOUT_APLL 1028 176f493602dSSylwester Nawrocki #define CLK_MOUT_MPLL 1029 177b568059bSAndrzej Hajda 178b568059bSAndrzej Hajda /* must be greater than maximal clock id */ 179f493602dSSylwester Nawrocki #define CLK_NR_CLKS 1030 180b568059bSAndrzej Hajda 181b568059bSAndrzej Hajda #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ 182