1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Author: Andrzej Haja <a.hajda@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Device Tree binding constants for Exynos4 clock controller. 10 */ 11 12 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H 13 #define _DT_BINDINGS_CLOCK_EXYNOS_4_H 14 15 /* core clocks */ 16 #define CLK_XXTI 1 17 #define CLK_XUSBXTI 2 18 #define CLK_FIN_PLL 3 19 #define CLK_FOUT_APLL 4 20 #define CLK_FOUT_MPLL 5 21 #define CLK_FOUT_EPLL 6 22 #define CLK_FOUT_VPLL 7 23 #define CLK_SCLK_APLL 8 24 #define CLK_SCLK_MPLL 9 25 #define CLK_SCLK_EPLL 10 26 #define CLK_SCLK_VPLL 11 27 #define CLK_ARM_CLK 12 28 #define CLK_ACLK200 13 29 #define CLK_ACLK100 14 30 #define CLK_ACLK160 15 31 #define CLK_ACLK133 16 32 #define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */ 33 #define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */ 34 #define CLK_MOUT_CORE 19 35 #define CLK_MOUT_APLL 20 36 #define CLK_SCLK_HDMIPHY 22 37 38 /* gate for special clocks (sclk) */ 39 #define CLK_SCLK_FIMC0 128 40 #define CLK_SCLK_FIMC1 129 41 #define CLK_SCLK_FIMC2 130 42 #define CLK_SCLK_FIMC3 131 43 #define CLK_SCLK_CAM0 132 44 #define CLK_SCLK_CAM1 133 45 #define CLK_SCLK_CSIS0 134 46 #define CLK_SCLK_CSIS1 135 47 #define CLK_SCLK_HDMI 136 48 #define CLK_SCLK_MIXER 137 49 #define CLK_SCLK_DAC 138 50 #define CLK_SCLK_PIXEL 139 51 #define CLK_SCLK_FIMD0 140 52 #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */ 53 #define CLK_SCLK_MDNIE_PWM0 142 54 #define CLK_SCLK_MIPI0 143 55 #define CLK_SCLK_AUDIO0 144 56 #define CLK_SCLK_MMC0 145 57 #define CLK_SCLK_MMC1 146 58 #define CLK_SCLK_MMC2 147 59 #define CLK_SCLK_MMC3 148 60 #define CLK_SCLK_MMC4 149 61 #define CLK_SCLK_SATA 150 /* Exynos4210 only */ 62 #define CLK_SCLK_UART0 151 63 #define CLK_SCLK_UART1 152 64 #define CLK_SCLK_UART2 153 65 #define CLK_SCLK_UART3 154 66 #define CLK_SCLK_UART4 155 67 #define CLK_SCLK_AUDIO1 156 68 #define CLK_SCLK_AUDIO2 157 69 #define CLK_SCLK_SPDIF 158 70 #define CLK_SCLK_SPI0 159 71 #define CLK_SCLK_SPI1 160 72 #define CLK_SCLK_SPI2 161 73 #define CLK_SCLK_SLIMBUS 162 74 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ 75 #define CLK_SCLK_MIPI1 164 /* Exynos4210 only */ 76 #define CLK_SCLK_PCM1 165 77 #define CLK_SCLK_PCM2 166 78 #define CLK_SCLK_I2S1 167 79 #define CLK_SCLK_I2S2 168 80 #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */ 81 #define CLK_SCLK_MFC 170 82 #define CLK_SCLK_PCM0 171 83 #define CLK_SCLK_G3D 172 84 #define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */ 85 #define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */ 86 #define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */ 87 #define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */ 88 #define CLK_SCLK_FIMG2D 177 89 90 /* gate clocks */ 91 #define CLK_FIMC0 256 92 #define CLK_FIMC1 257 93 #define CLK_FIMC2 258 94 #define CLK_FIMC3 259 95 #define CLK_CSIS0 260 96 #define CLK_CSIS1 261 97 #define CLK_JPEG 262 98 #define CLK_SMMU_FIMC0 263 99 #define CLK_SMMU_FIMC1 264 100 #define CLK_SMMU_FIMC2 265 101 #define CLK_SMMU_FIMC3 266 102 #define CLK_SMMU_JPEG 267 103 #define CLK_VP 268 104 #define CLK_MIXER 269 105 #define CLK_TVENC 270 /* Exynos4210 only */ 106 #define CLK_HDMI 271 107 #define CLK_SMMU_TV 272 108 #define CLK_MFC 273 109 #define CLK_SMMU_MFCL 274 110 #define CLK_SMMU_MFCR 275 111 #define CLK_G3D 276 112 #define CLK_G2D 277 113 #define CLK_ROTATOR 278 /* Exynos4210 only */ 114 #define CLK_MDMA 279 /* Exynos4210 only */ 115 #define CLK_SMMU_G2D 280 /* Exynos4210 only */ 116 #define CLK_SMMU_ROTATOR 281 /* Exynos4210 only */ 117 #define CLK_SMMU_MDMA 282 /* Exynos4210 only */ 118 #define CLK_FIMD0 283 119 #define CLK_MIE0 284 120 #define CLK_MDNIE0 285 /* Exynos4412 only */ 121 #define CLK_DSIM0 286 122 #define CLK_SMMU_FIMD0 287 123 #define CLK_FIMD1 288 /* Exynos4210 only */ 124 #define CLK_MIE1 289 /* Exynos4210 only */ 125 #define CLK_DSIM1 290 /* Exynos4210 only */ 126 #define CLK_SMMU_FIMD1 291 /* Exynos4210 only */ 127 #define CLK_PDMA0 292 128 #define CLK_PDMA1 293 129 #define CLK_PCIE_PHY 294 130 #define CLK_SATA_PHY 295 /* Exynos4210 only */ 131 #define CLK_TSI 296 132 #define CLK_SDMMC0 297 133 #define CLK_SDMMC1 298 134 #define CLK_SDMMC2 299 135 #define CLK_SDMMC3 300 136 #define CLK_SDMMC4 301 137 #define CLK_SATA 302 /* Exynos4210 only */ 138 #define CLK_SROMC 303 139 #define CLK_USB_HOST 304 140 #define CLK_USB_DEVICE 305 141 #define CLK_PCIE 306 142 #define CLK_ONENAND 307 143 #define CLK_NFCON 308 144 #define CLK_SMMU_PCIE 309 145 #define CLK_GPS 310 146 #define CLK_SMMU_GPS 311 147 #define CLK_UART0 312 148 #define CLK_UART1 313 149 #define CLK_UART2 314 150 #define CLK_UART3 315 151 #define CLK_UART4 316 152 #define CLK_I2C0 317 153 #define CLK_I2C1 318 154 #define CLK_I2C2 319 155 #define CLK_I2C3 320 156 #define CLK_I2C4 321 157 #define CLK_I2C5 322 158 #define CLK_I2C6 323 159 #define CLK_I2C7 324 160 #define CLK_I2C_HDMI 325 161 #define CLK_TSADC 326 162 #define CLK_SPI0 327 163 #define CLK_SPI1 328 164 #define CLK_SPI2 329 165 #define CLK_I2S1 330 166 #define CLK_I2S2 331 167 #define CLK_PCM0 332 168 #define CLK_I2S0 333 169 #define CLK_PCM1 334 170 #define CLK_PCM2 335 171 #define CLK_PWM 336 172 #define CLK_SLIMBUS 337 173 #define CLK_SPDIF 338 174 #define CLK_AC97 339 175 #define CLK_MODEMIF 340 176 #define CLK_CHIPID 341 177 #define CLK_SYSREG 342 178 #define CLK_HDMI_CEC 343 179 #define CLK_MCT 344 180 #define CLK_WDT 345 181 #define CLK_RTC 346 182 #define CLK_KEYIF 347 183 #define CLK_AUDSS 348 184 #define CLK_MIPI_HSI 349 /* Exynos4210 only */ 185 #define CLK_PIXELASYNCM0 351 186 #define CLK_PIXELASYNCM1 352 187 #define CLK_FIMC_LITE0 353 /* Exynos4x12 only */ 188 #define CLK_FIMC_LITE1 354 /* Exynos4x12 only */ 189 #define CLK_PPMUISPX 355 /* Exynos4x12 only */ 190 #define CLK_PPMUISPMX 356 /* Exynos4x12 only */ 191 #define CLK_FIMC_ISP 357 /* Exynos4x12 only */ 192 #define CLK_FIMC_DRC 358 /* Exynos4x12 only */ 193 #define CLK_FIMC_FD 359 /* Exynos4x12 only */ 194 #define CLK_MCUISP 360 /* Exynos4x12 only */ 195 #define CLK_GICISP 361 /* Exynos4x12 only */ 196 #define CLK_SMMU_ISP 362 /* Exynos4x12 only */ 197 #define CLK_SMMU_DRC 363 /* Exynos4x12 only */ 198 #define CLK_SMMU_FD 364 /* Exynos4x12 only */ 199 #define CLK_SMMU_LITE0 365 /* Exynos4x12 only */ 200 #define CLK_SMMU_LITE1 366 /* Exynos4x12 only */ 201 #define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */ 202 #define CLK_MPWM_ISP 368 /* Exynos4x12 only */ 203 #define CLK_I2C0_ISP 369 /* Exynos4x12 only */ 204 #define CLK_I2C1_ISP 370 /* Exynos4x12 only */ 205 #define CLK_MTCADC_ISP 371 /* Exynos4x12 only */ 206 #define CLK_PWM_ISP 372 /* Exynos4x12 only */ 207 #define CLK_WDT_ISP 373 /* Exynos4x12 only */ 208 #define CLK_UART_ISP 374 /* Exynos4x12 only */ 209 #define CLK_ASYNCAXIM 375 /* Exynos4x12 only */ 210 #define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */ 211 #define CLK_SPI0_ISP 377 /* Exynos4x12 only */ 212 #define CLK_SPI1_ISP 378 /* Exynos4x12 only */ 213 #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ 214 #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ 215 #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ 216 #define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */ 217 #define CLK_TMU_APBIF 383 218 219 /* mux clocks */ 220 #define CLK_MOUT_FIMC0 384 221 #define CLK_MOUT_FIMC1 385 222 #define CLK_MOUT_FIMC2 386 223 #define CLK_MOUT_FIMC3 387 224 #define CLK_MOUT_CAM0 388 225 #define CLK_MOUT_CAM1 389 226 #define CLK_MOUT_CSIS0 390 227 #define CLK_MOUT_CSIS1 391 228 #define CLK_MOUT_G3D0 392 229 #define CLK_MOUT_G3D1 393 230 #define CLK_MOUT_G3D 394 231 #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */ 232 233 /* div clocks */ 234 #define CLK_DIV_ISP0 450 /* Exynos4x12 only */ 235 #define CLK_DIV_ISP1 451 /* Exynos4x12 only */ 236 #define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */ 237 #define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */ 238 #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ 239 #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ 240 241 /* must be greater than maximal clock id */ 242 #define CLK_NR_CLKS 456 243 244 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ 245