1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Tomasz Figa <t.figa@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Device Tree binding constants for Samsung Exynos3250 clock controllers. 10 */ 11 12 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H 13 #define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H 14 15 /* 16 * Let each exported clock get a unique index, which is used on DT-enabled 17 * platforms to lookup the clock from a clock specifier. These indices are 18 * therefore considered an ABI and so must not be changed. This implies 19 * that new clocks should be added either in free spaces between clock groups 20 * or at the end. 21 */ 22 23 24 /* 25 * Main CMU 26 */ 27 28 #define CLK_OSCSEL 1 29 #define CLK_FIN_PLL 2 30 #define CLK_FOUT_APLL 3 31 #define CLK_FOUT_VPLL 4 32 #define CLK_FOUT_UPLL 5 33 #define CLK_FOUT_MPLL 6 34 35 /* Muxes */ 36 #define CLK_MOUT_MPLL_USER_L 16 37 #define CLK_MOUT_GDL 17 38 #define CLK_MOUT_MPLL_USER_R 18 39 #define CLK_MOUT_GDR 19 40 #define CLK_MOUT_EBI 20 41 #define CLK_MOUT_ACLK_200 21 42 #define CLK_MOUT_ACLK_160 22 43 #define CLK_MOUT_ACLK_100 23 44 #define CLK_MOUT_ACLK_266_1 24 45 #define CLK_MOUT_ACLK_266_0 25 46 #define CLK_MOUT_ACLK_266 26 47 #define CLK_MOUT_VPLL 27 48 #define CLK_MOUT_EPLL_USER 28 49 #define CLK_MOUT_EBI_1 29 50 #define CLK_MOUT_UPLL 30 51 #define CLK_MOUT_ACLK_400_MCUISP_SUB 31 52 #define CLK_MOUT_MPLL 32 53 #define CLK_MOUT_ACLK_400_MCUISP 33 54 #define CLK_MOUT_VPLLSRC 34 55 #define CLK_MOUT_CAM1 35 56 #define CLK_MOUT_CAM_BLK 36 57 #define CLK_MOUT_MFC 37 58 #define CLK_MOUT_MFC_1 38 59 #define CLK_MOUT_MFC_0 39 60 #define CLK_MOUT_G3D 40 61 #define CLK_MOUT_G3D_1 41 62 #define CLK_MOUT_G3D_0 42 63 #define CLK_MOUT_MIPI0 43 64 #define CLK_MOUT_FIMD0 44 65 #define CLK_MOUT_UART_ISP 45 66 #define CLK_MOUT_SPI1_ISP 46 67 #define CLK_MOUT_SPI0_ISP 47 68 #define CLK_MOUT_TSADC 48 69 #define CLK_MOUT_MMC1 49 70 #define CLK_MOUT_MMC0 50 71 #define CLK_MOUT_UART1 51 72 #define CLK_MOUT_UART0 52 73 #define CLK_MOUT_SPI1 53 74 #define CLK_MOUT_SPI0 54 75 #define CLK_MOUT_AUDIO 55 76 #define CLK_MOUT_MPLL_USER_C 56 77 #define CLK_MOUT_HPM 57 78 #define CLK_MOUT_CORE 58 79 #define CLK_MOUT_APLL 59 80 #define CLK_MOUT_ACLK_266_SUB 60 81 82 /* Dividers */ 83 #define CLK_DIV_GPL 64 84 #define CLK_DIV_GDL 65 85 #define CLK_DIV_GPR 66 86 #define CLK_DIV_GDR 67 87 #define CLK_DIV_MPLL_PRE 68 88 #define CLK_DIV_ACLK_400_MCUISP 69 89 #define CLK_DIV_EBI 70 90 #define CLK_DIV_ACLK_200 71 91 #define CLK_DIV_ACLK_160 72 92 #define CLK_DIV_ACLK_100 73 93 #define CLK_DIV_ACLK_266 74 94 #define CLK_DIV_CAM1 75 95 #define CLK_DIV_CAM_BLK 76 96 #define CLK_DIV_MFC 77 97 #define CLK_DIV_G3D 78 98 #define CLK_DIV_MIPI0_PRE 79 99 #define CLK_DIV_MIPI0 80 100 #define CLK_DIV_FIMD0 81 101 #define CLK_DIV_UART_ISP 82 102 #define CLK_DIV_SPI1_ISP_PRE 83 103 #define CLK_DIV_SPI1_ISP 84 104 #define CLK_DIV_SPI0_ISP_PRE 85 105 #define CLK_DIV_SPI0_ISP 86 106 #define CLK_DIV_TSADC_PRE 87 107 #define CLK_DIV_TSADC 88 108 #define CLK_DIV_MMC1_PRE 89 109 #define CLK_DIV_MMC1 90 110 #define CLK_DIV_MMC0_PRE 91 111 #define CLK_DIV_MMC0 92 112 #define CLK_DIV_UART1 93 113 #define CLK_DIV_UART0 94 114 #define CLK_DIV_SPI1_PRE 95 115 #define CLK_DIV_SPI1 96 116 #define CLK_DIV_SPI0_PRE 97 117 #define CLK_DIV_SPI0 98 118 #define CLK_DIV_PCM 99 119 #define CLK_DIV_AUDIO 100 120 #define CLK_DIV_I2S 101 121 #define CLK_DIV_CORE2 102 122 #define CLK_DIV_APLL 103 123 #define CLK_DIV_PCLK_DBG 104 124 #define CLK_DIV_ATB 105 125 #define CLK_DIV_COREM 106 126 #define CLK_DIV_CORE 107 127 #define CLK_DIV_HPM 108 128 #define CLK_DIV_COPY 109 129 130 /* Gates */ 131 #define CLK_ASYNC_G3D 128 132 #define CLK_ASYNC_MFCL 129 133 #define CLK_PPMULEFT 130 134 #define CLK_GPIO_LEFT 131 135 #define CLK_ASYNC_ISPMX 132 136 #define CLK_ASYNC_FSYSD 133 137 #define CLK_ASYNC_LCD0X 134 138 #define CLK_ASYNC_CAMX 135 139 #define CLK_PPMURIGHT 136 140 #define CLK_GPIO_RIGHT 137 141 #define CLK_MONOCNT 138 142 #define CLK_TZPC6 139 143 #define CLK_PROVISIONKEY1 140 144 #define CLK_PROVISIONKEY0 141 145 #define CLK_CMU_ISPPART 142 146 #define CLK_TMU_APBIF 143 147 #define CLK_KEYIF 144 148 #define CLK_RTC 145 149 #define CLK_WDT 146 150 #define CLK_MCT 147 151 #define CLK_SECKEY 148 152 #define CLK_TZPC5 149 153 #define CLK_TZPC4 150 154 #define CLK_TZPC3 151 155 #define CLK_TZPC2 152 156 #define CLK_TZPC1 153 157 #define CLK_TZPC0 154 158 #define CLK_CMU_COREPART 155 159 #define CLK_CMU_TOPPART 156 160 #define CLK_PMU_APBIF 157 161 #define CLK_SYSREG 158 162 #define CLK_CHIP_ID 159 163 #define CLK_QEJPEG 160 164 #define CLK_PIXELASYNCM1 161 165 #define CLK_PIXELASYNCM0 162 166 #define CLK_PPMUCAMIF 163 167 #define CLK_QEM2MSCALER 164 168 #define CLK_QEGSCALER1 165 169 #define CLK_QEGSCALER0 166 170 #define CLK_SMMUJPEG 167 171 #define CLK_SMMUM2M2SCALER 168 172 #define CLK_SMMUGSCALER1 169 173 #define CLK_SMMUGSCALER0 170 174 #define CLK_JPEG 171 175 #define CLK_M2MSCALER 172 176 #define CLK_GSCALER1 173 177 #define CLK_GSCALER0 174 178 #define CLK_QEMFC 175 179 #define CLK_PPMUMFC_L 176 180 #define CLK_SMMUMFC_L 177 181 #define CLK_MFC 178 182 #define CLK_SMMUG3D 179 183 #define CLK_QEG3D 180 184 #define CLK_PPMUG3D 181 185 #define CLK_G3D 182 186 #define CLK_QE_CH1_LCD 183 187 #define CLK_QE_CH0_LCD 184 188 #define CLK_PPMULCD0 185 189 #define CLK_SMMUFIMD0 186 190 #define CLK_DSIM0 187 191 #define CLK_FIMD0 188 192 #define CLK_CAM1 189 193 #define CLK_UART_ISP_TOP 190 194 #define CLK_SPI1_ISP_TOP 191 195 #define CLK_SPI0_ISP_TOP 192 196 #define CLK_TSADC 193 197 #define CLK_PPMUFILE 194 198 #define CLK_USBOTG 195 199 #define CLK_USBHOST 196 200 #define CLK_SROMC 197 201 #define CLK_SDMMC1 198 202 #define CLK_SDMMC0 199 203 #define CLK_PDMA1 200 204 #define CLK_PDMA0 201 205 #define CLK_PWM 202 206 #define CLK_PCM 203 207 #define CLK_I2S 204 208 #define CLK_SPI1 205 209 #define CLK_SPI0 206 210 #define CLK_I2C7 207 211 #define CLK_I2C6 208 212 #define CLK_I2C5 209 213 #define CLK_I2C4 210 214 #define CLK_I2C3 211 215 #define CLK_I2C2 212 216 #define CLK_I2C1 213 217 #define CLK_I2C0 214 218 #define CLK_UART1 215 219 #define CLK_UART0 216 220 #define CLK_BLOCK_LCD 217 221 #define CLK_BLOCK_G3D 218 222 #define CLK_BLOCK_MFC 219 223 #define CLK_BLOCK_CAM 220 224 #define CLK_SMIES 221 225 226 /* Special clocks */ 227 #define CLK_SCLK_JPEG 224 228 #define CLK_SCLK_M2MSCALER 225 229 #define CLK_SCLK_GSCALER1 226 230 #define CLK_SCLK_GSCALER0 227 231 #define CLK_SCLK_MFC 228 232 #define CLK_SCLK_G3D 229 233 #define CLK_SCLK_MIPIDPHY2L 230 234 #define CLK_SCLK_MIPI0 231 235 #define CLK_SCLK_FIMD0 232 236 #define CLK_SCLK_CAM1 233 237 #define CLK_SCLK_UART_ISP 234 238 #define CLK_SCLK_SPI1_ISP 235 239 #define CLK_SCLK_SPI0_ISP 236 240 #define CLK_SCLK_UPLL 237 241 #define CLK_SCLK_TSADC 238 242 #define CLK_SCLK_EBI 239 243 #define CLK_SCLK_MMC1 240 244 #define CLK_SCLK_MMC0 241 245 #define CLK_SCLK_I2S 242 246 #define CLK_SCLK_PCM 243 247 #define CLK_SCLK_SPI1 244 248 #define CLK_SCLK_SPI0 245 249 #define CLK_SCLK_UART1 246 250 #define CLK_SCLK_UART0 247 251 252 /* 253 * Total number of clocks of main CMU. 254 * NOTE: Must be equal to last clock ID increased by one. 255 */ 256 #define CLK_NR_CLKS 248 257 258 /* 259 * CMU DMC 260 */ 261 262 #define CLK_FOUT_BPLL 1 263 #define CLK_FOUT_EPLL 2 264 265 /* Muxes */ 266 #define CLK_MOUT_MPLL_MIF 8 267 #define CLK_MOUT_BPLL 9 268 #define CLK_MOUT_DPHY 10 269 #define CLK_MOUT_DMC_BUS 11 270 #define CLK_MOUT_EPLL 12 271 272 /* Dividers */ 273 #define CLK_DIV_DMC 16 274 #define CLK_DIV_DPHY 17 275 #define CLK_DIV_DMC_PRE 18 276 #define CLK_DIV_DMCP 19 277 #define CLK_DIV_DMCD 20 278 279 /* 280 * Total number of clocks of main CMU. 281 * NOTE: Must be equal to last clock ID increased by one. 282 */ 283 #define NR_CLKS_DMC 21 284 285 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */ 286