1 /* 2 * Copyright 2017 Texas Instruments, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 #ifndef __DT_BINDINGS_CLK_DRA7_H 14 #define __DT_BINDINGS_CLK_DRA7_H 15 16 #define DRA7_CLKCTRL_OFFSET 0x20 17 #define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET) 18 19 /* mpu clocks */ 20 #define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 21 22 /* ipu clocks */ 23 #define DRA7_IPU_CLKCTRL_OFFSET 0x40 24 #define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET) 25 #define DRA7_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50) 26 #define DRA7_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58) 27 #define DRA7_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60) 28 #define DRA7_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68) 29 #define DRA7_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70) 30 #define DRA7_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78) 31 #define DRA7_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80) 32 33 /* rtc clocks */ 34 #define DRA7_RTC_CLKCTRL_OFFSET 0x40 35 #define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET) 36 #define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44) 37 38 /* coreaon clocks */ 39 #define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 40 #define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) 41 42 /* l3main1 clocks */ 43 #define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 44 #define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 45 #define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) 46 #define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) 47 #define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) 48 #define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) 49 #define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) 50 51 /* dma clocks */ 52 #define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 53 54 /* emif clocks */ 55 #define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 56 57 /* atl clocks */ 58 #define DRA7_ATL_CLKCTRL_OFFSET 0x0 59 #define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) 60 #define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) 61 62 /* l4cfg clocks */ 63 #define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 64 #define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 65 #define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) 66 #define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) 67 #define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) 68 #define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) 69 #define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) 70 #define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) 71 #define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) 72 #define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) 73 #define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) 74 #define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) 75 #define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) 76 #define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) 77 #define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) 78 79 /* l3instr clocks */ 80 #define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 81 #define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 82 83 /* dss clocks */ 84 #define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 85 #define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) 86 87 /* l3init clocks */ 88 #define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 89 #define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) 90 #define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) 91 #define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) 92 #define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) 93 #define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) 94 #define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0) 95 #define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8) 96 #define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0) 97 #define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) 98 #define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) 99 #define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) 100 101 /* l4per clocks */ 102 #define DRA7_L4PER_CLKCTRL_OFFSET 0x0 103 #define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET) 104 #define DRA7_L4_PER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc) 105 #define DRA7_L4_PER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x14) 106 #define DRA7_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28) 107 #define DRA7_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30) 108 #define DRA7_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38) 109 #define DRA7_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40) 110 #define DRA7_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48) 111 #define DRA7_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50) 112 #define DRA7_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58) 113 #define DRA7_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60) 114 #define DRA7_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68) 115 #define DRA7_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70) 116 #define DRA7_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78) 117 #define DRA7_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80) 118 #define DRA7_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88) 119 #define DRA7_EPWMSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x90) 120 #define DRA7_EPWMSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x98) 121 #define DRA7_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0) 122 #define DRA7_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8) 123 #define DRA7_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0) 124 #define DRA7_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8) 125 #define DRA7_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0) 126 #define DRA7_EPWMSS0_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc4) 127 #define DRA7_TIMER13_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc8) 128 #define DRA7_TIMER14_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd0) 129 #define DRA7_TIMER15_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd8) 130 #define DRA7_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0) 131 #define DRA7_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8) 132 #define DRA7_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100) 133 #define DRA7_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108) 134 #define DRA7_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110) 135 #define DRA7_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118) 136 #define DRA7_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120) 137 #define DRA7_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128) 138 #define DRA7_TIMER16_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x130) 139 #define DRA7_QSPI_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x138) 140 #define DRA7_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140) 141 #define DRA7_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148) 142 #define DRA7_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150) 143 #define DRA7_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158) 144 #define DRA7_MCASP2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x160) 145 #define DRA7_MCASP3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x168) 146 #define DRA7_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170) 147 #define DRA7_MCASP5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x178) 148 #define DRA7_MCASP8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x190) 149 #define DRA7_MCASP4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x198) 150 #define DRA7_AES1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a0) 151 #define DRA7_AES2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a8) 152 #define DRA7_DES_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1b0) 153 #define DRA7_RNG_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c0) 154 #define DRA7_SHAM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c8) 155 #define DRA7_UART7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1d0) 156 #define DRA7_UART8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e0) 157 #define DRA7_UART9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e8) 158 #define DRA7_DCAN2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1f0) 159 #define DRA7_MCASP6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x204) 160 #define DRA7_MCASP7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x208) 161 162 /* wkupaon clocks */ 163 #define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 164 #define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) 165 #define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) 166 #define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) 167 #define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) 168 #define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) 169 #define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) 170 #define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) 171 #define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) 172 173 #endif 174