1aec6adc5SSerge Semin /* SPDX-License-Identifier: GPL-2.0-only */ 2aec6adc5SSerge Semin /* 3aec6adc5SSerge Semin * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC 4aec6adc5SSerge Semin * 5aec6adc5SSerge Semin * Baikal-T1 CCU clock indices 6aec6adc5SSerge Semin */ 7aec6adc5SSerge Semin #ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H 8aec6adc5SSerge Semin #define __DT_BINDINGS_CLOCK_BT1_CCU_H 9aec6adc5SSerge Semin 10aec6adc5SSerge Semin #define CCU_CPU_PLL 0 11aec6adc5SSerge Semin #define CCU_SATA_PLL 1 12aec6adc5SSerge Semin #define CCU_DDR_PLL 2 13aec6adc5SSerge Semin #define CCU_PCIE_PLL 3 14aec6adc5SSerge Semin #define CCU_ETH_PLL 4 15aec6adc5SSerge Semin 1611ea09b9SSerge Semin #define CCU_AXI_MAIN_CLK 0 1711ea09b9SSerge Semin #define CCU_AXI_DDR_CLK 1 1811ea09b9SSerge Semin #define CCU_AXI_SATA_CLK 2 1911ea09b9SSerge Semin #define CCU_AXI_GMAC0_CLK 3 2011ea09b9SSerge Semin #define CCU_AXI_GMAC1_CLK 4 2111ea09b9SSerge Semin #define CCU_AXI_XGMAC_CLK 5 2211ea09b9SSerge Semin #define CCU_AXI_PCIE_M_CLK 6 2311ea09b9SSerge Semin #define CCU_AXI_PCIE_S_CLK 7 2411ea09b9SSerge Semin #define CCU_AXI_USB_CLK 8 2511ea09b9SSerge Semin #define CCU_AXI_HWA_CLK 9 2611ea09b9SSerge Semin #define CCU_AXI_SRAM_CLK 10 2711ea09b9SSerge Semin 2811ea09b9SSerge Semin #define CCU_SYS_SATA_REF_CLK 0 2911ea09b9SSerge Semin #define CCU_SYS_APB_CLK 1 3011ea09b9SSerge Semin #define CCU_SYS_GMAC0_TX_CLK 2 3111ea09b9SSerge Semin #define CCU_SYS_GMAC0_PTP_CLK 3 3211ea09b9SSerge Semin #define CCU_SYS_GMAC1_TX_CLK 4 3311ea09b9SSerge Semin #define CCU_SYS_GMAC1_PTP_CLK 5 3411ea09b9SSerge Semin #define CCU_SYS_XGMAC_REF_CLK 6 3511ea09b9SSerge Semin #define CCU_SYS_XGMAC_PTP_CLK 7 3611ea09b9SSerge Semin #define CCU_SYS_USB_CLK 8 3711ea09b9SSerge Semin #define CCU_SYS_PVT_CLK 9 3811ea09b9SSerge Semin #define CCU_SYS_HWA_CLK 10 3911ea09b9SSerge Semin #define CCU_SYS_UART_CLK 11 4011ea09b9SSerge Semin #define CCU_SYS_I2C1_CLK 12 4111ea09b9SSerge Semin #define CCU_SYS_I2C2_CLK 13 4211ea09b9SSerge Semin #define CCU_SYS_GPIO_CLK 14 4311ea09b9SSerge Semin #define CCU_SYS_TIMER0_CLK 15 4411ea09b9SSerge Semin #define CCU_SYS_TIMER1_CLK 16 4511ea09b9SSerge Semin #define CCU_SYS_TIMER2_CLK 17 4611ea09b9SSerge Semin #define CCU_SYS_WDT_CLK 18 4711ea09b9SSerge Semin 48aec6adc5SSerge Semin #endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */ 49