17046c6b0SManivannan Sadhasivam /* SPDX-License-Identifier: GPL-2.0+ */ 27046c6b0SManivannan Sadhasivam /* 37046c6b0SManivannan Sadhasivam * Device Tree binding constants for Bitmain BM1880 SoC 47046c6b0SManivannan Sadhasivam * 57046c6b0SManivannan Sadhasivam * Copyright (c) 2019 Linaro Ltd. 67046c6b0SManivannan Sadhasivam */ 77046c6b0SManivannan Sadhasivam 87046c6b0SManivannan Sadhasivam #ifndef __DT_BINDINGS_CLOCK_BM1880_H 97046c6b0SManivannan Sadhasivam #define __DT_BINDINGS_CLOCK_BM1880_H 107046c6b0SManivannan Sadhasivam 117046c6b0SManivannan Sadhasivam #define BM1880_CLK_OSC 0 127046c6b0SManivannan Sadhasivam #define BM1880_CLK_MPLL 1 137046c6b0SManivannan Sadhasivam #define BM1880_CLK_SPLL 2 147046c6b0SManivannan Sadhasivam #define BM1880_CLK_FPLL 3 157046c6b0SManivannan Sadhasivam #define BM1880_CLK_DDRPLL 4 167046c6b0SManivannan Sadhasivam #define BM1880_CLK_A53 5 177046c6b0SManivannan Sadhasivam #define BM1880_CLK_50M_A53 6 187046c6b0SManivannan Sadhasivam #define BM1880_CLK_AHB_ROM 7 197046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI_SRAM 8 207046c6b0SManivannan Sadhasivam #define BM1880_CLK_DDR_AXI 9 217046c6b0SManivannan Sadhasivam #define BM1880_CLK_EFUSE 10 227046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_EFUSE 11 237046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI5_EMMC 12 247046c6b0SManivannan Sadhasivam #define BM1880_CLK_EMMC 13 257046c6b0SManivannan Sadhasivam #define BM1880_CLK_100K_EMMC 14 267046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI5_SD 15 277046c6b0SManivannan Sadhasivam #define BM1880_CLK_SD 16 287046c6b0SManivannan Sadhasivam #define BM1880_CLK_100K_SD 17 297046c6b0SManivannan Sadhasivam #define BM1880_CLK_500M_ETH0 18 307046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI4_ETH0 19 317046c6b0SManivannan Sadhasivam #define BM1880_CLK_500M_ETH1 20 327046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI4_ETH1 21 337046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI1_GDMA 22 347046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_GPIO 23 357046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_GPIO_INTR 24 367046c6b0SManivannan Sadhasivam #define BM1880_CLK_GPIO_DB 25 377046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI1_MINER 26 387046c6b0SManivannan Sadhasivam #define BM1880_CLK_AHB_SF 27 397046c6b0SManivannan Sadhasivam #define BM1880_CLK_SDMA_AXI 28 407046c6b0SManivannan Sadhasivam #define BM1880_CLK_SDMA_AUD 29 417046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_I2C 30 427046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_WDT 31 437046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_JPEG 32 447046c6b0SManivannan Sadhasivam #define BM1880_CLK_JPEG_AXI 33 457046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI5_NF 34 467046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_NF 35 477046c6b0SManivannan Sadhasivam #define BM1880_CLK_NF 36 487046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_PWM 37 497046c6b0SManivannan Sadhasivam #define BM1880_CLK_DIV_0_RV 38 507046c6b0SManivannan Sadhasivam #define BM1880_CLK_DIV_1_RV 39 517046c6b0SManivannan Sadhasivam #define BM1880_CLK_MUX_RV 40 527046c6b0SManivannan Sadhasivam #define BM1880_CLK_RV 41 537046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_SPI 42 547046c6b0SManivannan Sadhasivam #define BM1880_CLK_TPU_AXI 43 557046c6b0SManivannan Sadhasivam #define BM1880_CLK_DIV_UART_500M 44 567046c6b0SManivannan Sadhasivam #define BM1880_CLK_UART_500M 45 577046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_UART 46 587046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_I2S 47 597046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI4_USB 48 607046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_USB 49 617046c6b0SManivannan Sadhasivam #define BM1880_CLK_125M_USB 50 627046c6b0SManivannan Sadhasivam #define BM1880_CLK_33K_USB 51 637046c6b0SManivannan Sadhasivam #define BM1880_CLK_DIV_12M_USB 52 647046c6b0SManivannan Sadhasivam #define BM1880_CLK_12M_USB 53 657046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_VIDEO 54 667046c6b0SManivannan Sadhasivam #define BM1880_CLK_VIDEO_AXI 55 677046c6b0SManivannan Sadhasivam #define BM1880_CLK_VPP_AXI 56 687046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_VPP 57 697046c6b0SManivannan Sadhasivam #define BM1880_CLK_DIV_0_AXI1 58 707046c6b0SManivannan Sadhasivam #define BM1880_CLK_DIV_1_AXI1 59 717046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI1 60 727046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI2 61 737046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI3 62 747046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI4 63 757046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI5 64 767046c6b0SManivannan Sadhasivam #define BM1880_CLK_DIV_0_AXI6 65 777046c6b0SManivannan Sadhasivam #define BM1880_CLK_DIV_1_AXI6 66 787046c6b0SManivannan Sadhasivam #define BM1880_CLK_MUX_AXI6 67 797046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI6 68 807046c6b0SManivannan Sadhasivam #define BM1880_NR_CLKS 69 817046c6b0SManivannan Sadhasivam 827046c6b0SManivannan Sadhasivam #endif /* __DT_BINDINGS_CLOCK_BM1880_H */ 83