17e5c90e0SQiufang Dai /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
27e5c90e0SQiufang Dai /*
37e5c90e0SQiufang Dai  * Meson-AXG clock tree IDs
47e5c90e0SQiufang Dai  *
57e5c90e0SQiufang Dai  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
67e5c90e0SQiufang Dai  */
77e5c90e0SQiufang Dai 
87e5c90e0SQiufang Dai #ifndef __AXG_CLKC_H
97e5c90e0SQiufang Dai #define __AXG_CLKC_H
107e5c90e0SQiufang Dai 
117e5c90e0SQiufang Dai #define CLKID_SYS_PLL				0
127e5c90e0SQiufang Dai #define CLKID_FIXED_PLL				1
137e5c90e0SQiufang Dai #define CLKID_FCLK_DIV2				2
147e5c90e0SQiufang Dai #define CLKID_FCLK_DIV3				3
157e5c90e0SQiufang Dai #define CLKID_FCLK_DIV4				4
167e5c90e0SQiufang Dai #define CLKID_FCLK_DIV5				5
177e5c90e0SQiufang Dai #define CLKID_FCLK_DIV7				6
187e5c90e0SQiufang Dai #define CLKID_GP0_PLL				7
197e5c90e0SQiufang Dai #define CLKID_CLK81				10
207e5c90e0SQiufang Dai #define CLKID_MPLL0				11
217e5c90e0SQiufang Dai #define CLKID_MPLL1				12
227e5c90e0SQiufang Dai #define CLKID_MPLL2				13
237e5c90e0SQiufang Dai #define CLKID_MPLL3				14
247e5c90e0SQiufang Dai #define CLKID_DDR				15
257e5c90e0SQiufang Dai #define CLKID_AUDIO_LOCKER			16
267e5c90e0SQiufang Dai #define CLKID_MIPI_DSI_HOST			17
277e5c90e0SQiufang Dai #define CLKID_ISA				18
287e5c90e0SQiufang Dai #define CLKID_PL301				19
297e5c90e0SQiufang Dai #define CLKID_PERIPHS				20
307e5c90e0SQiufang Dai #define CLKID_SPICC0				21
317e5c90e0SQiufang Dai #define CLKID_I2C				22
327e5c90e0SQiufang Dai #define CLKID_RNG0				23
337e5c90e0SQiufang Dai #define CLKID_UART0				24
347e5c90e0SQiufang Dai #define CLKID_MIPI_DSI_PHY			25
357e5c90e0SQiufang Dai #define CLKID_SPICC1				26
367e5c90e0SQiufang Dai #define CLKID_PCIE_A				27
377e5c90e0SQiufang Dai #define CLKID_PCIE_B				28
387e5c90e0SQiufang Dai #define CLKID_HIU_IFACE				29
397e5c90e0SQiufang Dai #define CLKID_ASSIST_MISC			30
407e5c90e0SQiufang Dai #define CLKID_SD_EMMC_B				31
417e5c90e0SQiufang Dai #define CLKID_SD_EMMC_C				32
427e5c90e0SQiufang Dai #define CLKID_DMA				33
437e5c90e0SQiufang Dai #define CLKID_SPI				34
447e5c90e0SQiufang Dai #define CLKID_AUDIO				35
457e5c90e0SQiufang Dai #define CLKID_ETH				36
467e5c90e0SQiufang Dai #define CLKID_UART1				37
477e5c90e0SQiufang Dai #define CLKID_G2D				38
487e5c90e0SQiufang Dai #define CLKID_USB0				39
497e5c90e0SQiufang Dai #define CLKID_USB1				40
507e5c90e0SQiufang Dai #define CLKID_RESET				41
517e5c90e0SQiufang Dai #define CLKID_USB				42
527e5c90e0SQiufang Dai #define CLKID_AHB_ARB0				43
537e5c90e0SQiufang Dai #define CLKID_EFUSE				44
547e5c90e0SQiufang Dai #define CLKID_BOOT_ROM				45
557e5c90e0SQiufang Dai #define CLKID_AHB_DATA_BUS			46
567e5c90e0SQiufang Dai #define CLKID_AHB_CTRL_BUS			47
577e5c90e0SQiufang Dai #define CLKID_USB1_DDR_BRIDGE			48
587e5c90e0SQiufang Dai #define CLKID_USB0_DDR_BRIDGE			49
597e5c90e0SQiufang Dai #define CLKID_MMC_PCLK				50
607e5c90e0SQiufang Dai #define CLKID_VPU_INTR				51
617e5c90e0SQiufang Dai #define CLKID_SEC_AHB_AHB3_BRIDGE		52
627e5c90e0SQiufang Dai #define CLKID_GIC				53
637e5c90e0SQiufang Dai #define CLKID_AO_MEDIA_CPU			54
647e5c90e0SQiufang Dai #define CLKID_AO_AHB_SRAM			55
657e5c90e0SQiufang Dai #define CLKID_AO_AHB_BUS			56
667e5c90e0SQiufang Dai #define CLKID_AO_IFACE				57
677e5c90e0SQiufang Dai #define CLKID_AO_I2C				58
687e5c90e0SQiufang Dai #define CLKID_SD_EMMC_B_CLK0			59
697e5c90e0SQiufang Dai #define CLKID_SD_EMMC_C_CLK0			60
70a4fb7df2SJerome Brunet #define CLKID_HIFI_PLL				69
716c0ad1dfSYixun Lan #define CLKID_PCIE_CML_EN0			79
726c0ad1dfSYixun Lan #define CLKID_PCIE_CML_EN1			80
736c0ad1dfSYixun Lan #define CLKID_MIPI_ENABLE			81
74de3c1e71SJerome Brunet #define CLKID_GEN_CLK				84
757e5c90e0SQiufang Dai 
767e5c90e0SQiufang Dai #endif /* __AXG_CLKC_H */
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