1a636cd6cSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 235d35aaeSTushar Behera /* 335d35aaeSTushar Behera * This header provides constants for AT91 pmc status. 435d35aaeSTushar Behera * 535d35aaeSTushar Behera * The constants defined in this header are being used in dts. 635d35aaeSTushar Behera */ 735d35aaeSTushar Behera 835d35aaeSTushar Behera #ifndef _DT_BINDINGS_CLK_AT91_H 935d35aaeSTushar Behera #define _DT_BINDINGS_CLK_AT91_H 1035d35aaeSTushar Behera 11d387ff54SAlexandre Belloni #define PMC_TYPE_CORE 0 12d387ff54SAlexandre Belloni #define PMC_TYPE_SYSTEM 1 13d387ff54SAlexandre Belloni #define PMC_TYPE_PERIPHERAL 2 14d387ff54SAlexandre Belloni #define PMC_TYPE_GCK 3 1599767cd4SMichał Mirosław #define PMC_TYPE_PROGRAMMABLE 4 16d387ff54SAlexandre Belloni 17d387ff54SAlexandre Belloni #define PMC_SLOW 0 18d387ff54SAlexandre Belloni #define PMC_MCK 1 19d387ff54SAlexandre Belloni #define PMC_UTMI 2 20d387ff54SAlexandre Belloni #define PMC_MAIN 3 21d387ff54SAlexandre Belloni #define PMC_MCK2 4 22d387ff54SAlexandre Belloni #define PMC_I2S0_MUX 5 23d387ff54SAlexandre Belloni #define PMC_I2S1_MUX 6 2403a1ee1dSMichał Mirosław #define PMC_PLLACK 7 2503a1ee1dSMichał Mirosław #define PMC_PLLBCK 8 2603a1ee1dSMichał Mirosław #define PMC_AUDIOPLLCK 9 27d387ff54SAlexandre Belloni 28*3d86ee17SEugen Hristev /* SAMA7G5 */ 29*3d86ee17SEugen Hristev #define PMC_CPUPLL (PMC_MAIN + 1) 30*3d86ee17SEugen Hristev #define PMC_SYSPLL (PMC_MAIN + 2) 31*3d86ee17SEugen Hristev #define PMC_DDRPLL (PMC_MAIN + 3) 32*3d86ee17SEugen Hristev #define PMC_IMGPLL (PMC_MAIN + 4) 33*3d86ee17SEugen Hristev #define PMC_BAUDPLL (PMC_MAIN + 5) 34*3d86ee17SEugen Hristev #define PMC_AUDIOPMCPLL (PMC_MAIN + 6) 35*3d86ee17SEugen Hristev #define PMC_AUDIOIOPLL (PMC_MAIN + 7) 36*3d86ee17SEugen Hristev #define PMC_ETHPLL (PMC_MAIN + 8) 37*3d86ee17SEugen Hristev 38d387ff54SAlexandre Belloni #ifndef AT91_PMC_MOSCS 3935d35aaeSTushar Behera #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ 4035d35aaeSTushar Behera #define AT91_PMC_LOCKA 1 /* PLLA Lock */ 4135d35aaeSTushar Behera #define AT91_PMC_LOCKB 2 /* PLLB Lock */ 4235d35aaeSTushar Behera #define AT91_PMC_MCKRDY 3 /* Master Clock */ 4335d35aaeSTushar Behera #define AT91_PMC_LOCKU 6 /* UPLL Lock */ 4435d35aaeSTushar Behera #define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */ 4535d35aaeSTushar Behera #define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */ 4635d35aaeSTushar Behera #define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */ 4735d35aaeSTushar Behera #define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */ 48a5752e57SNicolas Ferre #define AT91_PMC_GCKRDY 24 /* Generated Clocks */ 49d387ff54SAlexandre Belloni #endif 5035d35aaeSTushar Behera 5135d35aaeSTushar Behera #endif 52