1*98872da6SDmitry Rokosov /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2*98872da6SDmitry Rokosov /*
3*98872da6SDmitry Rokosov  * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
4*98872da6SDmitry Rokosov  * Author: Jian Hu <jian.hu@amlogic.com>
5*98872da6SDmitry Rokosov  *
6*98872da6SDmitry Rokosov  * Copyright (c) 2023, SberDevices. All Rights Reserved.
7*98872da6SDmitry Rokosov  * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
8*98872da6SDmitry Rokosov  */
9*98872da6SDmitry Rokosov 
10*98872da6SDmitry Rokosov #ifndef __A1_PERIPHERALS_CLKC_H
11*98872da6SDmitry Rokosov #define __A1_PERIPHERALS_CLKC_H
12*98872da6SDmitry Rokosov 
13*98872da6SDmitry Rokosov #define CLKID_FIXPLL_IN		1
14*98872da6SDmitry Rokosov #define CLKID_USB_PHY_IN	2
15*98872da6SDmitry Rokosov #define CLKID_USB_CTRL_IN	3
16*98872da6SDmitry Rokosov #define CLKID_HIFIPLL_IN	4
17*98872da6SDmitry Rokosov #define CLKID_SYSPLL_IN		5
18*98872da6SDmitry Rokosov #define CLKID_DDS_IN		6
19*98872da6SDmitry Rokosov #define CLKID_SYS		7
20*98872da6SDmitry Rokosov #define CLKID_CLKTREE		8
21*98872da6SDmitry Rokosov #define CLKID_RESET_CTRL	9
22*98872da6SDmitry Rokosov #define CLKID_ANALOG_CTRL	10
23*98872da6SDmitry Rokosov #define CLKID_PWR_CTRL		11
24*98872da6SDmitry Rokosov #define CLKID_PAD_CTRL		12
25*98872da6SDmitry Rokosov #define CLKID_SYS_CTRL		13
26*98872da6SDmitry Rokosov #define CLKID_TEMP_SENSOR	14
27*98872da6SDmitry Rokosov #define CLKID_AM2AXI_DIV	15
28*98872da6SDmitry Rokosov #define CLKID_SPICC_B		16
29*98872da6SDmitry Rokosov #define CLKID_SPICC_A		17
30*98872da6SDmitry Rokosov #define CLKID_MSR		18
31*98872da6SDmitry Rokosov #define CLKID_AUDIO		19
32*98872da6SDmitry Rokosov #define CLKID_JTAG_CTRL		20
33*98872da6SDmitry Rokosov #define CLKID_SARADC_EN		21
34*98872da6SDmitry Rokosov #define CLKID_PWM_EF		22
35*98872da6SDmitry Rokosov #define CLKID_PWM_CD		23
36*98872da6SDmitry Rokosov #define CLKID_PWM_AB		24
37*98872da6SDmitry Rokosov #define CLKID_CEC		25
38*98872da6SDmitry Rokosov #define CLKID_I2C_S		26
39*98872da6SDmitry Rokosov #define CLKID_IR_CTRL		27
40*98872da6SDmitry Rokosov #define CLKID_I2C_M_D		28
41*98872da6SDmitry Rokosov #define CLKID_I2C_M_C		29
42*98872da6SDmitry Rokosov #define CLKID_I2C_M_B		30
43*98872da6SDmitry Rokosov #define CLKID_I2C_M_A		31
44*98872da6SDmitry Rokosov #define CLKID_ACODEC		32
45*98872da6SDmitry Rokosov #define CLKID_OTP		33
46*98872da6SDmitry Rokosov #define CLKID_SD_EMMC_A		34
47*98872da6SDmitry Rokosov #define CLKID_USB_PHY		35
48*98872da6SDmitry Rokosov #define CLKID_USB_CTRL		36
49*98872da6SDmitry Rokosov #define CLKID_SYS_DSPB		37
50*98872da6SDmitry Rokosov #define CLKID_SYS_DSPA		38
51*98872da6SDmitry Rokosov #define CLKID_DMA		39
52*98872da6SDmitry Rokosov #define CLKID_IRQ_CTRL		40
53*98872da6SDmitry Rokosov #define CLKID_NIC		41
54*98872da6SDmitry Rokosov #define CLKID_GIC		42
55*98872da6SDmitry Rokosov #define CLKID_UART_C		43
56*98872da6SDmitry Rokosov #define CLKID_UART_B		44
57*98872da6SDmitry Rokosov #define CLKID_UART_A		45
58*98872da6SDmitry Rokosov #define CLKID_SYS_PSRAM		46
59*98872da6SDmitry Rokosov #define CLKID_RSA		47
60*98872da6SDmitry Rokosov #define CLKID_CORESIGHT		48
61*98872da6SDmitry Rokosov #define CLKID_AM2AXI_VAD	49
62*98872da6SDmitry Rokosov #define CLKID_AUDIO_VAD		50
63*98872da6SDmitry Rokosov #define CLKID_AXI_DMC		51
64*98872da6SDmitry Rokosov #define CLKID_AXI_PSRAM		52
65*98872da6SDmitry Rokosov #define CLKID_RAMB		53
66*98872da6SDmitry Rokosov #define CLKID_RAMA		54
67*98872da6SDmitry Rokosov #define CLKID_AXI_SPIFC		55
68*98872da6SDmitry Rokosov #define CLKID_AXI_NIC		56
69*98872da6SDmitry Rokosov #define CLKID_AXI_DMA		57
70*98872da6SDmitry Rokosov #define CLKID_CPU_CTRL		58
71*98872da6SDmitry Rokosov #define CLKID_ROM		59
72*98872da6SDmitry Rokosov #define CLKID_PROC_I2C		60
73*98872da6SDmitry Rokosov #define CLKID_DSPA_EN		63
74*98872da6SDmitry Rokosov #define CLKID_DSPA_EN_NIC	64
75*98872da6SDmitry Rokosov #define CLKID_DSPB_EN		65
76*98872da6SDmitry Rokosov #define CLKID_DSPB_EN_NIC	66
77*98872da6SDmitry Rokosov #define CLKID_RTC		67
78*98872da6SDmitry Rokosov #define CLKID_CECA_32K		68
79*98872da6SDmitry Rokosov #define CLKID_CECB_32K		69
80*98872da6SDmitry Rokosov #define CLKID_24M		70
81*98872da6SDmitry Rokosov #define CLKID_12M		71
82*98872da6SDmitry Rokosov #define CLKID_FCLK_DIV2_DIVN	72
83*98872da6SDmitry Rokosov #define CLKID_GEN		73
84*98872da6SDmitry Rokosov #define CLKID_SARADC		75
85*98872da6SDmitry Rokosov #define CLKID_PWM_A		76
86*98872da6SDmitry Rokosov #define CLKID_PWM_B		77
87*98872da6SDmitry Rokosov #define CLKID_PWM_C		78
88*98872da6SDmitry Rokosov #define CLKID_PWM_D		79
89*98872da6SDmitry Rokosov #define CLKID_PWM_E		80
90*98872da6SDmitry Rokosov #define CLKID_PWM_F		81
91*98872da6SDmitry Rokosov #define CLKID_SPICC		82
92*98872da6SDmitry Rokosov #define CLKID_TS		83
93*98872da6SDmitry Rokosov #define CLKID_SPIFC		84
94*98872da6SDmitry Rokosov #define CLKID_USB_BUS		85
95*98872da6SDmitry Rokosov #define CLKID_SD_EMMC		86
96*98872da6SDmitry Rokosov #define CLKID_PSRAM		87
97*98872da6SDmitry Rokosov #define CLKID_DMC		88
98*98872da6SDmitry Rokosov #define CLKID_DSPA_A_SEL	95
99*98872da6SDmitry Rokosov #define CLKID_DSPA_B_SEL	98
100*98872da6SDmitry Rokosov #define CLKID_DSPB_A_SEL	101
101*98872da6SDmitry Rokosov #define CLKID_DSPB_B_SEL	104
102*98872da6SDmitry Rokosov #define CLKID_CECB_32K_SEL_PRE	113
103*98872da6SDmitry Rokosov #define CLKID_CECB_32K_SEL	114
104*98872da6SDmitry Rokosov #define CLKID_CECA_32K_SEL_PRE	117
105*98872da6SDmitry Rokosov #define CLKID_CECA_32K_SEL	118
106*98872da6SDmitry Rokosov #define CLKID_GEN_SEL		121
107*98872da6SDmitry Rokosov #define CLKID_PWM_A_SEL		124
108*98872da6SDmitry Rokosov #define CLKID_PWM_B_SEL		126
109*98872da6SDmitry Rokosov #define CLKID_PWM_C_SEL		128
110*98872da6SDmitry Rokosov #define CLKID_PWM_D_SEL		130
111*98872da6SDmitry Rokosov #define CLKID_PWM_E_SEL		132
112*98872da6SDmitry Rokosov #define CLKID_PWM_F_SEL		134
113*98872da6SDmitry Rokosov #define CLKID_SD_EMMC_SEL2	147
114*98872da6SDmitry Rokosov 
115*98872da6SDmitry Rokosov #endif /* __A1_PERIPHERALS_CLKC_H */
116