16b3c5978SDinh Nguyen /* SPDX-License-Identifier: GPL-2.0 */ 26b3c5978SDinh Nguyen /* 36b3c5978SDinh Nguyen * Copyright (C) 2019, Intel Corporation 46b3c5978SDinh Nguyen */ 56b3c5978SDinh Nguyen 66b3c5978SDinh Nguyen #ifndef __AGILEX_CLOCK_H 76b3c5978SDinh Nguyen #define __AGILEX_CLOCK_H 86b3c5978SDinh Nguyen 96b3c5978SDinh Nguyen /* fixed rate clocks */ 106b3c5978SDinh Nguyen #define AGILEX_OSC1 0 116b3c5978SDinh Nguyen #define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 126b3c5978SDinh Nguyen #define AGILEX_CB_INTOSC_LS_CLK 2 136b3c5978SDinh Nguyen #define AGILEX_L4_SYS_FREE_CLK 3 146b3c5978SDinh Nguyen #define AGILEX_F2S_FREE_CLK 4 156b3c5978SDinh Nguyen 166b3c5978SDinh Nguyen /* PLL clocks */ 176b3c5978SDinh Nguyen #define AGILEX_MAIN_PLL_CLK 5 186b3c5978SDinh Nguyen #define AGILEX_MAIN_PLL_C0_CLK 6 196b3c5978SDinh Nguyen #define AGILEX_MAIN_PLL_C1_CLK 7 206b3c5978SDinh Nguyen #define AGILEX_MAIN_PLL_C2_CLK 8 216b3c5978SDinh Nguyen #define AGILEX_MAIN_PLL_C3_CLK 9 226b3c5978SDinh Nguyen #define AGILEX_PERIPH_PLL_CLK 10 236b3c5978SDinh Nguyen #define AGILEX_PERIPH_PLL_C0_CLK 11 246b3c5978SDinh Nguyen #define AGILEX_PERIPH_PLL_C1_CLK 12 256b3c5978SDinh Nguyen #define AGILEX_PERIPH_PLL_C2_CLK 13 266b3c5978SDinh Nguyen #define AGILEX_PERIPH_PLL_C3_CLK 14 276b3c5978SDinh Nguyen #define AGILEX_MPU_FREE_CLK 15 286b3c5978SDinh Nguyen #define AGILEX_MPU_CCU_CLK 16 296b3c5978SDinh Nguyen #define AGILEX_BOOT_CLK 17 306b3c5978SDinh Nguyen 316b3c5978SDinh Nguyen /* fixed factor clocks */ 326b3c5978SDinh Nguyen #define AGILEX_L3_MAIN_FREE_CLK 18 336b3c5978SDinh Nguyen #define AGILEX_NOC_FREE_CLK 19 346b3c5978SDinh Nguyen #define AGILEX_S2F_USR0_CLK 20 356b3c5978SDinh Nguyen #define AGILEX_NOC_CLK 21 366b3c5978SDinh Nguyen #define AGILEX_EMAC_A_FREE_CLK 22 376b3c5978SDinh Nguyen #define AGILEX_EMAC_B_FREE_CLK 23 386b3c5978SDinh Nguyen #define AGILEX_EMAC_PTP_FREE_CLK 24 396b3c5978SDinh Nguyen #define AGILEX_GPIO_DB_FREE_CLK 25 406b3c5978SDinh Nguyen #define AGILEX_SDMMC_FREE_CLK 26 416b3c5978SDinh Nguyen #define AGILEX_S2F_USER0_FREE_CLK 27 426b3c5978SDinh Nguyen #define AGILEX_S2F_USER1_FREE_CLK 28 436b3c5978SDinh Nguyen #define AGILEX_PSI_REF_FREE_CLK 29 446b3c5978SDinh Nguyen 456b3c5978SDinh Nguyen /* Gate clocks */ 466b3c5978SDinh Nguyen #define AGILEX_MPU_CLK 30 476b3c5978SDinh Nguyen #define AGILEX_MPU_L2RAM_CLK 31 486b3c5978SDinh Nguyen #define AGILEX_MPU_PERIPH_CLK 32 496b3c5978SDinh Nguyen #define AGILEX_L4_MAIN_CLK 33 506b3c5978SDinh Nguyen #define AGILEX_L4_MP_CLK 34 516b3c5978SDinh Nguyen #define AGILEX_L4_SP_CLK 35 526b3c5978SDinh Nguyen #define AGILEX_CS_AT_CLK 36 536b3c5978SDinh Nguyen #define AGILEX_CS_TRACE_CLK 37 546b3c5978SDinh Nguyen #define AGILEX_CS_PDBG_CLK 38 556b3c5978SDinh Nguyen #define AGILEX_CS_TIMER_CLK 39 566b3c5978SDinh Nguyen #define AGILEX_S2F_USER0_CLK 40 576b3c5978SDinh Nguyen #define AGILEX_EMAC0_CLK 41 586b3c5978SDinh Nguyen #define AGILEX_EMAC1_CLK 43 596b3c5978SDinh Nguyen #define AGILEX_EMAC2_CLK 44 606b3c5978SDinh Nguyen #define AGILEX_EMAC_PTP_CLK 45 616b3c5978SDinh Nguyen #define AGILEX_GPIO_DB_CLK 46 626b3c5978SDinh Nguyen #define AGILEX_NAND_CLK 47 636b3c5978SDinh Nguyen #define AGILEX_PSI_REF_CLK 48 646b3c5978SDinh Nguyen #define AGILEX_S2F_USER1_CLK 49 656b3c5978SDinh Nguyen #define AGILEX_SDMMC_CLK 50 666b3c5978SDinh Nguyen #define AGILEX_SPI_M_CLK 51 676b3c5978SDinh Nguyen #define AGILEX_USB_CLK 52 686b3c5978SDinh Nguyen #define AGILEX_NUM_CLKS 53 696b3c5978SDinh Nguyen 706b3c5978SDinh Nguyen #endif /* __AGILEX_CLOCK_H */ 71