106d42212SManivannan Sadhasivam // SPDX-License-Identifier: GPL-2.0+ 206d42212SManivannan Sadhasivam // 306d42212SManivannan Sadhasivam // Device Tree binding constants for Actions Semi S900 Clock Management Unit 406d42212SManivannan Sadhasivam // 506d42212SManivannan Sadhasivam // Copyright (c) 2014 Actions Semi Inc. 606d42212SManivannan Sadhasivam // Copyright (c) 2018 Linaro Ltd. 706d42212SManivannan Sadhasivam 806d42212SManivannan Sadhasivam #ifndef __DT_BINDINGS_CLOCK_S900_CMU_H 906d42212SManivannan Sadhasivam #define __DT_BINDINGS_CLOCK_S900_CMU_H 1006d42212SManivannan Sadhasivam 1106d42212SManivannan Sadhasivam #define CLK_NONE 0 1206d42212SManivannan Sadhasivam 1306d42212SManivannan Sadhasivam /* fixed rate clocks */ 1406d42212SManivannan Sadhasivam #define CLK_LOSC 1 1506d42212SManivannan Sadhasivam #define CLK_HOSC 2 1606d42212SManivannan Sadhasivam 1706d42212SManivannan Sadhasivam /* pll clocks */ 1806d42212SManivannan Sadhasivam #define CLK_CORE_PLL 3 1906d42212SManivannan Sadhasivam #define CLK_DEV_PLL 4 2006d42212SManivannan Sadhasivam #define CLK_DDR_PLL 5 2106d42212SManivannan Sadhasivam #define CLK_NAND_PLL 6 2206d42212SManivannan Sadhasivam #define CLK_DISPLAY_PLL 7 2306d42212SManivannan Sadhasivam #define CLK_DSI_PLL 8 2406d42212SManivannan Sadhasivam #define CLK_ASSIST_PLL 9 2506d42212SManivannan Sadhasivam #define CLK_AUDIO_PLL 10 2606d42212SManivannan Sadhasivam 2706d42212SManivannan Sadhasivam /* system clock */ 2806d42212SManivannan Sadhasivam #define CLK_CPU 15 2906d42212SManivannan Sadhasivam #define CLK_DEV 16 3006d42212SManivannan Sadhasivam #define CLK_NOC 17 3106d42212SManivannan Sadhasivam #define CLK_NOC_MUX 18 3206d42212SManivannan Sadhasivam #define CLK_NOC_DIV 19 3306d42212SManivannan Sadhasivam #define CLK_AHB 20 3406d42212SManivannan Sadhasivam #define CLK_APB 21 3506d42212SManivannan Sadhasivam #define CLK_DMAC 22 3606d42212SManivannan Sadhasivam 3706d42212SManivannan Sadhasivam /* peripheral device clock */ 3806d42212SManivannan Sadhasivam #define CLK_GPIO 23 3906d42212SManivannan Sadhasivam 4006d42212SManivannan Sadhasivam #define CLK_BISP 24 4106d42212SManivannan Sadhasivam #define CLK_CSI0 25 4206d42212SManivannan Sadhasivam #define CLK_CSI1 26 4306d42212SManivannan Sadhasivam 4406d42212SManivannan Sadhasivam #define CLK_DE0 27 4506d42212SManivannan Sadhasivam #define CLK_DE1 28 4606d42212SManivannan Sadhasivam #define CLK_DE2 29 4706d42212SManivannan Sadhasivam #define CLK_DE3 30 4806d42212SManivannan Sadhasivam #define CLK_DSI 32 4906d42212SManivannan Sadhasivam 5006d42212SManivannan Sadhasivam #define CLK_GPU 33 5106d42212SManivannan Sadhasivam #define CLK_GPU_CORE 34 5206d42212SManivannan Sadhasivam #define CLK_GPU_MEM 35 5306d42212SManivannan Sadhasivam #define CLK_GPU_SYS 36 5406d42212SManivannan Sadhasivam 5506d42212SManivannan Sadhasivam #define CLK_HDE 37 5606d42212SManivannan Sadhasivam #define CLK_I2C0 38 5706d42212SManivannan Sadhasivam #define CLK_I2C1 39 5806d42212SManivannan Sadhasivam #define CLK_I2C2 40 5906d42212SManivannan Sadhasivam #define CLK_I2C3 41 6006d42212SManivannan Sadhasivam #define CLK_I2C4 42 6106d42212SManivannan Sadhasivam #define CLK_I2C5 43 6206d42212SManivannan Sadhasivam #define CLK_I2SRX 44 6306d42212SManivannan Sadhasivam #define CLK_I2STX 45 6406d42212SManivannan Sadhasivam #define CLK_IMX 46 6506d42212SManivannan Sadhasivam #define CLK_LCD 47 6606d42212SManivannan Sadhasivam #define CLK_NAND0 48 6706d42212SManivannan Sadhasivam #define CLK_NAND1 49 6806d42212SManivannan Sadhasivam #define CLK_PWM0 50 6906d42212SManivannan Sadhasivam #define CLK_PWM1 51 7006d42212SManivannan Sadhasivam #define CLK_PWM2 52 7106d42212SManivannan Sadhasivam #define CLK_PWM3 53 7206d42212SManivannan Sadhasivam #define CLK_PWM4 54 7306d42212SManivannan Sadhasivam #define CLK_PWM5 55 7406d42212SManivannan Sadhasivam #define CLK_SD0 56 7506d42212SManivannan Sadhasivam #define CLK_SD1 57 7606d42212SManivannan Sadhasivam #define CLK_SD2 58 7706d42212SManivannan Sadhasivam #define CLK_SD3 59 7806d42212SManivannan Sadhasivam #define CLK_SENSOR 60 7906d42212SManivannan Sadhasivam #define CLK_SPEED_SENSOR 61 8006d42212SManivannan Sadhasivam #define CLK_SPI0 62 8106d42212SManivannan Sadhasivam #define CLK_SPI1 63 8206d42212SManivannan Sadhasivam #define CLK_SPI2 64 8306d42212SManivannan Sadhasivam #define CLK_SPI3 65 8406d42212SManivannan Sadhasivam #define CLK_THERMAL_SENSOR 66 8506d42212SManivannan Sadhasivam #define CLK_UART0 67 8606d42212SManivannan Sadhasivam #define CLK_UART1 68 8706d42212SManivannan Sadhasivam #define CLK_UART2 69 8806d42212SManivannan Sadhasivam #define CLK_UART3 70 8906d42212SManivannan Sadhasivam #define CLK_UART4 71 9006d42212SManivannan Sadhasivam #define CLK_UART5 72 9106d42212SManivannan Sadhasivam #define CLK_UART6 73 9206d42212SManivannan Sadhasivam #define CLK_VCE 74 9306d42212SManivannan Sadhasivam #define CLK_VDE 75 9406d42212SManivannan Sadhasivam 9506d42212SManivannan Sadhasivam #define CLK_USB3_480MPLL0 76 9606d42212SManivannan Sadhasivam #define CLK_USB3_480MPHY0 77 9706d42212SManivannan Sadhasivam #define CLK_USB3_5GPHY 78 9806d42212SManivannan Sadhasivam #define CLK_USB3_CCE 79 9906d42212SManivannan Sadhasivam #define CLK_USB3_MAC 80 10006d42212SManivannan Sadhasivam 10106d42212SManivannan Sadhasivam #define CLK_TIMER 83 10206d42212SManivannan Sadhasivam 10306d42212SManivannan Sadhasivam #define CLK_HDMI_AUDIO 84 10406d42212SManivannan Sadhasivam 10506d42212SManivannan Sadhasivam #define CLK_24M 85 10606d42212SManivannan Sadhasivam 10706d42212SManivannan Sadhasivam #define CLK_EDP 86 10806d42212SManivannan Sadhasivam 10906d42212SManivannan Sadhasivam #define CLK_24M_EDP 87 11006d42212SManivannan Sadhasivam #define CLK_EDP_PLL 88 11106d42212SManivannan Sadhasivam #define CLK_EDP_LINK 89 11206d42212SManivannan Sadhasivam 11306d42212SManivannan Sadhasivam #define CLK_USB2H0_PLLEN 90 11406d42212SManivannan Sadhasivam #define CLK_USB2H0_PHY 91 11506d42212SManivannan Sadhasivam #define CLK_USB2H0_CCE 92 11606d42212SManivannan Sadhasivam #define CLK_USB2H1_PLLEN 93 11706d42212SManivannan Sadhasivam #define CLK_USB2H1_PHY 94 11806d42212SManivannan Sadhasivam #define CLK_USB2H1_CCE 95 11906d42212SManivannan Sadhasivam 12006d42212SManivannan Sadhasivam #define CLK_DDR0 96 12106d42212SManivannan Sadhasivam #define CLK_DDR1 97 12206d42212SManivannan Sadhasivam #define CLK_DMM 98 12306d42212SManivannan Sadhasivam 12406d42212SManivannan Sadhasivam #define CLK_ETH_MAC 99 12506d42212SManivannan Sadhasivam #define CLK_RMII_REF 100 12606d42212SManivannan Sadhasivam 12706d42212SManivannan Sadhasivam #define CLK_NR_CLKS (CLK_RMII_REF + 1) 12806d42212SManivannan Sadhasivam 12906d42212SManivannan Sadhasivam #endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */ 130