1 /* Common header for intel-gtt.ko and i915.ko */ 2 3 #ifndef _DRM_INTEL_GTT_H 4 #define _DRM_INTEL_GTT_H 5 6 struct intel_gtt { 7 /* Size of memory reserved for graphics by the BIOS */ 8 unsigned int stolen_size; 9 /* Total number of gtt entries. */ 10 unsigned int gtt_total_entries; 11 /* Part of the gtt that is mappable by the cpu, for those chips where 12 * this is not the full gtt. */ 13 unsigned int gtt_mappable_entries; 14 /* Whether i915 needs to use the dmar apis or not. */ 15 unsigned int needs_dmar : 1; 16 /* Share the scratch page dma with ppgtts. */ 17 dma_addr_t scratch_page_dma; 18 struct page *scratch_page; 19 /* needed for ioremap in drm/i915 */ 20 phys_addr_t gma_bus_addr; 21 } *intel_gtt_get(void); 22 23 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, 24 struct agp_bridge_data *bridge); 25 void intel_gmch_remove(void); 26 27 bool intel_enable_gtt(void); 28 29 void intel_gtt_chipset_flush(void); 30 void intel_gtt_insert_sg_entries(struct sg_table *st, 31 unsigned int pg_start, 32 unsigned int flags); 33 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries); 34 35 /* Special gtt memory types */ 36 #define AGP_DCACHE_MEMORY 1 37 #define AGP_PHYS_MEMORY 2 38 39 /* flag for GFDT type */ 40 #define AGP_USER_CACHED_MEMORY_GFDT (1 << 3) 41 42 #ifdef CONFIG_INTEL_IOMMU 43 extern int intel_iommu_gfx_mapped; 44 #endif 45 46 #endif 47