10ade6386SDaniel Vetter /* Common header for intel-gtt.ko and i915.ko */ 20ade6386SDaniel Vetter 30ade6386SDaniel Vetter #ifndef _DRM_INTEL_GTT_H 40ade6386SDaniel Vetter #define _DRM_INTEL_GTT_H 5c64f7ba5SChris Wilson 6c64f7ba5SChris Wilson const struct intel_gtt { 7c64f7ba5SChris Wilson /* Size of memory reserved for graphics by the BIOS */ 8c64f7ba5SChris Wilson unsigned int stolen_size; 90ade6386SDaniel Vetter /* Total number of gtt entries. */ 100ade6386SDaniel Vetter unsigned int gtt_total_entries; 110ade6386SDaniel Vetter /* Part of the gtt that is mappable by the cpu, for those chips where 120ade6386SDaniel Vetter * this is not the full gtt. */ 130ade6386SDaniel Vetter unsigned int gtt_mappable_entries; 144080775bSDaniel Vetter /* Whether i915 needs to use the dmar apis or not. */ 154080775bSDaniel Vetter unsigned int needs_dmar : 1; 165c042287SBen Widawsky /* Whether we idle the gpu before mapping/unmapping */ 175c042287SBen Widawsky unsigned int do_idle_maps : 1; 1850a4c4a9SDaniel Vetter /* Share the scratch page dma with ppgtts. */ 1950a4c4a9SDaniel Vetter dma_addr_t scratch_page_dma; 20428ccb21SDaniel Vetter /* for ppgtt PDE access */ 21428ccb21SDaniel Vetter u32 __iomem *gtt; 22dd2757f8SDaniel Vetter /* needed for ioremap in drm/i915 */ 23dd2757f8SDaniel Vetter phys_addr_t gma_bus_addr; 24c64f7ba5SChris Wilson } *intel_gtt_get(void); 2519966754SDaniel Vetter 2614be93ddSDaniel Vetter int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, 2714be93ddSDaniel Vetter struct agp_bridge_data *bridge); 2814be93ddSDaniel Vetter void intel_gmch_remove(void); 2914be93ddSDaniel Vetter 308ecd1a66SDaniel Vetter bool intel_enable_gtt(void); 318ecd1a66SDaniel Vetter 3240ce6575SDaniel Vetter void intel_gtt_chipset_flush(void); 334080775bSDaniel Vetter void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg); 344080775bSDaniel Vetter void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries); 354080775bSDaniel Vetter int intel_gtt_map_memory(struct page **pages, unsigned int num_entries, 364080775bSDaniel Vetter struct scatterlist **sg_list, int *num_sg); 374080775bSDaniel Vetter void intel_gtt_insert_sg_entries(struct scatterlist *sg_list, 384080775bSDaniel Vetter unsigned int sg_len, 394080775bSDaniel Vetter unsigned int pg_start, 404080775bSDaniel Vetter unsigned int flags); 414080775bSDaniel Vetter void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries, 424080775bSDaniel Vetter struct page **pages, unsigned int flags); 4323ed992aSDaniel Vetter 4423ed992aSDaniel Vetter /* Special gtt memory types */ 4523ed992aSDaniel Vetter #define AGP_DCACHE_MEMORY 1 4623ed992aSDaniel Vetter #define AGP_PHYS_MEMORY 2 4723ed992aSDaniel Vetter 4823ed992aSDaniel Vetter /* New caching attributes for gen6/sandybridge */ 4923ed992aSDaniel Vetter #define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2) 5023ed992aSDaniel Vetter #define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4) 5123ed992aSDaniel Vetter 5223ed992aSDaniel Vetter /* flag for GFDT type */ 5323ed992aSDaniel Vetter #define AGP_USER_CACHED_MEMORY_GFDT (1 << 3) 5423ed992aSDaniel Vetter 55650dc07eSDaniel Vetter #ifdef CONFIG_INTEL_IOMMU 56650dc07eSDaniel Vetter extern int intel_iommu_gfx_mapped; 57650dc07eSDaniel Vetter #endif 58650dc07eSDaniel Vetter 590ade6386SDaniel Vetter #endif 60