1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _I915_DRM_H_ 28 #define _I915_DRM_H_ 29 30 #include "drm.h" 31 32 /* Please note that modifications to all structs defined here are 33 * subject to backwards-compatibility constraints. 34 */ 35 36 #ifdef __KERNEL__ 37 /* For use by IPS driver */ 38 extern unsigned long i915_read_mch_val(void); 39 extern bool i915_gpu_raise(void); 40 extern bool i915_gpu_lower(void); 41 extern bool i915_gpu_busy(void); 42 extern bool i915_gpu_turbo_disable(void); 43 #endif 44 45 /* Each region is a minimum of 16k, and there are at most 255 of them. 46 */ 47 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 48 * of chars for next/prev indices */ 49 #define I915_LOG_MIN_TEX_REGION_SIZE 14 50 51 typedef struct _drm_i915_init { 52 enum { 53 I915_INIT_DMA = 0x01, 54 I915_CLEANUP_DMA = 0x02, 55 I915_RESUME_DMA = 0x03 56 } func; 57 unsigned int mmio_offset; 58 int sarea_priv_offset; 59 unsigned int ring_start; 60 unsigned int ring_end; 61 unsigned int ring_size; 62 unsigned int front_offset; 63 unsigned int back_offset; 64 unsigned int depth_offset; 65 unsigned int w; 66 unsigned int h; 67 unsigned int pitch; 68 unsigned int pitch_bits; 69 unsigned int back_pitch; 70 unsigned int depth_pitch; 71 unsigned int cpp; 72 unsigned int chipset; 73 } drm_i915_init_t; 74 75 typedef struct _drm_i915_sarea { 76 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 77 int last_upload; /* last time texture was uploaded */ 78 int last_enqueue; /* last time a buffer was enqueued */ 79 int last_dispatch; /* age of the most recently dispatched buffer */ 80 int ctxOwner; /* last context to upload state */ 81 int texAge; 82 int pf_enabled; /* is pageflipping allowed? */ 83 int pf_active; 84 int pf_current_page; /* which buffer is being displayed? */ 85 int perf_boxes; /* performance boxes to be displayed */ 86 int width, height; /* screen size in pixels */ 87 88 drm_handle_t front_handle; 89 int front_offset; 90 int front_size; 91 92 drm_handle_t back_handle; 93 int back_offset; 94 int back_size; 95 96 drm_handle_t depth_handle; 97 int depth_offset; 98 int depth_size; 99 100 drm_handle_t tex_handle; 101 int tex_offset; 102 int tex_size; 103 int log_tex_granularity; 104 int pitch; 105 int rotation; /* 0, 90, 180 or 270 */ 106 int rotated_offset; 107 int rotated_size; 108 int rotated_pitch; 109 int virtualX, virtualY; 110 111 unsigned int front_tiled; 112 unsigned int back_tiled; 113 unsigned int depth_tiled; 114 unsigned int rotated_tiled; 115 unsigned int rotated2_tiled; 116 117 int pipeA_x; 118 int pipeA_y; 119 int pipeA_w; 120 int pipeA_h; 121 int pipeB_x; 122 int pipeB_y; 123 int pipeB_w; 124 int pipeB_h; 125 126 /* fill out some space for old userspace triple buffer */ 127 drm_handle_t unused_handle; 128 __u32 unused1, unused2, unused3; 129 130 /* buffer object handles for static buffers. May change 131 * over the lifetime of the client. 132 */ 133 __u32 front_bo_handle; 134 __u32 back_bo_handle; 135 __u32 unused_bo_handle; 136 __u32 depth_bo_handle; 137 138 } drm_i915_sarea_t; 139 140 /* due to userspace building against these headers we need some compat here */ 141 #define planeA_x pipeA_x 142 #define planeA_y pipeA_y 143 #define planeA_w pipeA_w 144 #define planeA_h pipeA_h 145 #define planeB_x pipeB_x 146 #define planeB_y pipeB_y 147 #define planeB_w pipeB_w 148 #define planeB_h pipeB_h 149 150 /* Flags for perf_boxes 151 */ 152 #define I915_BOX_RING_EMPTY 0x1 153 #define I915_BOX_FLIP 0x2 154 #define I915_BOX_WAIT 0x4 155 #define I915_BOX_TEXTURE_LOAD 0x8 156 #define I915_BOX_LOST_CONTEXT 0x10 157 158 /* I915 specific ioctls 159 * The device specific ioctl range is 0x40 to 0x79. 160 */ 161 #define DRM_I915_INIT 0x00 162 #define DRM_I915_FLUSH 0x01 163 #define DRM_I915_FLIP 0x02 164 #define DRM_I915_BATCHBUFFER 0x03 165 #define DRM_I915_IRQ_EMIT 0x04 166 #define DRM_I915_IRQ_WAIT 0x05 167 #define DRM_I915_GETPARAM 0x06 168 #define DRM_I915_SETPARAM 0x07 169 #define DRM_I915_ALLOC 0x08 170 #define DRM_I915_FREE 0x09 171 #define DRM_I915_INIT_HEAP 0x0a 172 #define DRM_I915_CMDBUFFER 0x0b 173 #define DRM_I915_DESTROY_HEAP 0x0c 174 #define DRM_I915_SET_VBLANK_PIPE 0x0d 175 #define DRM_I915_GET_VBLANK_PIPE 0x0e 176 #define DRM_I915_VBLANK_SWAP 0x0f 177 #define DRM_I915_HWS_ADDR 0x11 178 #define DRM_I915_GEM_INIT 0x13 179 #define DRM_I915_GEM_EXECBUFFER 0x14 180 #define DRM_I915_GEM_PIN 0x15 181 #define DRM_I915_GEM_UNPIN 0x16 182 #define DRM_I915_GEM_BUSY 0x17 183 #define DRM_I915_GEM_THROTTLE 0x18 184 #define DRM_I915_GEM_ENTERVT 0x19 185 #define DRM_I915_GEM_LEAVEVT 0x1a 186 #define DRM_I915_GEM_CREATE 0x1b 187 #define DRM_I915_GEM_PREAD 0x1c 188 #define DRM_I915_GEM_PWRITE 0x1d 189 #define DRM_I915_GEM_MMAP 0x1e 190 #define DRM_I915_GEM_SET_DOMAIN 0x1f 191 #define DRM_I915_GEM_SW_FINISH 0x20 192 #define DRM_I915_GEM_SET_TILING 0x21 193 #define DRM_I915_GEM_GET_TILING 0x22 194 #define DRM_I915_GEM_GET_APERTURE 0x23 195 #define DRM_I915_GEM_MMAP_GTT 0x24 196 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 197 #define DRM_I915_GEM_MADVISE 0x26 198 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 199 #define DRM_I915_OVERLAY_ATTRS 0x28 200 #define DRM_I915_GEM_EXECBUFFER2 0x29 201 202 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 203 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 204 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 205 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 206 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 207 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 208 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 209 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 210 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 211 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 212 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 213 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 214 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 215 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 216 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 217 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 218 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 219 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 220 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 221 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 222 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 223 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 224 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 225 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 226 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 227 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 228 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 229 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 230 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 231 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 232 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 233 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 234 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 235 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 236 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 237 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 238 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 239 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 240 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image) 241 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 242 243 /* Allow drivers to submit batchbuffers directly to hardware, relying 244 * on the security mechanisms provided by hardware. 245 */ 246 typedef struct drm_i915_batchbuffer { 247 int start; /* agp offset */ 248 int used; /* nr bytes in use */ 249 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 250 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 251 int num_cliprects; /* mulitpass with multiple cliprects? */ 252 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 253 } drm_i915_batchbuffer_t; 254 255 /* As above, but pass a pointer to userspace buffer which can be 256 * validated by the kernel prior to sending to hardware. 257 */ 258 typedef struct _drm_i915_cmdbuffer { 259 char __user *buf; /* pointer to userspace command buffer */ 260 int sz; /* nr bytes in buf */ 261 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 262 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 263 int num_cliprects; /* mulitpass with multiple cliprects? */ 264 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 265 } drm_i915_cmdbuffer_t; 266 267 /* Userspace can request & wait on irq's: 268 */ 269 typedef struct drm_i915_irq_emit { 270 int __user *irq_seq; 271 } drm_i915_irq_emit_t; 272 273 typedef struct drm_i915_irq_wait { 274 int irq_seq; 275 } drm_i915_irq_wait_t; 276 277 /* Ioctl to query kernel params: 278 */ 279 #define I915_PARAM_IRQ_ACTIVE 1 280 #define I915_PARAM_ALLOW_BATCHBUFFER 2 281 #define I915_PARAM_LAST_DISPATCH 3 282 #define I915_PARAM_CHIPSET_ID 4 283 #define I915_PARAM_HAS_GEM 5 284 #define I915_PARAM_NUM_FENCES_AVAIL 6 285 #define I915_PARAM_HAS_OVERLAY 7 286 #define I915_PARAM_HAS_PAGEFLIPPING 8 287 #define I915_PARAM_HAS_EXECBUF2 9 288 #define I915_PARAM_HAS_BSD 10 289 #define I915_PARAM_HAS_BLT 11 290 291 typedef struct drm_i915_getparam { 292 int param; 293 int __user *value; 294 } drm_i915_getparam_t; 295 296 /* Ioctl to set kernel params: 297 */ 298 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 299 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 300 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 301 #define I915_SETPARAM_NUM_USED_FENCES 4 302 303 typedef struct drm_i915_setparam { 304 int param; 305 int value; 306 } drm_i915_setparam_t; 307 308 /* A memory manager for regions of shared memory: 309 */ 310 #define I915_MEM_REGION_AGP 1 311 312 typedef struct drm_i915_mem_alloc { 313 int region; 314 int alignment; 315 int size; 316 int __user *region_offset; /* offset from start of fb or agp */ 317 } drm_i915_mem_alloc_t; 318 319 typedef struct drm_i915_mem_free { 320 int region; 321 int region_offset; 322 } drm_i915_mem_free_t; 323 324 typedef struct drm_i915_mem_init_heap { 325 int region; 326 int size; 327 int start; 328 } drm_i915_mem_init_heap_t; 329 330 /* Allow memory manager to be torn down and re-initialized (eg on 331 * rotate): 332 */ 333 typedef struct drm_i915_mem_destroy_heap { 334 int region; 335 } drm_i915_mem_destroy_heap_t; 336 337 /* Allow X server to configure which pipes to monitor for vblank signals 338 */ 339 #define DRM_I915_VBLANK_PIPE_A 1 340 #define DRM_I915_VBLANK_PIPE_B 2 341 342 typedef struct drm_i915_vblank_pipe { 343 int pipe; 344 } drm_i915_vblank_pipe_t; 345 346 /* Schedule buffer swap at given vertical blank: 347 */ 348 typedef struct drm_i915_vblank_swap { 349 drm_drawable_t drawable; 350 enum drm_vblank_seq_type seqtype; 351 unsigned int sequence; 352 } drm_i915_vblank_swap_t; 353 354 typedef struct drm_i915_hws_addr { 355 __u64 addr; 356 } drm_i915_hws_addr_t; 357 358 struct drm_i915_gem_init { 359 /** 360 * Beginning offset in the GTT to be managed by the DRM memory 361 * manager. 362 */ 363 __u64 gtt_start; 364 /** 365 * Ending offset in the GTT to be managed by the DRM memory 366 * manager. 367 */ 368 __u64 gtt_end; 369 }; 370 371 struct drm_i915_gem_create { 372 /** 373 * Requested size for the object. 374 * 375 * The (page-aligned) allocated size for the object will be returned. 376 */ 377 __u64 size; 378 /** 379 * Returned handle for the object. 380 * 381 * Object handles are nonzero. 382 */ 383 __u32 handle; 384 __u32 pad; 385 }; 386 387 struct drm_i915_gem_pread { 388 /** Handle for the object being read. */ 389 __u32 handle; 390 __u32 pad; 391 /** Offset into the object to read from */ 392 __u64 offset; 393 /** Length of data to read */ 394 __u64 size; 395 /** 396 * Pointer to write the data into. 397 * 398 * This is a fixed-size type for 32/64 compatibility. 399 */ 400 __u64 data_ptr; 401 }; 402 403 struct drm_i915_gem_pwrite { 404 /** Handle for the object being written to. */ 405 __u32 handle; 406 __u32 pad; 407 /** Offset into the object to write to */ 408 __u64 offset; 409 /** Length of data to write */ 410 __u64 size; 411 /** 412 * Pointer to read the data from. 413 * 414 * This is a fixed-size type for 32/64 compatibility. 415 */ 416 __u64 data_ptr; 417 }; 418 419 struct drm_i915_gem_mmap { 420 /** Handle for the object being mapped. */ 421 __u32 handle; 422 __u32 pad; 423 /** Offset in the object to map. */ 424 __u64 offset; 425 /** 426 * Length of data to map. 427 * 428 * The value will be page-aligned. 429 */ 430 __u64 size; 431 /** 432 * Returned pointer the data was mapped at. 433 * 434 * This is a fixed-size type for 32/64 compatibility. 435 */ 436 __u64 addr_ptr; 437 }; 438 439 struct drm_i915_gem_mmap_gtt { 440 /** Handle for the object being mapped. */ 441 __u32 handle; 442 __u32 pad; 443 /** 444 * Fake offset to use for subsequent mmap call 445 * 446 * This is a fixed-size type for 32/64 compatibility. 447 */ 448 __u64 offset; 449 }; 450 451 struct drm_i915_gem_set_domain { 452 /** Handle for the object */ 453 __u32 handle; 454 455 /** New read domains */ 456 __u32 read_domains; 457 458 /** New write domain */ 459 __u32 write_domain; 460 }; 461 462 struct drm_i915_gem_sw_finish { 463 /** Handle for the object */ 464 __u32 handle; 465 }; 466 467 struct drm_i915_gem_relocation_entry { 468 /** 469 * Handle of the buffer being pointed to by this relocation entry. 470 * 471 * It's appealing to make this be an index into the mm_validate_entry 472 * list to refer to the buffer, but this allows the driver to create 473 * a relocation list for state buffers and not re-write it per 474 * exec using the buffer. 475 */ 476 __u32 target_handle; 477 478 /** 479 * Value to be added to the offset of the target buffer to make up 480 * the relocation entry. 481 */ 482 __u32 delta; 483 484 /** Offset in the buffer the relocation entry will be written into */ 485 __u64 offset; 486 487 /** 488 * Offset value of the target buffer that the relocation entry was last 489 * written as. 490 * 491 * If the buffer has the same offset as last time, we can skip syncing 492 * and writing the relocation. This value is written back out by 493 * the execbuffer ioctl when the relocation is written. 494 */ 495 __u64 presumed_offset; 496 497 /** 498 * Target memory domains read by this operation. 499 */ 500 __u32 read_domains; 501 502 /** 503 * Target memory domains written by this operation. 504 * 505 * Note that only one domain may be written by the whole 506 * execbuffer operation, so that where there are conflicts, 507 * the application will get -EINVAL back. 508 */ 509 __u32 write_domain; 510 }; 511 512 /** @{ 513 * Intel memory domains 514 * 515 * Most of these just align with the various caches in 516 * the system and are used to flush and invalidate as 517 * objects end up cached in different domains. 518 */ 519 /** CPU cache */ 520 #define I915_GEM_DOMAIN_CPU 0x00000001 521 /** Render cache, used by 2D and 3D drawing */ 522 #define I915_GEM_DOMAIN_RENDER 0x00000002 523 /** Sampler cache, used by texture engine */ 524 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 525 /** Command queue, used to load batch buffers */ 526 #define I915_GEM_DOMAIN_COMMAND 0x00000008 527 /** Instruction cache, used by shader programs */ 528 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 529 /** Vertex address cache */ 530 #define I915_GEM_DOMAIN_VERTEX 0x00000020 531 /** GTT domain - aperture and scanout */ 532 #define I915_GEM_DOMAIN_GTT 0x00000040 533 /** @} */ 534 535 struct drm_i915_gem_exec_object { 536 /** 537 * User's handle for a buffer to be bound into the GTT for this 538 * operation. 539 */ 540 __u32 handle; 541 542 /** Number of relocations to be performed on this buffer */ 543 __u32 relocation_count; 544 /** 545 * Pointer to array of struct drm_i915_gem_relocation_entry containing 546 * the relocations to be performed in this buffer. 547 */ 548 __u64 relocs_ptr; 549 550 /** Required alignment in graphics aperture */ 551 __u64 alignment; 552 553 /** 554 * Returned value of the updated offset of the object, for future 555 * presumed_offset writes. 556 */ 557 __u64 offset; 558 }; 559 560 struct drm_i915_gem_execbuffer { 561 /** 562 * List of buffers to be validated with their relocations to be 563 * performend on them. 564 * 565 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 566 * 567 * These buffers must be listed in an order such that all relocations 568 * a buffer is performing refer to buffers that have already appeared 569 * in the validate list. 570 */ 571 __u64 buffers_ptr; 572 __u32 buffer_count; 573 574 /** Offset in the batchbuffer to start execution from. */ 575 __u32 batch_start_offset; 576 /** Bytes used in batchbuffer from batch_start_offset */ 577 __u32 batch_len; 578 __u32 DR1; 579 __u32 DR4; 580 __u32 num_cliprects; 581 /** This is a struct drm_clip_rect *cliprects */ 582 __u64 cliprects_ptr; 583 }; 584 585 struct drm_i915_gem_exec_object2 { 586 /** 587 * User's handle for a buffer to be bound into the GTT for this 588 * operation. 589 */ 590 __u32 handle; 591 592 /** Number of relocations to be performed on this buffer */ 593 __u32 relocation_count; 594 /** 595 * Pointer to array of struct drm_i915_gem_relocation_entry containing 596 * the relocations to be performed in this buffer. 597 */ 598 __u64 relocs_ptr; 599 600 /** Required alignment in graphics aperture */ 601 __u64 alignment; 602 603 /** 604 * Returned value of the updated offset of the object, for future 605 * presumed_offset writes. 606 */ 607 __u64 offset; 608 609 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 610 __u64 flags; 611 __u64 rsvd1; 612 __u64 rsvd2; 613 }; 614 615 struct drm_i915_gem_execbuffer2 { 616 /** 617 * List of gem_exec_object2 structs 618 */ 619 __u64 buffers_ptr; 620 __u32 buffer_count; 621 622 /** Offset in the batchbuffer to start execution from. */ 623 __u32 batch_start_offset; 624 /** Bytes used in batchbuffer from batch_start_offset */ 625 __u32 batch_len; 626 __u32 DR1; 627 __u32 DR4; 628 __u32 num_cliprects; 629 /** This is a struct drm_clip_rect *cliprects */ 630 __u64 cliprects_ptr; 631 #define I915_EXEC_RING_MASK (7<<0) 632 #define I915_EXEC_DEFAULT (0<<0) 633 #define I915_EXEC_RENDER (1<<0) 634 #define I915_EXEC_BSD (2<<0) 635 #define I915_EXEC_BLT (3<<0) 636 __u64 flags; 637 __u64 rsvd1; 638 __u64 rsvd2; 639 }; 640 641 struct drm_i915_gem_pin { 642 /** Handle of the buffer to be pinned. */ 643 __u32 handle; 644 __u32 pad; 645 646 /** alignment required within the aperture */ 647 __u64 alignment; 648 649 /** Returned GTT offset of the buffer. */ 650 __u64 offset; 651 }; 652 653 struct drm_i915_gem_unpin { 654 /** Handle of the buffer to be unpinned. */ 655 __u32 handle; 656 __u32 pad; 657 }; 658 659 struct drm_i915_gem_busy { 660 /** Handle of the buffer to check for busy */ 661 __u32 handle; 662 663 /** Return busy status (1 if busy, 0 if idle) */ 664 __u32 busy; 665 }; 666 667 #define I915_TILING_NONE 0 668 #define I915_TILING_X 1 669 #define I915_TILING_Y 2 670 671 #define I915_BIT_6_SWIZZLE_NONE 0 672 #define I915_BIT_6_SWIZZLE_9 1 673 #define I915_BIT_6_SWIZZLE_9_10 2 674 #define I915_BIT_6_SWIZZLE_9_11 3 675 #define I915_BIT_6_SWIZZLE_9_10_11 4 676 /* Not seen by userland */ 677 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 678 /* Seen by userland. */ 679 #define I915_BIT_6_SWIZZLE_9_17 6 680 #define I915_BIT_6_SWIZZLE_9_10_17 7 681 682 struct drm_i915_gem_set_tiling { 683 /** Handle of the buffer to have its tiling state updated */ 684 __u32 handle; 685 686 /** 687 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 688 * I915_TILING_Y). 689 * 690 * This value is to be set on request, and will be updated by the 691 * kernel on successful return with the actual chosen tiling layout. 692 * 693 * The tiling mode may be demoted to I915_TILING_NONE when the system 694 * has bit 6 swizzling that can't be managed correctly by GEM. 695 * 696 * Buffer contents become undefined when changing tiling_mode. 697 */ 698 __u32 tiling_mode; 699 700 /** 701 * Stride in bytes for the object when in I915_TILING_X or 702 * I915_TILING_Y. 703 */ 704 __u32 stride; 705 706 /** 707 * Returned address bit 6 swizzling required for CPU access through 708 * mmap mapping. 709 */ 710 __u32 swizzle_mode; 711 }; 712 713 struct drm_i915_gem_get_tiling { 714 /** Handle of the buffer to get tiling state for. */ 715 __u32 handle; 716 717 /** 718 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 719 * I915_TILING_Y). 720 */ 721 __u32 tiling_mode; 722 723 /** 724 * Returned address bit 6 swizzling required for CPU access through 725 * mmap mapping. 726 */ 727 __u32 swizzle_mode; 728 }; 729 730 struct drm_i915_gem_get_aperture { 731 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 732 __u64 aper_size; 733 734 /** 735 * Available space in the aperture used by i915_gem_execbuffer, in 736 * bytes 737 */ 738 __u64 aper_available_size; 739 }; 740 741 struct drm_i915_get_pipe_from_crtc_id { 742 /** ID of CRTC being requested **/ 743 __u32 crtc_id; 744 745 /** pipe of requested CRTC **/ 746 __u32 pipe; 747 }; 748 749 #define I915_MADV_WILLNEED 0 750 #define I915_MADV_DONTNEED 1 751 #define __I915_MADV_PURGED 2 /* internal state */ 752 753 struct drm_i915_gem_madvise { 754 /** Handle of the buffer to change the backing store advice */ 755 __u32 handle; 756 757 /* Advice: either the buffer will be needed again in the near future, 758 * or wont be and could be discarded under memory pressure. 759 */ 760 __u32 madv; 761 762 /** Whether the backing store still exists. */ 763 __u32 retained; 764 }; 765 766 /* flags */ 767 #define I915_OVERLAY_TYPE_MASK 0xff 768 #define I915_OVERLAY_YUV_PLANAR 0x01 769 #define I915_OVERLAY_YUV_PACKED 0x02 770 #define I915_OVERLAY_RGB 0x03 771 772 #define I915_OVERLAY_DEPTH_MASK 0xff00 773 #define I915_OVERLAY_RGB24 0x1000 774 #define I915_OVERLAY_RGB16 0x2000 775 #define I915_OVERLAY_RGB15 0x3000 776 #define I915_OVERLAY_YUV422 0x0100 777 #define I915_OVERLAY_YUV411 0x0200 778 #define I915_OVERLAY_YUV420 0x0300 779 #define I915_OVERLAY_YUV410 0x0400 780 781 #define I915_OVERLAY_SWAP_MASK 0xff0000 782 #define I915_OVERLAY_NO_SWAP 0x000000 783 #define I915_OVERLAY_UV_SWAP 0x010000 784 #define I915_OVERLAY_Y_SWAP 0x020000 785 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 786 787 #define I915_OVERLAY_FLAGS_MASK 0xff000000 788 #define I915_OVERLAY_ENABLE 0x01000000 789 790 struct drm_intel_overlay_put_image { 791 /* various flags and src format description */ 792 __u32 flags; 793 /* source picture description */ 794 __u32 bo_handle; 795 /* stride values and offsets are in bytes, buffer relative */ 796 __u16 stride_Y; /* stride for packed formats */ 797 __u16 stride_UV; 798 __u32 offset_Y; /* offset for packet formats */ 799 __u32 offset_U; 800 __u32 offset_V; 801 /* in pixels */ 802 __u16 src_width; 803 __u16 src_height; 804 /* to compensate the scaling factors for partially covered surfaces */ 805 __u16 src_scan_width; 806 __u16 src_scan_height; 807 /* output crtc description */ 808 __u32 crtc_id; 809 __u16 dst_x; 810 __u16 dst_y; 811 __u16 dst_width; 812 __u16 dst_height; 813 }; 814 815 /* flags */ 816 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 817 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 818 struct drm_intel_overlay_attrs { 819 __u32 flags; 820 __u32 color_key; 821 __s32 brightness; 822 __u32 contrast; 823 __u32 saturation; 824 __u32 gamma0; 825 __u32 gamma1; 826 __u32 gamma2; 827 __u32 gamma3; 828 __u32 gamma4; 829 __u32 gamma5; 830 }; 831 832 #endif /* _I915_DRM_H_ */ 833