1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _I915_DRM_H_ 28 #define _I915_DRM_H_ 29 30 /* Please note that modifications to all structs defined here are 31 * subject to backwards-compatibility constraints. 32 */ 33 #include <linux/types.h> 34 #include "drm.h" 35 36 /* Each region is a minimum of 16k, and there are at most 255 of them. 37 */ 38 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 39 * of chars for next/prev indices */ 40 #define I915_LOG_MIN_TEX_REGION_SIZE 14 41 42 typedef struct _drm_i915_init { 43 enum { 44 I915_INIT_DMA = 0x01, 45 I915_CLEANUP_DMA = 0x02, 46 I915_RESUME_DMA = 0x03 47 } func; 48 unsigned int mmio_offset; 49 int sarea_priv_offset; 50 unsigned int ring_start; 51 unsigned int ring_end; 52 unsigned int ring_size; 53 unsigned int front_offset; 54 unsigned int back_offset; 55 unsigned int depth_offset; 56 unsigned int w; 57 unsigned int h; 58 unsigned int pitch; 59 unsigned int pitch_bits; 60 unsigned int back_pitch; 61 unsigned int depth_pitch; 62 unsigned int cpp; 63 unsigned int chipset; 64 } drm_i915_init_t; 65 66 typedef struct _drm_i915_sarea { 67 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 68 int last_upload; /* last time texture was uploaded */ 69 int last_enqueue; /* last time a buffer was enqueued */ 70 int last_dispatch; /* age of the most recently dispatched buffer */ 71 int ctxOwner; /* last context to upload state */ 72 int texAge; 73 int pf_enabled; /* is pageflipping allowed? */ 74 int pf_active; 75 int pf_current_page; /* which buffer is being displayed? */ 76 int perf_boxes; /* performance boxes to be displayed */ 77 int width, height; /* screen size in pixels */ 78 79 drm_handle_t front_handle; 80 int front_offset; 81 int front_size; 82 83 drm_handle_t back_handle; 84 int back_offset; 85 int back_size; 86 87 drm_handle_t depth_handle; 88 int depth_offset; 89 int depth_size; 90 91 drm_handle_t tex_handle; 92 int tex_offset; 93 int tex_size; 94 int log_tex_granularity; 95 int pitch; 96 int rotation; /* 0, 90, 180 or 270 */ 97 int rotated_offset; 98 int rotated_size; 99 int rotated_pitch; 100 int virtualX, virtualY; 101 102 unsigned int front_tiled; 103 unsigned int back_tiled; 104 unsigned int depth_tiled; 105 unsigned int rotated_tiled; 106 unsigned int rotated2_tiled; 107 108 int pipeA_x; 109 int pipeA_y; 110 int pipeA_w; 111 int pipeA_h; 112 int pipeB_x; 113 int pipeB_y; 114 int pipeB_w; 115 int pipeB_h; 116 117 /* fill out some space for old userspace triple buffer */ 118 drm_handle_t unused_handle; 119 __u32 unused1, unused2, unused3; 120 121 /* buffer object handles for static buffers. May change 122 * over the lifetime of the client. 123 */ 124 __u32 front_bo_handle; 125 __u32 back_bo_handle; 126 __u32 unused_bo_handle; 127 __u32 depth_bo_handle; 128 129 } drm_i915_sarea_t; 130 131 /* due to userspace building against these headers we need some compat here */ 132 #define planeA_x pipeA_x 133 #define planeA_y pipeA_y 134 #define planeA_w pipeA_w 135 #define planeA_h pipeA_h 136 #define planeB_x pipeB_x 137 #define planeB_y pipeB_y 138 #define planeB_w pipeB_w 139 #define planeB_h pipeB_h 140 141 /* Flags for perf_boxes 142 */ 143 #define I915_BOX_RING_EMPTY 0x1 144 #define I915_BOX_FLIP 0x2 145 #define I915_BOX_WAIT 0x4 146 #define I915_BOX_TEXTURE_LOAD 0x8 147 #define I915_BOX_LOST_CONTEXT 0x10 148 149 /* I915 specific ioctls 150 * The device specific ioctl range is 0x40 to 0x79. 151 */ 152 #define DRM_I915_INIT 0x00 153 #define DRM_I915_FLUSH 0x01 154 #define DRM_I915_FLIP 0x02 155 #define DRM_I915_BATCHBUFFER 0x03 156 #define DRM_I915_IRQ_EMIT 0x04 157 #define DRM_I915_IRQ_WAIT 0x05 158 #define DRM_I915_GETPARAM 0x06 159 #define DRM_I915_SETPARAM 0x07 160 #define DRM_I915_ALLOC 0x08 161 #define DRM_I915_FREE 0x09 162 #define DRM_I915_INIT_HEAP 0x0a 163 #define DRM_I915_CMDBUFFER 0x0b 164 #define DRM_I915_DESTROY_HEAP 0x0c 165 #define DRM_I915_SET_VBLANK_PIPE 0x0d 166 #define DRM_I915_GET_VBLANK_PIPE 0x0e 167 #define DRM_I915_VBLANK_SWAP 0x0f 168 #define DRM_I915_HWS_ADDR 0x11 169 #define DRM_I915_GEM_INIT 0x13 170 #define DRM_I915_GEM_EXECBUFFER 0x14 171 #define DRM_I915_GEM_PIN 0x15 172 #define DRM_I915_GEM_UNPIN 0x16 173 #define DRM_I915_GEM_BUSY 0x17 174 #define DRM_I915_GEM_THROTTLE 0x18 175 #define DRM_I915_GEM_ENTERVT 0x19 176 #define DRM_I915_GEM_LEAVEVT 0x1a 177 #define DRM_I915_GEM_CREATE 0x1b 178 #define DRM_I915_GEM_PREAD 0x1c 179 #define DRM_I915_GEM_PWRITE 0x1d 180 #define DRM_I915_GEM_MMAP 0x1e 181 #define DRM_I915_GEM_SET_DOMAIN 0x1f 182 #define DRM_I915_GEM_SW_FINISH 0x20 183 #define DRM_I915_GEM_SET_TILING 0x21 184 #define DRM_I915_GEM_GET_TILING 0x22 185 #define DRM_I915_GEM_GET_APERTURE 0x23 186 #define DRM_I915_GEM_MMAP_GTT 0x24 187 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 188 189 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 190 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 191 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 192 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 193 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 194 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 195 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 196 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 197 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 198 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 199 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 200 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 201 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 202 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 203 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 204 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 205 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 206 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 207 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 208 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 209 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 210 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 211 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 212 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 213 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 214 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 215 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 216 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 217 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 218 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 219 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 220 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 221 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 222 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 223 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_intel_get_pipe_from_crtc_id) 224 225 /* Allow drivers to submit batchbuffers directly to hardware, relying 226 * on the security mechanisms provided by hardware. 227 */ 228 typedef struct drm_i915_batchbuffer { 229 int start; /* agp offset */ 230 int used; /* nr bytes in use */ 231 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 232 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 233 int num_cliprects; /* mulitpass with multiple cliprects? */ 234 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 235 } drm_i915_batchbuffer_t; 236 237 /* As above, but pass a pointer to userspace buffer which can be 238 * validated by the kernel prior to sending to hardware. 239 */ 240 typedef struct _drm_i915_cmdbuffer { 241 char __user *buf; /* pointer to userspace command buffer */ 242 int sz; /* nr bytes in buf */ 243 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 244 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 245 int num_cliprects; /* mulitpass with multiple cliprects? */ 246 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 247 } drm_i915_cmdbuffer_t; 248 249 /* Userspace can request & wait on irq's: 250 */ 251 typedef struct drm_i915_irq_emit { 252 int __user *irq_seq; 253 } drm_i915_irq_emit_t; 254 255 typedef struct drm_i915_irq_wait { 256 int irq_seq; 257 } drm_i915_irq_wait_t; 258 259 /* Ioctl to query kernel params: 260 */ 261 #define I915_PARAM_IRQ_ACTIVE 1 262 #define I915_PARAM_ALLOW_BATCHBUFFER 2 263 #define I915_PARAM_LAST_DISPATCH 3 264 #define I915_PARAM_CHIPSET_ID 4 265 #define I915_PARAM_HAS_GEM 5 266 #define I915_PARAM_NUM_FENCES_AVAIL 6 267 268 typedef struct drm_i915_getparam { 269 int param; 270 int __user *value; 271 } drm_i915_getparam_t; 272 273 /* Ioctl to set kernel params: 274 */ 275 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 276 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 277 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 278 #define I915_SETPARAM_NUM_USED_FENCES 4 279 280 typedef struct drm_i915_setparam { 281 int param; 282 int value; 283 } drm_i915_setparam_t; 284 285 /* A memory manager for regions of shared memory: 286 */ 287 #define I915_MEM_REGION_AGP 1 288 289 typedef struct drm_i915_mem_alloc { 290 int region; 291 int alignment; 292 int size; 293 int __user *region_offset; /* offset from start of fb or agp */ 294 } drm_i915_mem_alloc_t; 295 296 typedef struct drm_i915_mem_free { 297 int region; 298 int region_offset; 299 } drm_i915_mem_free_t; 300 301 typedef struct drm_i915_mem_init_heap { 302 int region; 303 int size; 304 int start; 305 } drm_i915_mem_init_heap_t; 306 307 /* Allow memory manager to be torn down and re-initialized (eg on 308 * rotate): 309 */ 310 typedef struct drm_i915_mem_destroy_heap { 311 int region; 312 } drm_i915_mem_destroy_heap_t; 313 314 /* Allow X server to configure which pipes to monitor for vblank signals 315 */ 316 #define DRM_I915_VBLANK_PIPE_A 1 317 #define DRM_I915_VBLANK_PIPE_B 2 318 319 typedef struct drm_i915_vblank_pipe { 320 int pipe; 321 } drm_i915_vblank_pipe_t; 322 323 /* Schedule buffer swap at given vertical blank: 324 */ 325 typedef struct drm_i915_vblank_swap { 326 drm_drawable_t drawable; 327 enum drm_vblank_seq_type seqtype; 328 unsigned int sequence; 329 } drm_i915_vblank_swap_t; 330 331 typedef struct drm_i915_hws_addr { 332 __u64 addr; 333 } drm_i915_hws_addr_t; 334 335 struct drm_i915_gem_init { 336 /** 337 * Beginning offset in the GTT to be managed by the DRM memory 338 * manager. 339 */ 340 __u64 gtt_start; 341 /** 342 * Ending offset in the GTT to be managed by the DRM memory 343 * manager. 344 */ 345 __u64 gtt_end; 346 }; 347 348 struct drm_i915_gem_create { 349 /** 350 * Requested size for the object. 351 * 352 * The (page-aligned) allocated size for the object will be returned. 353 */ 354 __u64 size; 355 /** 356 * Returned handle for the object. 357 * 358 * Object handles are nonzero. 359 */ 360 __u32 handle; 361 __u32 pad; 362 }; 363 364 struct drm_i915_gem_pread { 365 /** Handle for the object being read. */ 366 __u32 handle; 367 __u32 pad; 368 /** Offset into the object to read from */ 369 __u64 offset; 370 /** Length of data to read */ 371 __u64 size; 372 /** 373 * Pointer to write the data into. 374 * 375 * This is a fixed-size type for 32/64 compatibility. 376 */ 377 __u64 data_ptr; 378 }; 379 380 struct drm_i915_gem_pwrite { 381 /** Handle for the object being written to. */ 382 __u32 handle; 383 __u32 pad; 384 /** Offset into the object to write to */ 385 __u64 offset; 386 /** Length of data to write */ 387 __u64 size; 388 /** 389 * Pointer to read the data from. 390 * 391 * This is a fixed-size type for 32/64 compatibility. 392 */ 393 __u64 data_ptr; 394 }; 395 396 struct drm_i915_gem_mmap { 397 /** Handle for the object being mapped. */ 398 __u32 handle; 399 __u32 pad; 400 /** Offset in the object to map. */ 401 __u64 offset; 402 /** 403 * Length of data to map. 404 * 405 * The value will be page-aligned. 406 */ 407 __u64 size; 408 /** 409 * Returned pointer the data was mapped at. 410 * 411 * This is a fixed-size type for 32/64 compatibility. 412 */ 413 __u64 addr_ptr; 414 }; 415 416 struct drm_i915_gem_mmap_gtt { 417 /** Handle for the object being mapped. */ 418 __u32 handle; 419 __u32 pad; 420 /** 421 * Fake offset to use for subsequent mmap call 422 * 423 * This is a fixed-size type for 32/64 compatibility. 424 */ 425 __u64 offset; 426 }; 427 428 struct drm_i915_gem_set_domain { 429 /** Handle for the object */ 430 __u32 handle; 431 432 /** New read domains */ 433 __u32 read_domains; 434 435 /** New write domain */ 436 __u32 write_domain; 437 }; 438 439 struct drm_i915_gem_sw_finish { 440 /** Handle for the object */ 441 __u32 handle; 442 }; 443 444 struct drm_i915_gem_relocation_entry { 445 /** 446 * Handle of the buffer being pointed to by this relocation entry. 447 * 448 * It's appealing to make this be an index into the mm_validate_entry 449 * list to refer to the buffer, but this allows the driver to create 450 * a relocation list for state buffers and not re-write it per 451 * exec using the buffer. 452 */ 453 __u32 target_handle; 454 455 /** 456 * Value to be added to the offset of the target buffer to make up 457 * the relocation entry. 458 */ 459 __u32 delta; 460 461 /** Offset in the buffer the relocation entry will be written into */ 462 __u64 offset; 463 464 /** 465 * Offset value of the target buffer that the relocation entry was last 466 * written as. 467 * 468 * If the buffer has the same offset as last time, we can skip syncing 469 * and writing the relocation. This value is written back out by 470 * the execbuffer ioctl when the relocation is written. 471 */ 472 __u64 presumed_offset; 473 474 /** 475 * Target memory domains read by this operation. 476 */ 477 __u32 read_domains; 478 479 /** 480 * Target memory domains written by this operation. 481 * 482 * Note that only one domain may be written by the whole 483 * execbuffer operation, so that where there are conflicts, 484 * the application will get -EINVAL back. 485 */ 486 __u32 write_domain; 487 }; 488 489 /** @{ 490 * Intel memory domains 491 * 492 * Most of these just align with the various caches in 493 * the system and are used to flush and invalidate as 494 * objects end up cached in different domains. 495 */ 496 /** CPU cache */ 497 #define I915_GEM_DOMAIN_CPU 0x00000001 498 /** Render cache, used by 2D and 3D drawing */ 499 #define I915_GEM_DOMAIN_RENDER 0x00000002 500 /** Sampler cache, used by texture engine */ 501 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 502 /** Command queue, used to load batch buffers */ 503 #define I915_GEM_DOMAIN_COMMAND 0x00000008 504 /** Instruction cache, used by shader programs */ 505 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 506 /** Vertex address cache */ 507 #define I915_GEM_DOMAIN_VERTEX 0x00000020 508 /** GTT domain - aperture and scanout */ 509 #define I915_GEM_DOMAIN_GTT 0x00000040 510 /** @} */ 511 512 struct drm_i915_gem_exec_object { 513 /** 514 * User's handle for a buffer to be bound into the GTT for this 515 * operation. 516 */ 517 __u32 handle; 518 519 /** Number of relocations to be performed on this buffer */ 520 __u32 relocation_count; 521 /** 522 * Pointer to array of struct drm_i915_gem_relocation_entry containing 523 * the relocations to be performed in this buffer. 524 */ 525 __u64 relocs_ptr; 526 527 /** Required alignment in graphics aperture */ 528 __u64 alignment; 529 530 /** 531 * Returned value of the updated offset of the object, for future 532 * presumed_offset writes. 533 */ 534 __u64 offset; 535 }; 536 537 struct drm_i915_gem_execbuffer { 538 /** 539 * List of buffers to be validated with their relocations to be 540 * performend on them. 541 * 542 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 543 * 544 * These buffers must be listed in an order such that all relocations 545 * a buffer is performing refer to buffers that have already appeared 546 * in the validate list. 547 */ 548 __u64 buffers_ptr; 549 __u32 buffer_count; 550 551 /** Offset in the batchbuffer to start execution from. */ 552 __u32 batch_start_offset; 553 /** Bytes used in batchbuffer from batch_start_offset */ 554 __u32 batch_len; 555 __u32 DR1; 556 __u32 DR4; 557 __u32 num_cliprects; 558 /** This is a struct drm_clip_rect *cliprects */ 559 __u64 cliprects_ptr; 560 }; 561 562 struct drm_i915_gem_pin { 563 /** Handle of the buffer to be pinned. */ 564 __u32 handle; 565 __u32 pad; 566 567 /** alignment required within the aperture */ 568 __u64 alignment; 569 570 /** Returned GTT offset of the buffer. */ 571 __u64 offset; 572 }; 573 574 struct drm_i915_gem_unpin { 575 /** Handle of the buffer to be unpinned. */ 576 __u32 handle; 577 __u32 pad; 578 }; 579 580 struct drm_i915_gem_busy { 581 /** Handle of the buffer to check for busy */ 582 __u32 handle; 583 584 /** Return busy status (1 if busy, 0 if idle) */ 585 __u32 busy; 586 }; 587 588 #define I915_TILING_NONE 0 589 #define I915_TILING_X 1 590 #define I915_TILING_Y 2 591 592 #define I915_BIT_6_SWIZZLE_NONE 0 593 #define I915_BIT_6_SWIZZLE_9 1 594 #define I915_BIT_6_SWIZZLE_9_10 2 595 #define I915_BIT_6_SWIZZLE_9_11 3 596 #define I915_BIT_6_SWIZZLE_9_10_11 4 597 /* Not seen by userland */ 598 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 599 /* Seen by userland. */ 600 #define I915_BIT_6_SWIZZLE_9_17 6 601 #define I915_BIT_6_SWIZZLE_9_10_17 7 602 603 struct drm_i915_gem_set_tiling { 604 /** Handle of the buffer to have its tiling state updated */ 605 __u32 handle; 606 607 /** 608 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 609 * I915_TILING_Y). 610 * 611 * This value is to be set on request, and will be updated by the 612 * kernel on successful return with the actual chosen tiling layout. 613 * 614 * The tiling mode may be demoted to I915_TILING_NONE when the system 615 * has bit 6 swizzling that can't be managed correctly by GEM. 616 * 617 * Buffer contents become undefined when changing tiling_mode. 618 */ 619 __u32 tiling_mode; 620 621 /** 622 * Stride in bytes for the object when in I915_TILING_X or 623 * I915_TILING_Y. 624 */ 625 __u32 stride; 626 627 /** 628 * Returned address bit 6 swizzling required for CPU access through 629 * mmap mapping. 630 */ 631 __u32 swizzle_mode; 632 }; 633 634 struct drm_i915_gem_get_tiling { 635 /** Handle of the buffer to get tiling state for. */ 636 __u32 handle; 637 638 /** 639 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 640 * I915_TILING_Y). 641 */ 642 __u32 tiling_mode; 643 644 /** 645 * Returned address bit 6 swizzling required for CPU access through 646 * mmap mapping. 647 */ 648 __u32 swizzle_mode; 649 }; 650 651 struct drm_i915_gem_get_aperture { 652 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 653 __u64 aper_size; 654 655 /** 656 * Available space in the aperture used by i915_gem_execbuffer, in 657 * bytes 658 */ 659 __u64 aper_available_size; 660 }; 661 662 struct drm_i915_get_pipe_from_crtc_id { 663 /** ID of CRTC being requested **/ 664 __u32 crtc_id; 665 666 /** pipe of requested CRTC **/ 667 __u32 pipe; 668 }; 669 670 #endif /* _I915_DRM_H_ */ 671