1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _I915_DRM_H_ 28 #define _I915_DRM_H_ 29 30 #include "drm.h" 31 32 /* Please note that modifications to all structs defined here are 33 * subject to backwards-compatibility constraints. 34 */ 35 36 #ifdef __KERNEL__ 37 /* For use by IPS driver */ 38 extern unsigned long i915_read_mch_val(void); 39 extern bool i915_gpu_raise(void); 40 extern bool i915_gpu_lower(void); 41 extern bool i915_gpu_busy(void); 42 extern bool i915_gpu_turbo_disable(void); 43 #endif 44 45 /* Each region is a minimum of 16k, and there are at most 255 of them. 46 */ 47 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 48 * of chars for next/prev indices */ 49 #define I915_LOG_MIN_TEX_REGION_SIZE 14 50 51 typedef struct _drm_i915_init { 52 enum { 53 I915_INIT_DMA = 0x01, 54 I915_CLEANUP_DMA = 0x02, 55 I915_RESUME_DMA = 0x03 56 } func; 57 unsigned int mmio_offset; 58 int sarea_priv_offset; 59 unsigned int ring_start; 60 unsigned int ring_end; 61 unsigned int ring_size; 62 unsigned int front_offset; 63 unsigned int back_offset; 64 unsigned int depth_offset; 65 unsigned int w; 66 unsigned int h; 67 unsigned int pitch; 68 unsigned int pitch_bits; 69 unsigned int back_pitch; 70 unsigned int depth_pitch; 71 unsigned int cpp; 72 unsigned int chipset; 73 } drm_i915_init_t; 74 75 typedef struct _drm_i915_sarea { 76 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 77 int last_upload; /* last time texture was uploaded */ 78 int last_enqueue; /* last time a buffer was enqueued */ 79 int last_dispatch; /* age of the most recently dispatched buffer */ 80 int ctxOwner; /* last context to upload state */ 81 int texAge; 82 int pf_enabled; /* is pageflipping allowed? */ 83 int pf_active; 84 int pf_current_page; /* which buffer is being displayed? */ 85 int perf_boxes; /* performance boxes to be displayed */ 86 int width, height; /* screen size in pixels */ 87 88 drm_handle_t front_handle; 89 int front_offset; 90 int front_size; 91 92 drm_handle_t back_handle; 93 int back_offset; 94 int back_size; 95 96 drm_handle_t depth_handle; 97 int depth_offset; 98 int depth_size; 99 100 drm_handle_t tex_handle; 101 int tex_offset; 102 int tex_size; 103 int log_tex_granularity; 104 int pitch; 105 int rotation; /* 0, 90, 180 or 270 */ 106 int rotated_offset; 107 int rotated_size; 108 int rotated_pitch; 109 int virtualX, virtualY; 110 111 unsigned int front_tiled; 112 unsigned int back_tiled; 113 unsigned int depth_tiled; 114 unsigned int rotated_tiled; 115 unsigned int rotated2_tiled; 116 117 int pipeA_x; 118 int pipeA_y; 119 int pipeA_w; 120 int pipeA_h; 121 int pipeB_x; 122 int pipeB_y; 123 int pipeB_w; 124 int pipeB_h; 125 126 /* fill out some space for old userspace triple buffer */ 127 drm_handle_t unused_handle; 128 __u32 unused1, unused2, unused3; 129 130 /* buffer object handles for static buffers. May change 131 * over the lifetime of the client. 132 */ 133 __u32 front_bo_handle; 134 __u32 back_bo_handle; 135 __u32 unused_bo_handle; 136 __u32 depth_bo_handle; 137 138 } drm_i915_sarea_t; 139 140 /* due to userspace building against these headers we need some compat here */ 141 #define planeA_x pipeA_x 142 #define planeA_y pipeA_y 143 #define planeA_w pipeA_w 144 #define planeA_h pipeA_h 145 #define planeB_x pipeB_x 146 #define planeB_y pipeB_y 147 #define planeB_w pipeB_w 148 #define planeB_h pipeB_h 149 150 /* Flags for perf_boxes 151 */ 152 #define I915_BOX_RING_EMPTY 0x1 153 #define I915_BOX_FLIP 0x2 154 #define I915_BOX_WAIT 0x4 155 #define I915_BOX_TEXTURE_LOAD 0x8 156 #define I915_BOX_LOST_CONTEXT 0x10 157 158 /* I915 specific ioctls 159 * The device specific ioctl range is 0x40 to 0x79. 160 */ 161 #define DRM_I915_INIT 0x00 162 #define DRM_I915_FLUSH 0x01 163 #define DRM_I915_FLIP 0x02 164 #define DRM_I915_BATCHBUFFER 0x03 165 #define DRM_I915_IRQ_EMIT 0x04 166 #define DRM_I915_IRQ_WAIT 0x05 167 #define DRM_I915_GETPARAM 0x06 168 #define DRM_I915_SETPARAM 0x07 169 #define DRM_I915_ALLOC 0x08 170 #define DRM_I915_FREE 0x09 171 #define DRM_I915_INIT_HEAP 0x0a 172 #define DRM_I915_CMDBUFFER 0x0b 173 #define DRM_I915_DESTROY_HEAP 0x0c 174 #define DRM_I915_SET_VBLANK_PIPE 0x0d 175 #define DRM_I915_GET_VBLANK_PIPE 0x0e 176 #define DRM_I915_VBLANK_SWAP 0x0f 177 #define DRM_I915_HWS_ADDR 0x11 178 #define DRM_I915_GEM_INIT 0x13 179 #define DRM_I915_GEM_EXECBUFFER 0x14 180 #define DRM_I915_GEM_PIN 0x15 181 #define DRM_I915_GEM_UNPIN 0x16 182 #define DRM_I915_GEM_BUSY 0x17 183 #define DRM_I915_GEM_THROTTLE 0x18 184 #define DRM_I915_GEM_ENTERVT 0x19 185 #define DRM_I915_GEM_LEAVEVT 0x1a 186 #define DRM_I915_GEM_CREATE 0x1b 187 #define DRM_I915_GEM_PREAD 0x1c 188 #define DRM_I915_GEM_PWRITE 0x1d 189 #define DRM_I915_GEM_MMAP 0x1e 190 #define DRM_I915_GEM_SET_DOMAIN 0x1f 191 #define DRM_I915_GEM_SW_FINISH 0x20 192 #define DRM_I915_GEM_SET_TILING 0x21 193 #define DRM_I915_GEM_GET_TILING 0x22 194 #define DRM_I915_GEM_GET_APERTURE 0x23 195 #define DRM_I915_GEM_MMAP_GTT 0x24 196 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 197 #define DRM_I915_GEM_MADVISE 0x26 198 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 199 #define DRM_I915_OVERLAY_ATTRS 0x28 200 #define DRM_I915_GEM_EXECBUFFER2 0x29 201 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 202 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 203 #define DRM_I915_GEM_WAIT 0x2c 204 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 205 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 206 #define DRM_I915_GEM_SET_CACHEING 0x2f 207 #define DRM_I915_GEM_GET_CACHEING 0x30 208 #define DRM_I915_REG_READ 0x31 209 210 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 211 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 212 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 213 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 214 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 215 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 216 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 217 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 218 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 219 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 220 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 221 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 222 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 223 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 224 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 225 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 226 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 227 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 228 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 229 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 230 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 231 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 232 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 233 #define DRM_IOCTL_I915_GEM_SET_CACHEING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct drm_i915_gem_cacheing) 234 #define DRM_IOCTL_I915_GEM_GET_CACHEING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct drm_i915_gem_cacheing) 235 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 236 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 237 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 238 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 239 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 240 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 241 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 242 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 243 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 244 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 245 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 246 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 247 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 248 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 249 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 250 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 251 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 252 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 253 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 254 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 255 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 256 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 257 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 258 259 /* Allow drivers to submit batchbuffers directly to hardware, relying 260 * on the security mechanisms provided by hardware. 261 */ 262 typedef struct drm_i915_batchbuffer { 263 int start; /* agp offset */ 264 int used; /* nr bytes in use */ 265 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 266 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 267 int num_cliprects; /* mulitpass with multiple cliprects? */ 268 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 269 } drm_i915_batchbuffer_t; 270 271 /* As above, but pass a pointer to userspace buffer which can be 272 * validated by the kernel prior to sending to hardware. 273 */ 274 typedef struct _drm_i915_cmdbuffer { 275 char __user *buf; /* pointer to userspace command buffer */ 276 int sz; /* nr bytes in buf */ 277 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 278 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 279 int num_cliprects; /* mulitpass with multiple cliprects? */ 280 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 281 } drm_i915_cmdbuffer_t; 282 283 /* Userspace can request & wait on irq's: 284 */ 285 typedef struct drm_i915_irq_emit { 286 int __user *irq_seq; 287 } drm_i915_irq_emit_t; 288 289 typedef struct drm_i915_irq_wait { 290 int irq_seq; 291 } drm_i915_irq_wait_t; 292 293 /* Ioctl to query kernel params: 294 */ 295 #define I915_PARAM_IRQ_ACTIVE 1 296 #define I915_PARAM_ALLOW_BATCHBUFFER 2 297 #define I915_PARAM_LAST_DISPATCH 3 298 #define I915_PARAM_CHIPSET_ID 4 299 #define I915_PARAM_HAS_GEM 5 300 #define I915_PARAM_NUM_FENCES_AVAIL 6 301 #define I915_PARAM_HAS_OVERLAY 7 302 #define I915_PARAM_HAS_PAGEFLIPPING 8 303 #define I915_PARAM_HAS_EXECBUF2 9 304 #define I915_PARAM_HAS_BSD 10 305 #define I915_PARAM_HAS_BLT 11 306 #define I915_PARAM_HAS_RELAXED_FENCING 12 307 #define I915_PARAM_HAS_COHERENT_RINGS 13 308 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 309 #define I915_PARAM_HAS_RELAXED_DELTA 15 310 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 311 #define I915_PARAM_HAS_LLC 17 312 #define I915_PARAM_HAS_ALIASING_PPGTT 18 313 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 314 #define I915_PARAM_HAS_SEMAPHORES 20 315 316 typedef struct drm_i915_getparam { 317 int param; 318 int __user *value; 319 } drm_i915_getparam_t; 320 321 /* Ioctl to set kernel params: 322 */ 323 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 324 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 325 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 326 #define I915_SETPARAM_NUM_USED_FENCES 4 327 328 typedef struct drm_i915_setparam { 329 int param; 330 int value; 331 } drm_i915_setparam_t; 332 333 /* A memory manager for regions of shared memory: 334 */ 335 #define I915_MEM_REGION_AGP 1 336 337 typedef struct drm_i915_mem_alloc { 338 int region; 339 int alignment; 340 int size; 341 int __user *region_offset; /* offset from start of fb or agp */ 342 } drm_i915_mem_alloc_t; 343 344 typedef struct drm_i915_mem_free { 345 int region; 346 int region_offset; 347 } drm_i915_mem_free_t; 348 349 typedef struct drm_i915_mem_init_heap { 350 int region; 351 int size; 352 int start; 353 } drm_i915_mem_init_heap_t; 354 355 /* Allow memory manager to be torn down and re-initialized (eg on 356 * rotate): 357 */ 358 typedef struct drm_i915_mem_destroy_heap { 359 int region; 360 } drm_i915_mem_destroy_heap_t; 361 362 /* Allow X server to configure which pipes to monitor for vblank signals 363 */ 364 #define DRM_I915_VBLANK_PIPE_A 1 365 #define DRM_I915_VBLANK_PIPE_B 2 366 367 typedef struct drm_i915_vblank_pipe { 368 int pipe; 369 } drm_i915_vblank_pipe_t; 370 371 /* Schedule buffer swap at given vertical blank: 372 */ 373 typedef struct drm_i915_vblank_swap { 374 drm_drawable_t drawable; 375 enum drm_vblank_seq_type seqtype; 376 unsigned int sequence; 377 } drm_i915_vblank_swap_t; 378 379 typedef struct drm_i915_hws_addr { 380 __u64 addr; 381 } drm_i915_hws_addr_t; 382 383 struct drm_i915_gem_init { 384 /** 385 * Beginning offset in the GTT to be managed by the DRM memory 386 * manager. 387 */ 388 __u64 gtt_start; 389 /** 390 * Ending offset in the GTT to be managed by the DRM memory 391 * manager. 392 */ 393 __u64 gtt_end; 394 }; 395 396 struct drm_i915_gem_create { 397 /** 398 * Requested size for the object. 399 * 400 * The (page-aligned) allocated size for the object will be returned. 401 */ 402 __u64 size; 403 /** 404 * Returned handle for the object. 405 * 406 * Object handles are nonzero. 407 */ 408 __u32 handle; 409 __u32 pad; 410 }; 411 412 struct drm_i915_gem_pread { 413 /** Handle for the object being read. */ 414 __u32 handle; 415 __u32 pad; 416 /** Offset into the object to read from */ 417 __u64 offset; 418 /** Length of data to read */ 419 __u64 size; 420 /** 421 * Pointer to write the data into. 422 * 423 * This is a fixed-size type for 32/64 compatibility. 424 */ 425 __u64 data_ptr; 426 }; 427 428 struct drm_i915_gem_pwrite { 429 /** Handle for the object being written to. */ 430 __u32 handle; 431 __u32 pad; 432 /** Offset into the object to write to */ 433 __u64 offset; 434 /** Length of data to write */ 435 __u64 size; 436 /** 437 * Pointer to read the data from. 438 * 439 * This is a fixed-size type for 32/64 compatibility. 440 */ 441 __u64 data_ptr; 442 }; 443 444 struct drm_i915_gem_mmap { 445 /** Handle for the object being mapped. */ 446 __u32 handle; 447 __u32 pad; 448 /** Offset in the object to map. */ 449 __u64 offset; 450 /** 451 * Length of data to map. 452 * 453 * The value will be page-aligned. 454 */ 455 __u64 size; 456 /** 457 * Returned pointer the data was mapped at. 458 * 459 * This is a fixed-size type for 32/64 compatibility. 460 */ 461 __u64 addr_ptr; 462 }; 463 464 struct drm_i915_gem_mmap_gtt { 465 /** Handle for the object being mapped. */ 466 __u32 handle; 467 __u32 pad; 468 /** 469 * Fake offset to use for subsequent mmap call 470 * 471 * This is a fixed-size type for 32/64 compatibility. 472 */ 473 __u64 offset; 474 }; 475 476 struct drm_i915_gem_set_domain { 477 /** Handle for the object */ 478 __u32 handle; 479 480 /** New read domains */ 481 __u32 read_domains; 482 483 /** New write domain */ 484 __u32 write_domain; 485 }; 486 487 struct drm_i915_gem_sw_finish { 488 /** Handle for the object */ 489 __u32 handle; 490 }; 491 492 struct drm_i915_gem_relocation_entry { 493 /** 494 * Handle of the buffer being pointed to by this relocation entry. 495 * 496 * It's appealing to make this be an index into the mm_validate_entry 497 * list to refer to the buffer, but this allows the driver to create 498 * a relocation list for state buffers and not re-write it per 499 * exec using the buffer. 500 */ 501 __u32 target_handle; 502 503 /** 504 * Value to be added to the offset of the target buffer to make up 505 * the relocation entry. 506 */ 507 __u32 delta; 508 509 /** Offset in the buffer the relocation entry will be written into */ 510 __u64 offset; 511 512 /** 513 * Offset value of the target buffer that the relocation entry was last 514 * written as. 515 * 516 * If the buffer has the same offset as last time, we can skip syncing 517 * and writing the relocation. This value is written back out by 518 * the execbuffer ioctl when the relocation is written. 519 */ 520 __u64 presumed_offset; 521 522 /** 523 * Target memory domains read by this operation. 524 */ 525 __u32 read_domains; 526 527 /** 528 * Target memory domains written by this operation. 529 * 530 * Note that only one domain may be written by the whole 531 * execbuffer operation, so that where there are conflicts, 532 * the application will get -EINVAL back. 533 */ 534 __u32 write_domain; 535 }; 536 537 /** @{ 538 * Intel memory domains 539 * 540 * Most of these just align with the various caches in 541 * the system and are used to flush and invalidate as 542 * objects end up cached in different domains. 543 */ 544 /** CPU cache */ 545 #define I915_GEM_DOMAIN_CPU 0x00000001 546 /** Render cache, used by 2D and 3D drawing */ 547 #define I915_GEM_DOMAIN_RENDER 0x00000002 548 /** Sampler cache, used by texture engine */ 549 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 550 /** Command queue, used to load batch buffers */ 551 #define I915_GEM_DOMAIN_COMMAND 0x00000008 552 /** Instruction cache, used by shader programs */ 553 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 554 /** Vertex address cache */ 555 #define I915_GEM_DOMAIN_VERTEX 0x00000020 556 /** GTT domain - aperture and scanout */ 557 #define I915_GEM_DOMAIN_GTT 0x00000040 558 /** @} */ 559 560 struct drm_i915_gem_exec_object { 561 /** 562 * User's handle for a buffer to be bound into the GTT for this 563 * operation. 564 */ 565 __u32 handle; 566 567 /** Number of relocations to be performed on this buffer */ 568 __u32 relocation_count; 569 /** 570 * Pointer to array of struct drm_i915_gem_relocation_entry containing 571 * the relocations to be performed in this buffer. 572 */ 573 __u64 relocs_ptr; 574 575 /** Required alignment in graphics aperture */ 576 __u64 alignment; 577 578 /** 579 * Returned value of the updated offset of the object, for future 580 * presumed_offset writes. 581 */ 582 __u64 offset; 583 }; 584 585 struct drm_i915_gem_execbuffer { 586 /** 587 * List of buffers to be validated with their relocations to be 588 * performend on them. 589 * 590 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 591 * 592 * These buffers must be listed in an order such that all relocations 593 * a buffer is performing refer to buffers that have already appeared 594 * in the validate list. 595 */ 596 __u64 buffers_ptr; 597 __u32 buffer_count; 598 599 /** Offset in the batchbuffer to start execution from. */ 600 __u32 batch_start_offset; 601 /** Bytes used in batchbuffer from batch_start_offset */ 602 __u32 batch_len; 603 __u32 DR1; 604 __u32 DR4; 605 __u32 num_cliprects; 606 /** This is a struct drm_clip_rect *cliprects */ 607 __u64 cliprects_ptr; 608 }; 609 610 struct drm_i915_gem_exec_object2 { 611 /** 612 * User's handle for a buffer to be bound into the GTT for this 613 * operation. 614 */ 615 __u32 handle; 616 617 /** Number of relocations to be performed on this buffer */ 618 __u32 relocation_count; 619 /** 620 * Pointer to array of struct drm_i915_gem_relocation_entry containing 621 * the relocations to be performed in this buffer. 622 */ 623 __u64 relocs_ptr; 624 625 /** Required alignment in graphics aperture */ 626 __u64 alignment; 627 628 /** 629 * Returned value of the updated offset of the object, for future 630 * presumed_offset writes. 631 */ 632 __u64 offset; 633 634 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 635 __u64 flags; 636 __u64 rsvd1; 637 __u64 rsvd2; 638 }; 639 640 struct drm_i915_gem_execbuffer2 { 641 /** 642 * List of gem_exec_object2 structs 643 */ 644 __u64 buffers_ptr; 645 __u32 buffer_count; 646 647 /** Offset in the batchbuffer to start execution from. */ 648 __u32 batch_start_offset; 649 /** Bytes used in batchbuffer from batch_start_offset */ 650 __u32 batch_len; 651 __u32 DR1; 652 __u32 DR4; 653 __u32 num_cliprects; 654 /** This is a struct drm_clip_rect *cliprects */ 655 __u64 cliprects_ptr; 656 #define I915_EXEC_RING_MASK (7<<0) 657 #define I915_EXEC_DEFAULT (0<<0) 658 #define I915_EXEC_RENDER (1<<0) 659 #define I915_EXEC_BSD (2<<0) 660 #define I915_EXEC_BLT (3<<0) 661 662 /* Used for switching the constants addressing mode on gen4+ RENDER ring. 663 * Gen6+ only supports relative addressing to dynamic state (default) and 664 * absolute addressing. 665 * 666 * These flags are ignored for the BSD and BLT rings. 667 */ 668 #define I915_EXEC_CONSTANTS_MASK (3<<6) 669 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 670 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 671 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 672 __u64 flags; 673 __u64 rsvd1; /* now used for context info */ 674 __u64 rsvd2; 675 }; 676 677 /** Resets the SO write offset registers for transform feedback on gen7. */ 678 #define I915_EXEC_GEN7_SOL_RESET (1<<8) 679 680 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 681 #define i915_execbuffer2_set_context_id(eb2, context) \ 682 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 683 #define i915_execbuffer2_get_context_id(eb2) \ 684 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 685 686 struct drm_i915_gem_pin { 687 /** Handle of the buffer to be pinned. */ 688 __u32 handle; 689 __u32 pad; 690 691 /** alignment required within the aperture */ 692 __u64 alignment; 693 694 /** Returned GTT offset of the buffer. */ 695 __u64 offset; 696 }; 697 698 struct drm_i915_gem_unpin { 699 /** Handle of the buffer to be unpinned. */ 700 __u32 handle; 701 __u32 pad; 702 }; 703 704 struct drm_i915_gem_busy { 705 /** Handle of the buffer to check for busy */ 706 __u32 handle; 707 708 /** Return busy status (1 if busy, 0 if idle). 709 * The high word is used to indicate on which rings the object 710 * currently resides: 711 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) 712 */ 713 __u32 busy; 714 }; 715 716 #define I915_CACHEING_NONE 0 717 #define I915_CACHEING_CACHED 1 718 719 struct drm_i915_gem_cacheing { 720 /** 721 * Handle of the buffer to set/get the cacheing level of. */ 722 __u32 handle; 723 724 /** 725 * Cacheing level to apply or return value 726 * 727 * bits0-15 are for generic cacheing control (i.e. the above defined 728 * values). bits16-31 are reserved for platform-specific variations 729 * (e.g. l3$ caching on gen7). */ 730 __u32 cacheing; 731 }; 732 733 #define I915_TILING_NONE 0 734 #define I915_TILING_X 1 735 #define I915_TILING_Y 2 736 737 #define I915_BIT_6_SWIZZLE_NONE 0 738 #define I915_BIT_6_SWIZZLE_9 1 739 #define I915_BIT_6_SWIZZLE_9_10 2 740 #define I915_BIT_6_SWIZZLE_9_11 3 741 #define I915_BIT_6_SWIZZLE_9_10_11 4 742 /* Not seen by userland */ 743 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 744 /* Seen by userland. */ 745 #define I915_BIT_6_SWIZZLE_9_17 6 746 #define I915_BIT_6_SWIZZLE_9_10_17 7 747 748 struct drm_i915_gem_set_tiling { 749 /** Handle of the buffer to have its tiling state updated */ 750 __u32 handle; 751 752 /** 753 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 754 * I915_TILING_Y). 755 * 756 * This value is to be set on request, and will be updated by the 757 * kernel on successful return with the actual chosen tiling layout. 758 * 759 * The tiling mode may be demoted to I915_TILING_NONE when the system 760 * has bit 6 swizzling that can't be managed correctly by GEM. 761 * 762 * Buffer contents become undefined when changing tiling_mode. 763 */ 764 __u32 tiling_mode; 765 766 /** 767 * Stride in bytes for the object when in I915_TILING_X or 768 * I915_TILING_Y. 769 */ 770 __u32 stride; 771 772 /** 773 * Returned address bit 6 swizzling required for CPU access through 774 * mmap mapping. 775 */ 776 __u32 swizzle_mode; 777 }; 778 779 struct drm_i915_gem_get_tiling { 780 /** Handle of the buffer to get tiling state for. */ 781 __u32 handle; 782 783 /** 784 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 785 * I915_TILING_Y). 786 */ 787 __u32 tiling_mode; 788 789 /** 790 * Returned address bit 6 swizzling required for CPU access through 791 * mmap mapping. 792 */ 793 __u32 swizzle_mode; 794 }; 795 796 struct drm_i915_gem_get_aperture { 797 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 798 __u64 aper_size; 799 800 /** 801 * Available space in the aperture used by i915_gem_execbuffer, in 802 * bytes 803 */ 804 __u64 aper_available_size; 805 }; 806 807 struct drm_i915_get_pipe_from_crtc_id { 808 /** ID of CRTC being requested **/ 809 __u32 crtc_id; 810 811 /** pipe of requested CRTC **/ 812 __u32 pipe; 813 }; 814 815 #define I915_MADV_WILLNEED 0 816 #define I915_MADV_DONTNEED 1 817 #define __I915_MADV_PURGED 2 /* internal state */ 818 819 struct drm_i915_gem_madvise { 820 /** Handle of the buffer to change the backing store advice */ 821 __u32 handle; 822 823 /* Advice: either the buffer will be needed again in the near future, 824 * or wont be and could be discarded under memory pressure. 825 */ 826 __u32 madv; 827 828 /** Whether the backing store still exists. */ 829 __u32 retained; 830 }; 831 832 /* flags */ 833 #define I915_OVERLAY_TYPE_MASK 0xff 834 #define I915_OVERLAY_YUV_PLANAR 0x01 835 #define I915_OVERLAY_YUV_PACKED 0x02 836 #define I915_OVERLAY_RGB 0x03 837 838 #define I915_OVERLAY_DEPTH_MASK 0xff00 839 #define I915_OVERLAY_RGB24 0x1000 840 #define I915_OVERLAY_RGB16 0x2000 841 #define I915_OVERLAY_RGB15 0x3000 842 #define I915_OVERLAY_YUV422 0x0100 843 #define I915_OVERLAY_YUV411 0x0200 844 #define I915_OVERLAY_YUV420 0x0300 845 #define I915_OVERLAY_YUV410 0x0400 846 847 #define I915_OVERLAY_SWAP_MASK 0xff0000 848 #define I915_OVERLAY_NO_SWAP 0x000000 849 #define I915_OVERLAY_UV_SWAP 0x010000 850 #define I915_OVERLAY_Y_SWAP 0x020000 851 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 852 853 #define I915_OVERLAY_FLAGS_MASK 0xff000000 854 #define I915_OVERLAY_ENABLE 0x01000000 855 856 struct drm_intel_overlay_put_image { 857 /* various flags and src format description */ 858 __u32 flags; 859 /* source picture description */ 860 __u32 bo_handle; 861 /* stride values and offsets are in bytes, buffer relative */ 862 __u16 stride_Y; /* stride for packed formats */ 863 __u16 stride_UV; 864 __u32 offset_Y; /* offset for packet formats */ 865 __u32 offset_U; 866 __u32 offset_V; 867 /* in pixels */ 868 __u16 src_width; 869 __u16 src_height; 870 /* to compensate the scaling factors for partially covered surfaces */ 871 __u16 src_scan_width; 872 __u16 src_scan_height; 873 /* output crtc description */ 874 __u32 crtc_id; 875 __u16 dst_x; 876 __u16 dst_y; 877 __u16 dst_width; 878 __u16 dst_height; 879 }; 880 881 /* flags */ 882 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 883 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 884 struct drm_intel_overlay_attrs { 885 __u32 flags; 886 __u32 color_key; 887 __s32 brightness; 888 __u32 contrast; 889 __u32 saturation; 890 __u32 gamma0; 891 __u32 gamma1; 892 __u32 gamma2; 893 __u32 gamma3; 894 __u32 gamma4; 895 __u32 gamma5; 896 }; 897 898 /* 899 * Intel sprite handling 900 * 901 * Color keying works with a min/mask/max tuple. Both source and destination 902 * color keying is allowed. 903 * 904 * Source keying: 905 * Sprite pixels within the min & max values, masked against the color channels 906 * specified in the mask field, will be transparent. All other pixels will 907 * be displayed on top of the primary plane. For RGB surfaces, only the min 908 * and mask fields will be used; ranged compares are not allowed. 909 * 910 * Destination keying: 911 * Primary plane pixels that match the min value, masked against the color 912 * channels specified in the mask field, will be replaced by corresponding 913 * pixels from the sprite plane. 914 * 915 * Note that source & destination keying are exclusive; only one can be 916 * active on a given plane. 917 */ 918 919 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 920 #define I915_SET_COLORKEY_DESTINATION (1<<1) 921 #define I915_SET_COLORKEY_SOURCE (1<<2) 922 struct drm_intel_sprite_colorkey { 923 __u32 plane_id; 924 __u32 min_value; 925 __u32 channel_mask; 926 __u32 max_value; 927 __u32 flags; 928 }; 929 930 struct drm_i915_gem_wait { 931 /** Handle of BO we shall wait on */ 932 __u32 bo_handle; 933 __u32 flags; 934 /** Number of nanoseconds to wait, Returns time remaining. */ 935 __s64 timeout_ns; 936 }; 937 938 struct drm_i915_gem_context_create { 939 /* output: id of new context*/ 940 __u32 ctx_id; 941 __u32 pad; 942 }; 943 944 struct drm_i915_gem_context_destroy { 945 __u32 ctx_id; 946 __u32 pad; 947 }; 948 949 struct drm_i915_reg_read { 950 __u64 offset; 951 __u64 val; /* Return value */ 952 }; 953 #endif /* _I915_DRM_H_ */ 954